Assignment 1

Digital Logical Circuits

The gates are available in integrated form and the digital integrated circuits (ICs) are most
commonly used in complex digital circuit design. The logical gates can be designed in
different methods. Therefore there are different types of logical families. The unipolar and
bipolar logical families are the main logical families.

 Classification of Digital Logical Circuits

Digital Logical Circuits

Bipolar Unipolar

Standard Unsaturated PMOS & NMOS CMOS

 Characteristics of Digital Logical Circuits

The Characteristics of logical circuits are dependent on performance parameters.
The main are given below:-

1. Speed of operation
2. Power dissipation
3. Voltage, Current parameters
4. Cost
5. Noise immunity
6. Availability

 2 Input AND Gate

7408
 2 Input OR Gate

 2 Input NOT Gate

 2 Input NAND Gate

7400

 Different Logical Gates and their Truth Table:-

1. Representation of Logical Level

Logic 0 Logic 1

False True
Open Switch Close Switch
Low Voltage High Voltage
No Yes
Off On
2. Gates with Boolean Algebra(equation) and Truth Table.

a. OR Gate

A B X=A+B
0 0 0
0 1 1
1 0 1
1 1 1

The equation => X+A OR B

= A+B ; X= Output

A,B = Inputs

b. AND Gate

The equation => X= A.B

A B X=A.B

0 0 0
0 1 0
1 0 0
1 1 1

X= Output , A,B= Input

c. NOT Gate

A X=Â=A’

0 1
1 0

X= Output , A= Input

d. NOR Gate

A B X=(A+B)

0 0 1
0 1 0
1 0 0
1 1 0

The equation => X= A+B = (A+B)’ X= Output, A,B= Input

e. NAND Gate

A B X= A+B= (AB)’

0 0 1
0 1 1
1 0 1
1 1 0

The equation => X= A+B= (AB)’ X= Output, A,B= Input

f. Xclusive OR Gate (XOR Gate)

 A B X= A+B

0 0 0
0 1 1
1 0 1
1 1 0

The equation => X= A+B X= Output, A,B= Input

g. Exclusive NOR Gate ( Ex NOR Gate)

A B X=A+B

0 0 1
0 1 0
1 0 0
1 1 1

The equation => X=A+B X= Output, A,B= Input

Assignment 2

Multiplexers
A multiplexers is a combinational circuit that receives binary information from one of 2 nd
input data lines and directs it to a single output line . the selection of a particular input data
line for the output is determined by a set of selection inputs . A 2 nd to 1st multiplexers has
2nd input data lines and n input selection lines whose bit combinations determine which
input data are selected for the output .

A 4 to 1 line multiplexer is shown in fig2 . each of the four inputs I0 through I3 is applied to
one input of an AND gate. The two selection inputs S1 and S0 are decoded to select a
particular AND gate . The outputs of the AND gates are applied to a single OR gate to
provide the single output. To demonstrate
The circuit operation , consider the case when S1 S0 = 10 the AND gate associated with
input I2 has two of its input equal to 1. The Third input of the gate is connected to I2. The
other three AND gates have at least one input equal to 0, which makes their output equal to
0.
The or gate output is now equal to the value of I2, thus providing a path from the selected
input to the output.
The 4 to 1 line multiplexers in figure has six inputs and one output . A truth table describing
the circuits needs 64 rows since six input variables can have 24 binary combinations.

 Diagramatic Representation of 4 to 1 multiplexer

X

S3

S2 Z

S1

S0
 Truth table of 4 to 1 Multiplexer

X Y Z
0 0 S0
0 1 S1
1 0 S2
1 1 S3

 3 Input AND Gate :-

 Truth table of 3 input AND:-

A B C Y

0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

Assignment 3
Decoders and Encoders
 Decoders

Discrete quantities of information are represented in digital computers with

binary codes. A binary code of n bits is capable of representing up to 2n
distinct elements of the coded information. A decoder is a combinational
circuits that converts binary information from the n coded inputs to a
maximum of 2n inique outputs. If the n-bits coded information has unused bit
combinations, the decoder may have less than 2n outputs.

The decoders presented in this section are called n-ts-m-line decoders , where
m=<2n . Their purpose is to generate the 2n( or fewer) binary combinations of
the n input variables. A decoder has n inputs and m outputs and is also referred
to as an n*m decoder.

The logical diagram of 3 to 8 line decoder. The three data inputs A0,A1 and
A2 are decoded into eight outputs , each output representing one of the
combinations of the three binary outputs each output representing one of the
combination of the three binary input variables. The three inverters provide the
component of the binary combinations . A particular application of this
decoder is a binary to octal conversion. The input variable represents a binary
number and the outputs represent the eight digits of the octal number system.

1. Decoder
N=2 => 2n = 2^2 = 4 numbers

Truth table

A0 A1 D0 D1 D2 D3

0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

Diagram:-
 A0

A1
DO

D1

D2

D3

Encoders

An encoder is a digital circuit that performs the inverse operation of a decoder.

An encoder has 2n (or less) input lines and n-output lines. The output lines
generate the binary code corresponding to the input value. An example of an
encoder is the octal to binary encoder, whose truth table is given in table
below . it has eight inputs , one of each of the octal digits , and three outputs
that generate the corresponding binary number. It is assumed that only one
input has a value of 1 at any given time , otherwise, the circuit has null/ no
meaning.
The encoder can be implemented with OR gates whose inputs are determined
directly from the truth table output A0 = 1 if the octal digital input is 1 or can
be expressed by the following Boolean functions:

A0= D1+D2+D3+D4
A1= D2+D3+D6+D7
A2= D4+D5+D6+D7

The encoder can be implemented with three OR Gates.

 Diagram:-
 D1

D2

D3
Output0

Output1

 Truth Table:-

D0 D1 D2 D3 A0 A1

1 0 0 0 0 0
0 0 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1

A0= D2+D3
A1= D1+D3

Assignment 4

Comparators
A comparator is a combinational circuit that compares the magnitude of two
numbers (A and B) and generates one of the following outputs. A=B, A<B, &
A>B

The block diagram of a single bit magnitude comparator is shown below :-

A0 Single Bit Magnitude A0>B0

B0 Comparator A0=B0
A0<B0
 To implement the comparator , the XNOR Gates and AND gates are used.
The property of the XNOR gates can be used to find weather the two
binary digits are equal or not, and the AND Gates are used to find
wheather a binary digit is less than or greater than another bit . Xnor gates
have two inputs A. & B. If A.!=B., then output will be ‘0’. It has two AND
gates, one with A. And B. As inputs and another with A. And B. As their
inputs. The AND gate output is ‘1’ if A.>B. (i.e A.=1 and B.=0) and ‘0’ if
A.<B. ( i.e A.=0, B.=1)
And ‘0’ of A.>B. ( i.e A.=1 and B.=0)

 Application of Comparator:-

1. Comparators are often used as part of the Address decoding circuit in

computers to select a specific input or output device for the storage of data
2. They are used to actuate circuitry derive the physical variable towards the
reference value.
3. They are also used in control applications.

 A(An An-1..........A1 A0)

 B(Bn Bn-1..........B1 B0)

 Truth Table:-

A B f(A==B)

0 0 1
0 1 0
1 0 0
1 1 1

 Truth Table:-

A B f(A>B) f(A<B)

0 0 0 0
0 1 0 1
1 0 1 0
1 1 0 0

 F(A==B) = A+B

Also
 f(A<B) = f(A= = B)* f(A>B)

An>Bn
A==Bn An-1>Bn-1 A>B

Assignment 5

Adder Subtractor:-
The Addition and Subtraction operations can be comb ined into one common circuit by including an exclusive –
OR gate with each full-adder. A 4 bit The mode input Cin control is the operation. When Cin=0 the circuit is an
adder and when Cin =1 the circuit becomes a subtractor. Each exclusive –OR gate receives input Cin and one of
the inputs of B when Cin=0. We have B X-OR 0 =B. The full adder receive the value of B when Cin=0. The input
carry is 0, and the circuit performs A plus B when Cin=1 we have B X-OR 1=B’ and C0=1. The B inputs are all
complemented and a1 is added through the input carry. The circuit performs the operation A plus the 2’s
complement of B. For unsigned numbers, this given A-B if A>=B or the 2’s complement of (B-A) if A<B for
Signed Numbers, the Result is A-B provided that there is no overflow.

A ( A4 A3 A2 A1 )

B ( B4 B3 B2 B1 )

TRUTH TABLE:-

A B X
0 0 0
0 1 1
1 0 1
1 1 0
From Figure:-

If , B4=1 O/P=1

B3=0 O/P=0

B2=1 O/P=1

B1=1 O/P=1

When:- Cin =0
Then B

B4=1 O/P=0

B3=1 O/P=0
 B2=0 O/P=1

B1=1 O/P=1

Pin Diagran of 7483:-

Circuit Diagram:-
B4

B3

B2

B1
A4
A3
A2
A1

Cin
Cout

sum4
sum3
sum2
sum1
 Assignment 6

LOGIC UNIT
Binary Logic deals with binary variables and with operations that assume logical meaning. It is used to
describe, in algebraic or tabular form, the manipulation and processing of binary information. The
manipulation is done by logic circuits called gates. Gates are block of hardware that produce Signals of binary 1
or 0 when input logic requirements are satisfied. The input output relationship of the binary variables for each
gate can be represented in tabular form by a truth table. The basic logic gates are AND and Inclusive –OR
with Multiple inputs and NOT with a Single Input.

All the logic gates can be generated using a logic unit comprising of the basic logic Gates
AND, OR and NOT. There is an inverter for Input x and y to generate its complement x’ and y’ respectively. An
AND Gate is used to get the term xy , x’y, xy’ and x’y’ and OR Gate is used to combine the two terms to get the
output z.

1. AND

Z=X.Y

2. OR

Z=X+Y = XY’+XY+XY+X’Y = X(Y’+Y) + Y(X+X’) = X+Y

3. NAND

Z=(XY)’= XY’+X’Y’+X’Y’+X’Y = Y’(X+X’)+X’(Y’+Y) = X’+Y’ = (XY)’

4. NOR

Z=(X+Y)’

5. XOR

Z= X X-OR Y = X’Y +XY’

 6. XNOR

Z=(X X-OR Y)’ = X’Y +XY’

7. NOT
Z=X’ or Z=Y’

8. Buffer
Z=X or Z=Y
X

S3

S2 Z

S1

S0
F(x,y)=m3s3+m2s2+m1s1+m0s0 ; where m3=XY, m2= XY’, m1=X’Y, m0=X’Y’

TRUTH TABLE:-

S3 S2 S1 S0 LOGIC
1 0 0 0 AND
1 1 1 0 OR
0 1 1 1 NAND
0 0 0 1 NOR
0 1 1 0 XOR
1 0 0 1 XNOR

Assignment 7

BCD Adder
BCD Adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in
BCD.A BCD adder must include correction logic in its internal construction consider the
arithmetic addition of two decimal digits in BCD, together with a possible carry from a
previous stage since each input digit does not exceed 9, the output sum can not be greater
than 9+9+1=19. The 1 in the sum being an input carry. Suppose that we apply two BCD digits
to a 4 bit binary adder.The adder will form the sum in binary and produce a result that may
range from the sum in binary and produce a result that may range from 0 to 19. These
binary numbers are listed in the table given below.

Derivation of BCD Adder:

Decimal Binary BCD Sum

0 0000 0000
1 0001 0001
2 0010 0010
3 0011 0011
4 0100 0100
5 0101 0101
6 0110 0110
7 0111 0111
8 1000 1000
9 1001 1001
10 1010 00010000
11 1011 00010001
12 1100 00010010
13 1101 00010011
14 1110 00010100
15 1111 00010101
16 10000 00010110
 17 10001 00010111
18 10010 00011000
19 10011 00011001

The second column in the table lists the binary sums as they appear in the outputs of a 4 bit binary
adder. The output sum of two decimal numbers must be represented in BCD and should appear in
the form listed in the third column of the table. The problem is to find a simple rule by which binary
number in second column can be converted to the correct BCD digit representation. When the
binary number is equal to or less than 1001, the corresponding BCD numbers are identical and
therefore no conversion is needed. When the binary numbers are greater than 1001, the addition of
binary 6 (0110) to the binary number converts it to the correct BCD representation and also produce
and output carry.

A2 A1
A4
A3

B4
B3
B2
B1

GND
Cout

S4
S3
S2
S1

Assignment 8

Arithmetic Unit
The basic component of an arithmetic circuit is the parallel adder. By controlling the data inputs to
the adder, it is possible to obtain different types of arithmetic operations. The diagram of a 4 bit
arithmetic circuit is shown in the figure given below.
It has four parallel adder circuits that constitute the 4 bit adder and four multiplexers for choosing
operations. These are two 4 bit inputs A (X 3X2X1X0) and B (Y3Y2Y1Y0) and a 4-bit output K (K 3K2K1K0).
The four inputs from A (X3X2X1X0) go directly to the X inputs of the binary adder. Each of the four
inputs from B (Y3Y2Y1Y0) are connected to the data inputs are also receive the component of B
(Y3Y2Y1Y0). The other two data inputs are connected to logic-0 and logic-1. Logic-0 is a fixed voltage
value and the logic-1 signal can be generated through an inverter whose input is 0. The four
Multiplexers are connected and controlled by two selection inputs S 1 and S0. The input carry Cin goes
to the carry input of FA in the last significant position.

The output of the binary adder is calculated from the following arithmetic sum:

K= A+Y+ Cin

Where A is the 4-bit binary number at the X input and Y is the 4-bit binary number at the Y input of
the binary adder. Cin is the input carry, which can be equal to 0 or 1. Note that the symbol + in the
equation above denotes an arithmetic plus. By controlling the value of Y with the two selection
inputs S1 and S0 and making Cin equal to 0 or 1, it is possible to generate the eight arithmetic
operations listed in the following table:
 S1 S2 Cin Y K=A+Y+Cin Operation
0 0 0 B K=A+B Addition
0 0 1 B K=A+B+1 Addition with carry
0 1 0 B’ K=A+B’ Subtraction with carry
0 1 1 B’ K=A+B’+1 Subtraction
1 0 0 1 K=A-1 Decrement
1 0 1 1 K=A Transfer
1 1 0 0 K=A Transfer
1 1 1 0 K=A+1 Increment

Pin Configuration of Multiplexer:

Assignment 9

Read Write Operation using RAM ICs

A RAM chip is better suited for communication with the CPU if it has one or more control inputs that
select the chip only when needed. Another common feature is bidirectional data that allows the
transfer of data either from memory to CPU during the read operation or from CPU to memory
during the write operation. A bidirectional bus can be constructed with three state buffers. A three-
state buffer output can be placed in one of three possible states: a signal equivalent to logic 1 and 0
or high impedance state. The logic 1 and 0 are normal digital signals. The high impedance state
behaves like an open circuit, which means that the output does not carry a signal and has no logic
significance.

RAM Chip Configuration:

The block diagram of a RAM is shown above. The unit is in operation only when CE=1 and CE’=0. If
the select inputs are not enabled, or if they are enabled but the read or write inputs are not enabled,
the memory is inhibited and its data bus is in a high impedance state. When CE’ is at low voltage
then only the memory can be placed in a read or write mode. When the WR mode is enabled, the
memory stores a byte from the data bus into a location specified by address input lines when the R
input is enabled of the selected byte is placed into the data bus. The R and WR signals control the
memory operation as well as the bus buffers associated with the bidirectional data bus. The function
table listed below specifies the operation of the RAM chip.

Function Table:

Input
CE’ WR’ Function Output
L L Write Input data complement
L H Read Addressed word complement
H L Input Not Defined
H H Hold Open

Assignment 10

To cascade two RAM ICs for vertical and horizontal expansion

The large memory can be constructed by expanding some small size chips in either horizontally or
vertically. In horizontal expansion, word is increased, whereas in vertical expansion, number of
locations is increased.

For example: two RAM chips each of size 16 X 4 is given

1. It can be horizontally expanded to obtain a large memory of size 16 X 8

2. It can be constructed (connected) vertically to construct a large memory of size 32 X 4

D0
D1
D2
D3 Q0
Q1
Q2
Q3
RAM 1

A0
A1
A2
A3

D0 RAM 2
D1
D2
D3
Q0
Q1
A0 Q2
A1 Q3
A2
A3