International Conference on Communication and Signal Processing, April 4-6, 2019, India

An Efficient Design of 16 Bit MAC Unit using

Vedic Mathematics
Akella Srinivasa Krishna Vamsi and Ramesh S R

Abstract—Multiply and Accumulate (MAC) is one of the II. RELATED WORK

primary operations used widely in signal-processing and other
applications. Multiplier is the fundamental component of Digital As multiplication is termed as a widely used arithmetic
Signal Processors (DSP’s).Its parameters such as power, LUT operation, the reasearch has always been aiming to design fast
utilization and delay decides the performance of a DSP. So, multipliers either by showing improvements in power,area or
there is a need to design a power and delay efficient multiplier.
delay. In a MAC architecture proposed using an optimized
In this paper, a 16-bit MAC unit is designed using an 8-bit vedic
multiplier and carry-save adder. A comparison with the existing multiplier various parameters were calculated for 8bit, 16bit
8-bit vedic multiplier using Square-Root (SQR) Carry-Select and 32bit MAC units. The authors in [2] proposed a MAC
Adder (CSLA) is presented. It is compared with a conventional using vedic sutras and implemented in 90nm technology
array-multiplier. The entire design is implemented in Verilog showing improvements in circuit power, critical path delay
HDL. Synthesis and simulations were done using Xilinx ISE
and area in 4bit, 8bit MAC units respectively.
Design Suite 14.5 and Vivado 2018.2. The proposed design
achieves significant improvement in area and delay. In addition, An architecture for designing a 16bit vedic-multiplier using
a reduction in power around 9.5% is achieved. urdhva tiryakbhyam(UT) with three different adders has been
done in [3] and achieved around 32% reduction in
Index Terms—MAC unit, vedic mathematics, carry-save
adder, Verilog HDL, Look-up Table. combinational path delay compared to the previous
architectures.
The authors in [4] presented the design of a 16 bit vedic
I. INTRODUCTION multiplier with carry look-ahead adder and implemented on
16nm technology. The obtained results show improvement in
LOW power plays a prominent role in today’s current
trends of VLSI. Power dissipation has become a major
power compared to booth multiplier and other existing
architectures at the cost of transistor count. A booth-multipler
optimization objective due to increased demand for low-power with carry-look ahead adder is presented in [5] and
digital signal processors. There are numerous techniques and implemented in 90nm technology showing an improvement in
extension circuits employed to achieve low power in VLSI power, area compared to previous designs. In [6] , the design
designs. In a “Digital Signal Processor” (DSP) [1], the of a Multiply and Accumulate (MAC) unit is presented. For
commonly used operations are “multiply and accumulate” this, an 8bit vedic-multiplier using urdhva tiryakbhyam(UT)
(MAC), convolution and “Fast-Fourier Transforms” (FFT) etc. with square-root carry-select adder(SQRT-CSLA) is designed
The multiplier is considered as an essential block for the and implemented on an FPGA , compared the LUT slices,
above operations. Power consumption in a DSP hugely depend delay with the existing booth multiplier and concluded that
on MAC unit. MAC unit consists of a multiplier, an adder for speed of the neural network is increased with their proposed
adding its partial products and an accumulator for storing the design.Delay reduction using carry save addition is reported
obtained results. So for improving the speed of MAC unit, in[7].
speed of the multiplier should be improved. A carry save The authors in [8] proposed a MAC using a “modified
adder is used for this purpose and ancient vedic mathematics booth” algorithm and implemented on an FPGA.A comparison
is used for achieving reductions in power. with conventional architecture showed improvements in
This work emphasizes on designing a 16-bit MAC unit with power and area. The design of a 4bit , 8bit and 16bit vedic-
an 8-bit vedic-multiplier using urdhvatiryak (UT) logic and multipliers along with application of pipelining technique is
utilizes a carry save adder for adding the partial products. It is done in [9] thereby showing improvement in terms of power
then compared with a conventional array-multiplier and an reduction compared to the previous designs.
existing 8-bit vedic-multiplier using SQR-CSLA. In [10], the authors presented a survey on design of
The rest of the paper presents related work followed by different MAC units using multipliers such as wallace tree,
brief introduction of vedic mathematics in sections II and III dadda, modified booth etc and implemented in 90nm CMOS
respectively. In section IV, the design of MAC unit using an 8 technology.
bit vedic multiplier with carry save adder is presented. Section
V describes results and discussion. Section VI gives the III. VEDIC-MATHEMATICS
conclusion . Vedic-mathematics is a very old technique that can be
directly utilized to various branches of mathematics such as
algebra, arithmetic etc. It reduces the complexity by removing
the unnecessary steps while calculating any result. There are
16 sutras in vedic-mathematics. Table I shows the list of all
Akella Srinivasa Krishna Vamsi is with the Department of Electronics and vedic sutras.
Communication Engineering, Amrita School of Engineering,Coimbatore,
Amrita Vishwa Vidyapeetham,India. (email:akellakrishnavamsi@gmail.com).
Ramesh.S.R. is working as an Assistant Professor (Sr.Gr) with the Department
of Electronics and Communication Engineering, Amrita School of
Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India. (email:
sr_ramesh@cb.amrita.edu).

978-1-5386-7595-3/19/$31.00 ©2019 IEEE

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 TABLE I
16 VEDIC-SUTRAS [3]

S. No Sutra

1. (Anurupye) Shunyamanyat
2. Chalana-Kalanabyham
3. Ekadhikena Purvena
4. Ekanyunena Purvena

5. Gunakasamuccayah

6. Gunitasamuccayah
7. Nikhilam-Navatashcaramam Dashatah
8. Paraavartya-Yojayet
9. Puranapuranabyham
10. Sankalana-vyavakalanabhyam
11. Shesanyankena-Charamena
12. Shunyam-Saamyasamuccaye
13. Sopantyadvayamantyam Fig. 1. Basic MAC
14. Urdhva-Tiryakbhyam
15. Vyashtisamastih
16. Yavadunam

Among the above 16 sutras, Urdhva Tiryakbhyam(UT) and

Nikhilam Navatashcaramam Dashatah (NND) are used for
computing multiplication of any two numbers. Generally,
NND sutra is preferred for larger bit numbers and UT sutra is
preferred for smaller bit numbers. Hence UT sutra is used in
this work.

1) Urdhva Tiryakbhyam (UT)

Urdhva Tiryakbhyam(UT) means “vertically and cross-

wise” [4]. It is used for multiplication of two numbers with
any base. Let us consider the procedure for multiplying two Fig. 2. Implementation of 2bit multiplier with HA’s
3-bit numbers say U[2:0] and V[2:0] for example and C[3:0]
denotes the carry, Y[2:0] denotes the partial product output. However, the above design is not suitable for higher order
Then the following steps are to be followed: multipliers as it leads to increase in delay. Hence, a carry save
step1: C0Y0 = U0V0 adder is preferred for adding the partial products. Here partial
step2: C1Y1 = {(U0*V1) + (U1*V0)} + C0 products are generated in a parallel manner just like an array
step3: C2Y2 = {(U0*V2) + (U1*V1) + (U2*V0)} + C1 multiplier.
step4: C3Y3 = {(U1*V2) + (U2*V1)} + C2
step5: C4Y4 = {(U2*V2)} + C3 1) Carry-Save Adder
Hence, the final product = C4Y4Y3Y2Y1Y0
It is generally used for computing addition of 3 or more n-
IV. DESIGN OF MAC bit numbers. Here, the three inputs are converted to two
outputs where one output denotes partial sum and the other
In the design of a 16-bit MAC unit, an 8bit multipliers is one represents carry. The final sum is given by shifting the
used. It has been designed by 4bit multipliers. Similarly, 4bit carry to left by 1 bit position and then appending the MSB of
multiplier is designed using 2 bit multipliers. Fig. 1 shows partial sum with zeroes. Fig. 3 represents a carry-save adder
MAC. The implementation of the 2-bit multiplier with half- with an example.
adders using UT sutra is given by Fig. 2.

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 The simulations are as given below in Fig. 5, Fig. 6 and
Fig. 7 respectively. The obtained values are tabulated in Table
II and Table III.

Fig. 3. Carry-save adder

Fig. 5. Outputs of 8bit array-multiplier
2) Proposed 8 Bit Multiplier
The 8bit vedic-multiplier has been designed by four 4bit
multipliers. Here the inputs a[7:0] and b[7:0] are divided into
a[3:0], a[7:4], b[3:0], b[7:4] respectively and fed as inputs to
the multipliers and the final result is a 16 bit number. Fig. 4
represents the proposed architecture for 8bit multiplier.

Fig. 6. Outputs of proposed 8bit vedic-multiplier

Fig. 7. Outputs of 16 bit MAC unit

Table II illustrates the comparison of power between

Fig. 4. Design of 8 bit multiplier using 4 bit multipliers based on UT sutra conventional array multiplier and proposed multiplier.

V. RESULTS AND DISCUSSION TABLE II

POWER COMPARISON
The proposed 8bit vedic-multiplier is implemented in
Verilog HDL and simulated in Xilinx Vivado, then synthesis
is carried out in Xilinx ISE Design suite. Using this, a 16 bit Circuit Power(W)
MAC is also designed.
A conventional 8 bit array multiplier using half-adders and
full-adders is also designed for comparison. Here the targeted Array multiplier 0.992
FPGA is Artix-7.
Proposed multiplier 0.906

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 Table III presents the comparison of existing [6] and VI. CONCLUSION
proposed works in terms of area and delay. A 16 bit MAC unit utilizing an 8bit vedic-multiplier with
TABLE III carry save adder was designed. It was based on UT sutra and
AREA AND DELAY COMPARISON coded in verilog HDL. The implementation was carried on
Artix-7 FPGA. It was observed to possess around 9.5% power
Parameters Existing Proposed
multiplier
reduction along with significant improvement in area and
[6] delay. A comparison with a conventional multiplier and
existing multiplier was carried out respectively. The MAC unit
LUT Slices 397 149 designed with the proposed multiplier can be used in DSP
applications for improving the speed and performance. In
Delay (ns) 19.1 9.484 future, this work can be extended by replacing the multipliers
with reversible logic gates for achieving further power
reduction and better performance.
Along with FPGA implementation, the proposed 8bit
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Fig. 9. Area comparison

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