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    Iqra University Islamabad: Lab Sheet #3 of Digital Logic Design

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    This document provides instructions for an experiment to implement XOR and XNOR gates using NAND gates. The document includes the theory behind implementing these gates with NAND gates, including Boolean equations and logic diagrams. It then provides step-by-step procedures for building the XOR and XNOR gate circuits using NAND gates on a logic trainer. Students are instructed to test the circuits, record the output truths tables, and have their work verified by an instructor.

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    Iqra University Islamabad: Lab Sheet #3 of Digital Logic Design

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    Just Watch
    97 views5 pages
    This document provides instructions for an experiment to implement XOR and XNOR gates using NAND gates. The document includes the theory behind implementing these gates with NAND gates, including Boolean equations and logic diagrams. It then provides step-by-step procedures for building the XOR and XNOR gate circuits using NAND gates on a logic trainer. Students are instructed to test the circuits, record the output truths tables, and have their work verified by an instructor.

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    Lab Sheet 3

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    This document provides instructions for an experiment to implement XOR and XNOR gates using NAND gates. The document includes the theory behind implementing these gates with NAND gates, including Boolean equations and logic diagrams. It then provides step-by-step procedures for building the XOR and XNOR gate circuits using NAND gates on a logic trainer. Students are instructed to test the circuits, record the output truths tables, and have their work verified by an instructor.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    97 views5 pages

    Iqra University Islamabad: Lab Sheet #3 of Digital Logic Design

    Uploaded by

    Just Watch
    This document provides instructions for an experiment to implement XOR and XNOR gates using NAND gates. The document includes the theory behind implementing these gates with NAND gates, including Boolean equations and logic diagrams. It then provides step-by-step procedures for building the XOR and XNOR gate circuits using NAND gates on a logic trainer. Students are instructed to test the circuits, record the output truths tables, and have their work verified by an instructor.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    IQRA UNIVERSITY ISLAMABAD

    LAB SHEET #3
    OF DIGITAL LOGIC DESIGN

    Submitted by: Muhammad Furqan Ali


    Submitted to: Sir Waqar ul Hassan
    Subject: Digital Logic Design
    Department: BSCS
    Reg.no: CK-20-110014

    Experiment No. 3:
    Implement XOR and XNOR gates using NAND gates.

    Apparatus:
    • Logic trainer
    • Connecting wires
    • 14 pin ICs (7400)
    • Power supply

    Theory:
    Digital circuits are more frequently constructed with NAND and OR gates than with AND
    and OR gates. NAND and NOR gates are easier to fabricate with electronic components and are
    the basic gates used in all IC digital logic families. The graphic symbols for XOR, XNOR and NAND
    gates together with their algebraic functions are given below:

    Figure 3.1: Logic gates

    Truth Table for XOR gate:

    Input A Input B Output F


    0 0 0
    0 1 1
    1 0 1
    1 1 0

    Table3.1: Truth table for XOR gate

    The NAND logic diagram for XOR is obtained from Boolean function in the following way:

    1. The implementation of a XOR function with NAND gates requires that the function be
    simplified in the sum of products form.
    F = A’B + AB’ equation. 2.1
    2. Draw a NAND gate for each product term of the function that has at least two literals.
    This constitutes a group of first level gates.

    Figure 3.2: First level gates


    3. Draw a single NAND gate with in the second level, with inputs coming from the outputs
    of first-level gates.

    Figure 3.3: Second level gates

    4. A two input NAND gate can be used as inverter by applying logic 1 at one of the inputs.
    Figure 3.4: NAND implementation of XOR gate

    Calculations:

    Fill in the truth table for the XNOR function:

    Input A Input B Output F


    0 0 1
    0 1 0
    1 0 0
    1 1 1
    Table3.2: Truth table for XNOR gate

    Write Boolean function for XNOR gate:

    F = (A’B + AB’)’

    Draw NAND logic diagram for the XNOR gate:

    Procedure:

    It is clear from the logic diagram that the NAND gate implementation of XOR gate requires five
    NAND gates. You will need two quad- 2 in NAND gate ICs to perform this experiment. Gets the
    required number of ICs containing NAND gates and other apparatus from the lab attendant. Plug
    in the ICs in the breadboard of the Logic Trainer. Connect 5Vdc power supply and ground on pins
    14 and 7 respectively. For other pin configuration consult the data sheet (we have already used
    NAND gates in the first lab so it should not be a problem). Wire your circuit according to the logic
    diagram for XOR gate as given above. Once you have wired the circuit, check it with your
    instructor and, if approved, power up your circuit. The outputs should be connected to the LEDs
    on the Logic Trainer for monitoring purpose. Apply different input combinations at the input and
    note down the outputs and fill in the following truth table. This truth table should conform to the
    one given in theory. If there are problems, consult the appendix on troubleshooting given at the
    end of lab manual. If the problem persists, request lab supervisor for help.

    Repeat the same procedure for NAND gate implementation of XNOR gate.

    Observations:
    Fill in the following truth table in the presence of the lab lab instructor.

    Truth Table for XOR Gate:

    Input A Input B Output F


    0 0 0
    0 1 1
    1 0 1
    1 1 0

    Table3.3: Truth table for XOR gate


    Furqan.Ali
    Signature: --------------------

    Truth Table for XNOR Gate:

    Input A Input B Output F


    0 0 1
    0 1 0
    1 0 0
    1 1 1

    Table3.4: Truth table for XNOR gate

    Furqan.Ali
    Signature: --------------------

    Conclusions: The truth tables shows XOR and XNOR gates can be implemented by using NAND
    gates only.
    INSTRUCTOR VERIFICATION SHEET
    For each verification, be prepared to explain your answer and respond to other related
    questions that the lab TA’s or Professors might ask.

    Name: Date of Lab:

    Verified: Date/Time:

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