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Xperiment O. 3: Digital Logic Design Laboratory Hand Book

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Digital Logic Design Laboratory Hand Book

Experiment No. 3
VERIFICATION / IMPLEMENTATION OF DEMORGAN’S
THEOREMS, SIMPLIFICATION USING BOOLEAN ALGEBRA
AND CONSTRUCTION OF ALL LOGIC GATES BY USING
UNIVERSAL GATES
OBJECTIVE
 Assemble of the circuit according to the expression / equation by using Logic Gates.
Verifying their results of both circuits.
 Assemble of all Logic Gates by using universal gates, NAND gate and NOR gate.
Verifying their results
EQUIPMENT
 ePAL Trainer Board
 Connecting wires
COMPONENTs
 IC Type 7400 Quadruple 2-input NAND gates,
 IC Type 7402 Quadruple 2-input NOR gates
 IC Type 7404 Inverters gates
 IC Type 7432 Quadruple 2-input OR gates
 IC Type 7408 Quadruple 2-input AND gates
THEORY
PART 1; DeMorgan Theorem;
DeMorgan, a mathematician who knew Boole, proposed two theorems that are an important part
of Boolean algebra. In practical terms. DeMorgan's theorems provide mathematical verification of
the equivalency of the NAND and negative-OR gates and the equivalency of the NOR and
negative-AND gates.
DeMorgan’s 1st Theorem;
One of DeMorgan's theorems is stated as follows:
The complement of a product of variables is equal to the sum of the complements of the variables,
Stated another way,
The complement of two or more ANDed variables is equivalent to the OR of the complements of
the individual variables. The formula for expressing this theorem for two variables is

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CONNECTION DIAGRAM

DeMorgan’s 2nd Theorem;

DeMorgan's second theorem is stated as follows:


The complement of a sum of variables is equal to the product of the complements of the variables.
Stated another way,
The complement of two or more ORed variables is equivalent to the AND of the complements of
the individual variables, The formula for expressing this theorem for two variables is

CONNECTION DIAGRAM

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Applying DeMorgan's Theorems

The following procedure illustrates the application of DeMorgan's theorems and Boolean algebra
to the specific expression.

Construct circuits for L.H.S & R.H.S and verify the results.

PART 2;

 SIMPLIFICATION USING BOOLEAN ALGEBRA:


Many times, in the application of Boolean Algebra, we have to reduce a particular expression to
its simplest from or change its form to a more convenient one to implement the expression most
efficiently. This approach taken in this section is to use the basic Laws and Rules to manipulate
and simplify an expression.
A simplified Boolean expression uses the fewest gates possible to implement a given expression.

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Construct circuits for L.H.S & R.H.S and verify the results.
PART 3;
 UNIVERSAL GATE;
A universal gate is a gate which can implement any Boolean function without need to use any
other gate type. The NAND and NOR gates are universal gates. Both NAND and NOR gates
can realize basic logic gates (AND, OR and NOT) logic circuits singlehandedly. Therefore,
AOI logic can be converted to NAND logic or NOR logic.
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CONNECTION DIAGRAM

INVERTER /NOT GATE:


USING NAND

USING NOR

OR GATE
USING NAND

USING NOR

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AND GATE
USING NAND

USING NOR

BUFFER GATE
USING NAND

USING NOR

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PROCEDURE
1. Verify the gates.
2. Make the connections as per the circuit diagrams given in Figure above.
3. Switch on Vcc and apply various combinations of input according to the truth table for
each circuit.
4. Note down the output readings for logic using NAND and AOI logic using NOR.

RESULTS & CALCULATIONS


Sr.No INPUT OUTPUT Remarks
DeMorgan’s 1st A B
1 Theorem
1 0
0 1
DeMorgan’s 2nd A B
2 Theorem
1 0
0 1
Application of X Y Z L.HS R.H.S
3 DeMorgan Theorem

0 0 0
0 0 1
= 0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
SIMPLIFICATION X Y Z L.HS R.H.S
AB+A(B+C)+B
4 USING BOOLEAN (B+C)

ALGEBRA
0 0 0
0 0 1
= 0 1 0

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0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 3.1
Inputs Outputs (Inverter)

A Y (using NAND gate) Y (using NOR gate)

Table 3.2

Inputs Outputs (Buffer)

A Y (using NAND gate) Y (using NOR gate)


0
1

Table 3.3
Inputs Outputs (AND Logic)
A B Y (using NAND gate) Y (using NOR gate)
0 0
0 1
1 0
1 1
Table 3.4
Inputs Outputs (OR Logic)
A B Y (using NAND gate) Y (using NOR gate)
0 0
0 1
1 0
1 1

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CONCLUSION
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