MANUFACTURING

TEST
PRINCIPLES
(VLSI UNIT-5)

Prepared by
Tamilarasu T
tamilarasuece@gmail.com
Final ECE(2010 batch)
INTRODUCTION
 Faults should be detected during
manufacturing level itself.
 Digital circuits’ classification:
1. Combinational circuits
2. Sequential circuits
Here we are going to discuss different
methods of testing.
 TESTING
COMBINATIONAL
CIRCUITS
 Present output depends on present
input only.
 For testing of ‘n’ input circuits, 2^n
combinations are needed.
 For large values of ‘n’ it seems to be
difficult.
COMBINATIONAL LOGIC:
TESTING SEQUENTIAL
CIRCUITS:

 Present output not only depends on

present input but also depends on past
input & output.
 Due to feedback paths, testing is some
what complicated.
SEQUENTIAL LOGIC:
FAULT MODEL:

 Models bridge the gap between the physical

reality and mathematical abstraction.
DEFECTS:
 Unintended differences between the
implemented hardware & its intended design
ERROR:
 A wrong output signal produced by a
defective system is called error
FAULTS
 A representation of defects is called faults.
TYPICAL DEFECTS IN VLSI:

 Age defects
 Material defects
 Surface impurities
 Dielectric breakdown
STUCK AT FAULTS

 This fault is modeled by assigning values

(0 or 1) to a signal line in the circuit
 These faults can be simultaneously
presents in the circuits
 A circuit with ‘n’ combinations will have
(3^n)-1 possible stuck line combinations
TYPES OF STUCK AT FAULTS

1. Stuck-at-1 (s-a-1)
2. Stuck-at-0 (s-a-0)
S-A-0

 This fault is modeled by assigning ‘0’ to

a signal line in the circuit.
S-A-1

 This fault is modeled by assigning ‘1’ to a

signal line in the circuit.
O.C & S.C FAULTS

 These faults are due to physical faults

which in turn cause physical change in
the circuit
REASONS FOR S.C FAULTS:

 Under etching
 Spiking
 Diffusion shorts
 Contact opens
 Gate to source/drain short
 Mask misalignment
REASONS FOR O.C FAULTS:

 A bad contact
 Metal missing
 Poor wire bonding
 Metal migration
ILLUSTRATION FOR O.C
 CMOS-NOR
QUESTIONS:
 A circuit with ‘n’ combinations will
have ……….. possible stuck line
combinations.
 Define faults.
 Reasons for o.c faults.
 Define stuck at faults.
CONT. & OBS.:
CONTROLABILITY
 Difficulty of setting particular logic signal to a
zero or one.
 RANGE: one to infinite

OBSERVABILITY
 Difficulty of observing particular logic signal to a
zero or one.
 RANGE: zero to infinite
SCOAP algorithm
 Sandia Controllability/Observability Analysis
Program.
 Proposed by Goldstein.
 The 1-Controllability is the probability of a
signal value on line being set to 1 by a
random vector.
 The 0-Controllability is the probability of a
signal value on line being set to 0 by a
random vector.
NUMERICAL MEASURES for
SCOAP:
1. CC0(n)
2. CC1(n)
3. CO(n)
4. SC0(n)
5. SC1(n)
6. SO(n)
Different Cases of
controllability
Output is controlled by OUTPUT COTROLLABILITY

Setting one value Min(input controllabilities) +1

Setting all values sum(input controllabilities) +1

Multiple inputs min(all input controllabilities) +1

SCOAP controllability AND gate

a b Z

0 0 0

0 1 0

1 0 0

1 1 1 cc1(b)
SCOAP controllability OR gate

a b Z

0 0 0

0 1 1

1 0 1
1 1 1
SCOAP controllability NOR gate

a b Z

0 0 1

0 1 0

1 0 0

1 1 0
SCOAP controllability NAND gate

a b Z

0 0 1

0 1 1

1 0 1

1 1 0
SCOAP controllability XOR gate

a b Z

0 0 0

0 1 1

1 0 1

1 1 0
SCOAP controllability X-NOR gate

a b Z

0 0 1

0 1 0

1 0 0

1 1 1
SCOAP controllability NOT gate

a Z
1 0
0 1
 OBSVERABILITY
LOGIC GATES OBSERVABILITY CALCULATION
OR co(a)=co(z)+cc0(b)+1
co(b)=co(z)+cc0(a)+1
AND co(a)=co(z)+cc1(b)+1
co(b)=co(z)+cc1(a)+1
XOR co(a)=co(z)+min(cc0(b),cc1(b))+1
co(a)=co(z)+min(cc0(b),cc1(b))+1
OBSVERABILITY

LOGIC GATES OBSERVABILITY CALCULATION

NOR co(a)=co(z)+cc0(b)+1
co(b)=co(z)+cc0(a)+1
NAND co(a)=co(z)+cc1(b)+1
co(b)=co(z)+cc1(a)+1
XOR co(a)=co(z)+min(cc0(b),cc1(b))+1
co(a)=co(z)+min(cc0(b),cc1(b))+1
 OBSVERABILITY

LOGIC GATE OBSERVABILITY CALCULATION

NOT co(a)=co(z)+1
QUESTIONS
 Define observability & controllability.
 SCOAP controllability of NAND gate.
AUTOMATIC TEST PATTERN
GENERATION
 ATPG algorithms inject a fault into a ckt.
 Uses a variety of mechanisms to activate the
fault.
 Non controlling values is given for other
inputs
 It’s to view the fault propagation.
 Finally detect the fault by comparing with
expected output.
D-calculus
 ATPG algorithm.
 Developed by Rother.
 The symbol D(detect) indicates the
value of fault.
 The node values are defined by
1,0,X,D,Dbar,
 Routh’s algebra:
SYMBOL MEANING GOOD MACHINE FAILING
MACHINE

D (1/0) 1 0

Dbar (1/0) 0 1

0 (0/0) 0 0

1 (1/1) 1 1

X (X/X) X X
 D-calculus for AND gate
AND 0 1 X D Dbar

0 0 0 0 0 0

1 0 1 X D Dbar

X 0 X X X X

D 0 D X D 0

Dbar 0 Dbar X 0 Dbar

D-calculus for OR gate
OR 1 0 X D Dbar

1 1 1 1 1 1

0 1 0 X D Dbar

X 1 X X X X

D 1 D X D 1

Dbar 1 Dbar X 1 Dbar

D-calculus for NOT gate
A Abar

0 1

1 0

X X

D Dbar

Dbar D
PODEM algorithm
 Path oriented decision making algorithm.
 Solves the problem of reconvergent.
 Allows multipath sensitization.
 Similar to D-calculus major difference is it is
reversible during incorrect decision.

BASIC STEPS
1. Objective
2. Back trace
3. Implication
4. D-frontier
 Find using Routh’s algebra:

SYMBOL MEANING GOOD MACHINE FAILING

MACHINE

X
QUESTIONS:
EXPAND THE FOLLOWING:
1. PODEM
2. ATPG
3. D-calculus.
FAULT SIMULATION

 To verify the correctness of the design

 It verifies the test
TYPES
1. Serial fault simulation

2. Parallel fault simulation

3. Concurrent fault simulation

4. Non deterministic fault simulation

SERIAL FAULT
SIMULATION

 Simulate circuit using true value mode for all

vectors.
 Primary output values are saved is a file.
 Faulty circuits are simulated one by one.
 This can be done by inserting faults at line or
node
 Then output of former & latter are compared
No. of simulation cycles (Sy)
are given by

Sy = (2N/2)Y+N

= NY+N

=N(Y+1)

=NY (app)
N -no.of test vectors
Y-no. of nodes
PARALLEL FAULT
SIMULATION

 It uses the bit parallelism of logical operations in a

digital computer
 It allows simultaneous simulation with identical
connectivity, but possibly different values
 Performance: (W-1) times faster than former one.
 W-bits in the machine word size
 Here,
Sy = (Yn /M)
CONCURRENT FAULT
SIMULATION

 Here simulating whole circuit with fault

models are avoided
 First simulate the good circuit
 Then inject fault and re simulate part
of circuit that behaves differently
NON-DETERMINISTIC
SIMULATION

 Previous models are deterministic fault

simulation
 Here simulation is done by using
probabilistic fault simulation
 We simulate a subset or sample of faults
and extrapolate fault coverage from the
sample
DELAY FAULT TESTING

 Due to combinational delay in the circuit

Specific delay faults are:
1. Transition faults
2. Gate delay faults
3. Line delay faults
4. Path delay faults.
STASTICAL FAULT ANALYSIS
 Technique that statistically determines
1. controllabilities,
2. observabilities,
3. detection probabilities &
4. fault converge from true value of
simulation.
FAULT SAMPLING

 Subset of faults is randomly picked from the

set of all faults
 This subset is usually a small fraction of the
complete faulty set
 Faults in sample are simulated & the sample
coverage is used as an estimate of the fault
coverage in the complete fault set
 Increasing sample value decreases the error
bound
CONCLUSION
Finding defects at manufacturing level
itself will give us a better result. Using
above techniques faults free circuits can
be obtained at manufacturing level.
REFERENCE
VLSI design by R.Uma.
QUERIES