UNIT – III

1(a) For the circuit shown below, the test pattern to detect SA1, SA0 at G3/Y and SA0, SA1 at G2/Y:

6 Marks

(b) Discuss in detail the bridging fault model. 4 Marks

2(a) Explain the 4-bit PRBS generator with an example. 5 Marks

(b) Describe briefly the various DFT schemes used in digital systems. 5 marks

UNIT – IV

3 (a) Explain D-algorithm with an example. 6 Marks

(b) Explain the terms 4 Marks

(i) Fault diagnosis and detection (ii) Test generation.

4 (a) Explain in detail about methods adopted for fault diagnosis in combinational circuits.

6 Marks

(b) Using path sensitization method generate test pattern for the s-a-0 fault in the circuit given
below: 4 Marks

UNIT – V

5 (a) Explain signature analysis with the help of an example. 5 Marks

(b) With the help of the following input sequence explain LFSR and 4-bit PBRS.
Input sequence 1000 for LFSR and 001111 for 4-bit PBRS. 5 Marks
6. Describe the algorithmic steps involved in PODEM. 10 Marks
SOLUIONS:

1(a) G3/Y –

SA0 – {2202,0010}

SA1 – {0002}

G2/Y –

SA0 – {1111}

SA1 – {1110}

1(b) A bridging fault occurs when two signal lines in a digital circuit unintentionally connect.
This can lead to incorrect signal behavior and potentially cause the circuit to malfunction.
Bridging faults are typically restricted to signals that are physically adjacent in the design

Types of Bridging Faults

Wired-AND Fault: When the bridged signals result in a logical AND operation.

Wired-OR Fault: When the bridged signals result in a logical OR operation.

2(a)

2(b) Explain any of the following: Scan Chain, Built-In Self-Test (BIST).

3 (a) The D algorithm was developed by Roth at IBM in 1966 and was the first complete test pattern
algorithm designed to be programmable on a computer. The D algorithm is a deterministic ATPG
method for combinational circuits, guaranteed to find a test vector if one exists for detecting a fault.
It uses cubical algebra for the automatic generation of tests.

Three types of cubes are considered:

 Singular cover table (SCT)

 Propagation D-cube (PDC)
 Primitive D-cube of a fault (PDCF)
Singular Cover Table (SCT) of any logic gate is the compact form of truth-table. This is done using
don’t cares (x). Following reduced truth table is the singular cover of an AND gate.

We know that, for an AND gate, the output is logic-1 only when both of its inputs are high. At the same
time, the output is logic-0 for all the other cases where any of its input is low. The output of the AND
gate is low for most of the cases. Hence, specifying separate columns for every possible input
combinations becomes redundant. Therefore we merge the rows of AND gate and define the truth-
table using don’t cares in a more condensed form.

Primitive D-cube of a Fault (PDCF) is used to specify the minimum input conditions required at
inputs of a gate to produce an error at its output. This is used for fault activation. PDCF can be derived
from the intersection of singular covers of gates in faulty and non-faulty conditions having different
outputs.

Propagation D-cubes (PDCs) of a gate causes the output of the gate to depend upon the minimum
number of its specified inputs. It is used to propagate D or D’ from a specified input to the
output. Propagation D-Cubes can be derived from the intersection of singular cubes of gates of
opposite output values.

Example:

Step 1: Activate the fault by using PDCF of AND gate with output s-a-0 for gate G1. Discrepancy D is
generated.

Step 2: Forward propagate D by using suitable PDC of OR gate G3. For OR gate we have PDCs as: {0,
D/D’, D/D’}, {D/D’, 0, D/D’} and {D/D’, D/D’, D/D’}. Since already one of its input (g) is assigned D, we
chose PDC as {D, 0, D}. There is only one single D-frontier in this case.

Step 3: Intersect test cubes of row 1 and row 2 to obtain the unified test cube. Follow the test-cube
intersection table for this. Empty boxes can be assumed as don’t care (x).

TC(1) = TC(0) ∩ PDG3 = {1, 1, x, x, x, x, D, x, x, x, x, x} ∩ { x, x, x, x, x, x, D, 0, x, D, x, x, x}

= {1∩x, 1∩x, x∩x, x∩x, x∩x, x∩x, D∩D, x∩0, x∩x, x∩D, x∩x, x∩x, x∩x}

= {1, 1, x, x, x, x, D, 0, x, D, x, x, x}

Now we can D-drive through gate G3 towards the next D-frontiers.

Step 4: After every forward propagation, we need to perform backward implication to satisfy the J-
frontier and check for consistency. For this, first, obtain the singular cover of NAND gate G2. Since its
output is already assigned logic-0, the only possible singular cover is {1, 1, 0}.

Step 5: Intersect test cubes to obtain the unified test cube. J-frontier is satisfied, and consistency is
maintained.

Step 6: For forward propagation, there are two possible D-frontiers available, gate G5 and G6. We
chose the gate G5.

Step 7: Find PDC of AND gate G5 for forward propagation.

Step 8: D-drive through gate G5 by intersecting the previous two test-cubes. We have finally reached
the primary outputs.

Step 9: Perform backward implication to justify the J-frontier gate G4. For this, we again need to find
a suitable singular cover.

Step 10: Intersect last two test-cubes to obtain the final test-cube. No conflicts during intersection,
hence justification completed. Assign don’t care (x) to the remaining empty boxes like f and y to
obtain the complete test-cube.

D Algorithm Table:

The test vector for finding the g→s-a-0 fault is:

{a, b, c, d, e, f} = {1, 1, 1, 1, x, x}

3 (b) Explain the following terms

(i) Fault diagnosis and Fault detection (ii) Test generation.

4 (a) Explain the methods: Path Sensitization, Boolean Difference, Kohavi Algorithm, D Alogrithm.
4 (b) To sensitize the fault, 1 is to be applied at the output of the AND gate. Also, there is only one path
for fault propagation-- fault location to E. Now, to justify we need to apply a 0 at the second input of
the OR gate. This leads to a collision. For justification we need a 0 in the second input of the OR gate
and to sensitize the fault B is to be 1, which makes the second input of the OR gate a 1. This is illustrated
in the figure below in terms of Routh’s algebra.

Now, since there is no other alternative path for fault propagation, this fault is not testable. In fact the
answer is true. This fault is not testable. This example actually illustrates another utility of ATPG
algorithm—finding redundancy in circuits. If we observer carefully, function represented by this circuit
is: E=A.B+B. This can be simplified as B(A+1), which is B. So these two gates are redundant. So, if ATPG
by path sensitization discovers that a fault is not testable, then there is redundancy in the circuit.

5 (a)
5 (b)
6.