CSD Module 1 Question Bank

Qn. Questions
No.
1. Solve for prime implicants & essential prime implicants using k-map method
a f(a,b,c,d)= Σm(0,2,5,7,8,10,13,15)+ Σd(1,4,11,14)
b f(a,b,c,d)= π M (0,3,4,5,6,7,11,15) . π d(2,14)
c f(a,b,c,d)= Σm(5,7,8,9,10,11,12,14) using MEV
2 Solve for prime implicants & essential prime implicants using k-map method
a f(a,b,c,d)= Σm(3,4,5,7,9,12,13,15)
b f(a,b,c,d)= π M (0,2,3,8,9,10,12,14)
c f(a,b,c,d)= Σm(3,4,5,7,8,11,12,13,15) using MEV
3. a Determine the minimum sum of products and minimum product of sums for
f=b’c’d’+bcd+acd+a’b’c+a’bc’d
b What is Map-Entered Variable method? Apply MEV method simplify following
function: f(a,b,c,d)= Σm(2, 3, 4, 5, 13, 15)+ Σd(8, 9 10, 11)
4. Construct a minimized expression for given expression using Quine Mc-clusky
method.
a f(a,b,c,d)= Σm(7,9,12,13,14,15)+ Σd(4,11)
b f(a,b,c,d)= π M (0, 5,6,7,8,9,13,15)
c f(a,b,c,d)= Σm(0,2,3,4,8,10,12,13,14)
d f(a,b,c,d)= π M (2,3,8,12,13) . π d(10,14)
5 a Implement f(a,b,c,d)= Σm(0,1,2,5,7,9,12)+Σd(3,4,8) using 8-to-1 multiplexer.
b Realize the Boolean expressions using a 3-to-8 decoder
f1(A,B,C) = Σm(1,2,4,5), f2(A,B,C) = Σm(1,5,7), f3(A,B,C) = Σm(2,5,6)
6. a Realize 16:1 MUX using 4:1 MUX
b Implement f(a,b,c,d)= Σm(0,1,2,5,7,9,12)+Σd(3,4,8) using 8-to-1 multiplexer.
7. a Realize the Full adder using a 3-to-8 decoder
b Define Demultiplexer. Write block diagram, truth table and logic equation of 1
to 8 DMUX
8. Describe 2 bit magnitude comparator
9. Explain Even Parity Generators with truth table and logic circuit
10. Explain tristate buffers and how it can be used as 2:1 MUX
11. Discuss 8-to-3 Priority Encoder
12. Explain Odd parity Generator with truth table and logic circuit
13. Describe 3 to 8 binary encoder with block diagram, truth table and logic
equation.
 MCQs

Q. No Multiple Choice Questions PART A

The gates required to build a half adder are

01 a) EX-OR gate and NOR gate b) EX-OR gate and OR gate
c) EX-OR gate and AND gate d) EX-NOR gate and AND gate
Which gate is best used as a basic comparator?
02 a) NOR b) AND
c) OR d) Exclusive OR

Which combinational circuit is renowned for selecting a single input from multiple inputs & directing
the binary information to output line?
03
a) Data Selector b) Data distributor
c) Both data selector and data distributor d) De-Multiplexer
Which one of the following Demultiplexers requires only two select lines
04 a) 1-to-2 demux b) 1-to-4 demux
c) 1-to-8 demux d) 1-to-32 demux
A three-state buffer has the following output states
05 a) 1,0,Z b) Clear, redo, Set
c) clock, halt, 1 d) Set, reset, halt
Which combinational circuit is renowned for selecting a single input from multiple inputs &
directing the binary information to output line?
06
a) Data Selector b) Data distributor
c) Both data selector and data distributor d) De-Multiplexer
If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
07 a) 2 b) m
c) n d) 2n
When the enable input is one, s1=1, S0=0 in the 1:4 Demultiplexers then the outputs Y0, Y1, Y2, and
Y3 are ________________ ?
08
a) Y0=Y1=Y2=Y3=1 b) Y0=Y1=Y2=Y3=0
c) Y0=Y1=Y3=0, Y2=1 d) Y1=Y2=Y3=1, Y0=0
What is a parity bit?
09 a) An error detection achieved by adding an extra bit b) After addition, the carry is found
c) Bit generated during data transmission d) After addition, the total number of bits
There are ______ cells in a 4-variable K-map.
10 a) 4 b)8
c) 16 d) 32
Most demultiplexers facilitate which type of conversion?
11
a) Decimal-to-hexadecimal b) Single input, multiple outputs
 c) AC to DC d) Odd parity to even parity
12 One that is not the outcome of magnitude comparator is ____________
a) a > b b) a – b
c) a < b d) a = b
How many outputs will a decimal-to-BCD encoder have?
13 a) 4 b) 8
c) 12 d) 16
The logical sum of two or more logical product terms is called __________
14
a) SOP b) POS
c) OR operation d) NAND operation
Binary Code is a symbolic representation of __________ information.
a) Continuous b) Discrete
15
c) Analog d) Both continuous and discrete
 CSD Module 2 Question Bank

Qn. Questions
No.
1. Develop the characteristic table, characteristic equation, excitation table, state diagram and
timing diagram for the following flip flops(4M each)
a) Positive edge triggered SR flip b) Negative edge triggered JK flip flop
2 Define shift register? Explain the working of 8bit SISO shift register using SR Flip Flop.

3. With neat diagram explain 4bit SISO register using D Flipflops and write state table to right
shift the contents 0111.
4. Illustrate any two applications of shift registers with neat logic diagram and timing diagram.

5 a Identify Race around condition in JK flip-flops.(2M)

b Realize a JK master slave flipflop with neat diagram, truth table and timing diagram(6M)
6. Construct multi operational PIPO right shift register using Flip-flops and MUXs and also build
timing diagram for the same.

7. Consider a 3-bit Johnson counter with input data word as 001,

a) Determine all definite states of Johnson counter. (2M)
b) Design a counter using D Flip-flops for the generated states. (6M)

8. Design a sequence detector circuit, which detects three or more consecutive 1’s in a string of
bits coming through an input line.
(a) Find the state diagram. (2M)
(b) Tabulate state (or transition) table of sequence detector. (2M)
(c) Implement the circuit using D flip-flops. (4M)

9. Illustrate the Universal Shift register with a neat diagram.

10. Differentiate between latch and a flip-flop. Explain different types of flip-flops with Truth
Table and Logic Circuit.
11. a Name the four basic types of shift registers, draw a block diagram for each. (4M)
b Illustrate 8 bit serial adder with neat diagram(4M)
 MCQs

Q. No Multiple Choice Questions PART A

The output of the sequential circuit depends upon _________

a) Present input
01 b) Past input
c) Present input and present state
d) None of the above
When both set and reset are disabled in S-R flip flop then the output will be __________
a) Set
02 b) Reset
c) No change
d) Indeterminate

In which flip flop the present input will be the next output?
a) S-R
03 b) J-K
c) D
d) T
_________ are the applications of flip flop
a) Registers
04 b) Counters
c) Storage devices
d) All of the above
________ is an example for sequential circuit
a) Flip flop
05 b) Full adder
c) Half adder
d) None of the above
In serial shifting method, data shifting occurs ____________
a) One bit at a time
06 b) simultaneously
c) Two bit at a time
d) Four bit at a time
A register is defined as ___________
07 a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
 c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
How many clock pulses will be required to completely load serially a 5-bit shift register?
a) 2
08 b) 3
c) 4
d) 5
What is the difference between a ring shift counter and a Johnson shift counter?
a) There is no difference
09 b) A ring is faster
c) The feedback is reversed
d) The Johnson is faster
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing
________
10 a) 1110
b) 0111
c) 1000
d) 1001
In a 4-bit Johnson counter sequence, there are a total of how many states or bit patterns?
a) 1
11 b) 3
c) 4
d) 8
9. What is one disadvantage of an S-R flip-flop?
12 a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State
In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output will oscillate
back and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The
situation is referred to as?
13 a) Conversion condition
b) Race around condition
c) Lock out state
d) Forbidden State
9. For realisation of D flip-flop from SR flip-flop, the external input is given through ___________
14 a) S
b) R
c) D
 d) Both S and R
A shift register is defined as ___________
a) The register capable of shifting information to another register
15 b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
 BMS INSTITUTE OF TECHNOLOGY AND MANAGEMENT
Avalahalli, Doddaballapura Main Road, Bengaluru – 560064

Course Name Computer System Design Course Code 21CS36

Branch & Semester CSE , ISE III Date 5/10/2020, 2:00-3:40 PM

Module III - -

1. How many flip-flops are required to make a MOD-32 binary counter?

A. 3

B. 45

C. 5

D. 6

2. A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock
pulses?
A. 10002

B. 10102

C. 10112

D. 11012
The terminal count of a modulus-11 binary counter is ________.
A. 1010

B. 1000

C. 1001

D. 1100
Answer: Option A
Synchronous construction reduces the delay time of a counter to the delay of:
A. all flip-flops and gates

B. all flip-flops and gates after a 3 count

C. a single gate

D. a single flip-flop and a gate

Answer: Option D
Synchronous counters eliminate the delay problems encountered with asynchronous counters
because the:
 A. input clock pulses are applied only to the first and last stages

B. input clock pulses are applied only to the last stage

C. input clock pulses are not used to activate any of the counter stages

D. input clock pulses are applied simultaneously to each stage

Answer: Option D
What is the difference between combinational logic and sequential logic?
Combinational circuits are not triggered by timing pulses, sequential circuits are triggered
A.
by timing pulses.

B. Combinational and sequential circuits are both triggered by timing pulses.

C. Neither circuit is triggered by timing pulses.

Answer: Option A
When two counters are cascaded, the overall MOD number is equal to the ________ of their
individual MOD numbers.
A. product

B. sum

C. log

D. reciprocal
Answer: Option A
Which segments of a seven-segment display would be required to be active to display the
decimal digit 2?
A. a, b, d, e, and g

B. a, b, c, d, and g

C. a, c, d, f, and g

D. a, b, c, d, e, and f
Answer: Option A
A BCD counter is a ________.
A. binary counter

B. full-modulus counter

C. decade counter

D. divide-by-10 counter
Answer: Option C
How many flip-flops are required to construct a decade counter?
A. 10

B. 8

C. 5

D. 4
Answer: Option D
 Select the response that best describes the use of the Master Reset on typical 4-bit binary
counters.
A. When MR1 and MR2 are both HIGH, all Qs will be reset to zero.

B. When MR1 and MR2 are both HIGH, all Qs will be reset to one.

C. MR1 and MR2 are provided to synchronously reset all four flip-flops.

D. To enable the count mode, MR1 and MR2 must be held LOW.
Answer: Option A
Which of the following is an invalid output state for an 8421 BCD counter?
A. 1110

B. 0000

C. 0010

D. 0001
Answer: Option A
How many different states does a 3-bit asynchronous counter have?
A. 2

B. 4

C. 8

D. 16
Answer: Option C
Three cascaded modulus-5 counters have an overall modulus of ________.
A. 5

B. 25

C. 125

D. 500
Answer: Option C
Once an up-/down-counter begins its count sequence, it cannot be reversed.
A. True

B. False
Answer: Option B
The final output of a modulus-8 counter occurs one time for every ________.
A. 8 clock pulses

B. 16 clock pulses

C. 24 clock pulses

D. 32 clock pulses
Answer: Option A
A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does
the counter go on the next clock pulse?
A. 1101

B. 1011

C. 1111

D. 0000
Answer: Option B

1. Analyze the state graph for the following circuit using Mealy and Moore Model.

2. Analyze the state graph for the following circuit using Mealy and Moore Model.

3. Analyze the state graph for the following circuit using Mealy and Moore Model.
4. Sketch a 3-bit counter which counts in the irregular sequence of states 000, 100, 111,
010, 011 (repeat) 000 and derive the equations for TC, TB and TA.

5. Design Mod-6 up synchronous up counter where the unused states lead to 000.
6. Design Mod-8 up synchronous up counter where the unused states lead to 000.
7. Design Mod-5 up synchronous up counter where the unused states lead to 000.
8. Design Mod-6 up synchronous up counter.
9. Design Mod-8 up synchronous up counter.
10. Design Mod-5 up synchronous up counter.
11. Design Asynchronous UP-Counter using JK FF.
12. Design Asynchronous Down-Counter using JK FF.
13. Design Mealy and Moore Model for Sequential Parity Counter.
14. Design Mealy Model for Serial Adder.
15. State the difference between Mealy and Moore Model.
Module 4 Question Bank
1. Draw and explain the top level structure of computer
2. (a) Differentiate between computer architecture and computer organization
(b) list and explain the four basic functions of computer
3. Illustrate with a neat diagram the simplified view of major elements of multicore
computer
4. List and highlight the important sub- areas within the processor core
5. What is stored program concept? Explain with a neat diagram IAS computer structure
6. With respect to designing for performance explain
(a) Microprocessor speed
(b) Performance balance
7. What is the significance of Amdahl’s law, show with a neat graph how Amdahl’s law
helps to speed up the multiprocessors
8. Highlight with important features the evolution of the Intel product line
9. Illustrate with a neat diagram the Top level view of computer components
10. Show with an example the program execution indicating the contents of memory and
registers
11. Show with a neat flow diagram the programed I/O and interrupt driven I/O as part of
techniques for Input of a block of data
12. Explain with neat flow diagram the how a simple Interrupt is processed by CPU
indicating hardware and software states
 Q.
Multiple Choice Questions PART A
No
___________ moves the data between computer and its external environment
01 (a) CPU (b) Main Memory (c) I/O System (d) System Interconnection
Answer: c
___________ provides storage internal to the CPU
02 (a) Registers (b) RAM (c) ROM (d) None of the above
Answer: a

If a processor contains _____________ it is referred to as a multicore processor

03 (a) One core (b) Any core (C) Multicore (d) None of the above
Answer: c
___________Manages the transfer of data to and from main memory via cache
04 (a) Load Store logic (b) Instruction logic (c) ALU (d) None of the above
Answer: a
____________ is responsible for the parsing and decoding of all z/Architecture operation codes
05 (a) IFU (b) IDU (c)LSU (d) None of the above
Answer: b
_____________ microprocessor was an 8-bit machine, with an 8-bit data path to memory
06 (a) 8080 (b) 8088 (c)8085 (d) 80186
Answer: a
______________ is still the basic technology for computer main memory
07 (a) SRAM (b) DRAM (c) SDRAM (d) none of the above
Answer: b
_____________ enables a processor to work simultaneously on multiple instructions by performing a
different phase for each of the multiple instructions at the same time
08
(a) Brach prediction (b) Pipelining (c) Data flow analysis (d) All the these
Answer: b
The processing required for a single instruction is called an __________________
09 (a) Fetch cycle (b) decode cycle (c) execute cycle (d) instruction cycle
Answer: d
___________simply means that the processor can and will ignore that interrupt request signal
10 (a) A disabled interrupt (b) A vectored interrupt (d) Scalar interrupt (d) None of the above
Answer: a
With memory- mapped I/O there is a ____________for memory locations and I/O devices
11 (a) Two address space (b) Single address space (c) No address Space (d) None of the above
Answer: b
_________________ mode, the I/O module and main memory exchange data directly, without
12
processor involvement
(a) DMA (b) Memory mapped I/O (c) I/O mapped I/O (d) None of the above
Answer: a
___________ I/O command is used to test various status conditions associated with an I/O module and
its peripherals
13
(a) Control (b) Test (c) Read (d) Write
Answer: b
14

15
Module 5 Question Bank
1) Briefly explain the following representations
i) Sign magnitude ii) Two’s complement
2) Assume the numbers are represented in 8-bits two’s complement representation .show the
calculation for the following
a.9+12 b. 9-12 c. -9+12 d.-9-12
3) Given a=0011 and b=1011 in two’s complement notation (a=3 and b=-5), compare the
product with Booth’s algorithm.
4) Sketch the block diagram of hardware for addition and subtraction and explain how an
overflow occurs with an example.
5) Show the flowchart for unsigned binary multiplication with the given values are a=1011 and
b=1101 .
6) Show the flowchart for unsigned binary division and analyse with an example for restoring
two’s complement division of 7 and 3.
7) List the four registers used in fetch cycle and Illustrate the sequence of events in fetch cycle
and with an example
8) Illustrate the sequence of events in execute cycle with an example
9) Explain the complete sequence of micro operations with a flowchart.
10) Explain how is a horizontal microinstruction is interpreted.
11) Explain how is a vertical microinstruction is interpreted.
12) Discuss the tasks for hardwired implementation of a control unit with a neat sketch.
13) Discuss the micro programmed implementation of a control unit with a neat sketch.
14) Define the following
i) Micro-instruction ii) micro program
15) Solve the following pairs of numbers represented in 2’s-complement format to
perform addition and subtraction and find whether overflow has occurred or not. The
numbers are represented using 7-bits including the sign bit.
a) +25 and +38 b) +33 and +51 c) –24 and +63 d) –23 and –57
16) Sketch a flow chart for complete sequence of micro-operations and explain.
17) Use the booth’s algorithm to multiply 25 by 15 where each number is represented
using 6 bits
18) Demonstrate with a block diagram, the basic organization of micro programmed
control unit
Q.
Multiple Choice Questions PART A
No
The sign magnitude representation of -1 is
01 a) 0001 b)1110 c) 1000 d)1001
Solution: d
The ALU gives the output of the operations and the output is stored in the _________
02 a) Memory Devices b)Registers c) Flags d)Output Units
Solution: b

Two’s complement representation for -3 is

03 a) 1011 b)1110 c) 1000 d)1001
solution: a
__________holds the address of the next instruction to be fetched.
04 a) Program counter b) instruction register c) flags d) MBR
solution : program counter (a)
5. ______determines the status of the processor and the outcome of previous ALU operations.
05 a) Program counter b) instruction register c) flags d) MBR
solution : c-flags
A sequence of control words corresponding to a control sequence is called __________
a) Micro routine b) Micro function c) Micro procedure d) none
06 solution – a-micro routine

In micro programmed approach ,the signals are generated by _______

07 a) Machine instruction b) system programs c) Utility tools d) none of the above
solution:-a-machine instructions
To read the words sequentially ____________________is used
08 a) PC b) IR c) UPC d) none of the above
solution: c) -UPC
Individual control words of the micro routine are called as__________
09 a)Micro task b) Micro operation c) Micro instruction d) Micro command
solution :- c) Micro instruction
Highly encoded schemes that use compact codes to specify a small number of functions in each micro
instruction is ___________
10
a)horizontal organization b) Vertical organization c) diagonal organization d) none of the above
solution : b) vertical organization
The functions of execution and sequencing performed by using
11 a) input signals b) output signals c) control signal d) CPU
solution :- c) control signal
12 which representation is most efficient to perform arithmetic operations on the numbers?
a) sign magnitude b) 1’s complement c) 2’s complement d)none

when we perform subtraction on -7 and -5 and the answer in 2’s complement form is ____
13 a) 11110 b) 1110 c) 1010 d) 0010
solution :b) 1110.
The flag ‘V’ is set to 1 indicates that
14
a) The operation is valid b) the operation is validated c) the operation has resulted in an
overflow d) none
15