Part A

1. For a 4-bit universal shift register, the selection lines S0S1 = 00 represents _____
operation
a. Locked state (No change)
b. Shift-Left
c. Shift-Right
d. Parallel Loading
Ans : Locked state (No change)
2. For a 4-bit universal shift register, the selection lines S0S1 = 01 represents _____
operation
a. Locked state (No change)
b. Shift-Left
c. Shift-Right
d. Parallel Loading
Ans : Shift-Left
3. For a 4-bit universal shift register, the selection lines S0S1 = 10 represents _____
operation
a. Locked state (No change)
b. Shift-Left
c. Shift-Right
d. Parallel Loading
Ans : Shift- Right
4. For a 4-bit universal shift register, the selection lines S0S1 = 11 represents _____
operation
a. Locked state (No change)
b. Shift-Left
c. Shift-Right
d. Parallel Loading
Ans : Parallel Loading
5. Number of D flipflops required for designing the synchronous counter for the
given state diagram is ……………
 a. 2
b. 3
c. 5
d. 7
Ans: b. 3
6. The propagation delay in synchronous counter is much lesser than that of
asynchronous counter due to ……………….
a. clocking of all flip flops at the same instant
b. increase in number of states
c. absence of connection between output of preceding flip flop and clock of next one
d. absence of mode control operation
Ans: a. clocking of all flip flops at the same instant
7. Ripple counters are also called ____________
a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
Ans: b) Asynchronous counters
8. In a three-stage counter, using RS flip flops what will be the value of the counter
after giving 9 pulses to its input? Assume that the value of counter before giving any
pulses is 1.
a) 1
b) 2
c) 9
d) 10
Ans: b) 2
9. A MOD-16 ripple counter is holding the count 1001. What will the count be after
31 clock pulses?
a) 1000
b) 1010
c) 1011
d) 1101
Ans : a) 1000
10. The terminal count of a typical modulus-10 binary counter is ____________
a) 0000
b) 1010
c) 1001
d) 1111
Ans: c) 1001
11. A decimal counter has ______ states.
a) 5
b) 10
c) 15
d) 20
12. Three decade counters would have ____________
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
13. The final count of a modulus-11 binary counter is ________.
a) 1000
b) 1100
c) 1010
d) 1011
14. A 4-bit counter has a maximum modulus of ____________
a) 3
b) 6
c) 8
d) 16
15. When two counters are cascaded, the overall MOD number is equal to the
________ of their individual MOD numbers.
a) product
b) sum
c) log
d) reciprocal
16. Which of the following is an invalid output state for an 8421 BCD counter?
a) 1110
b) 0000
c) 0010
d) 1001
17. The desirable count for a presettable counter is loaded when
a load = 1 and reset =1
b load = 1 and reset =0
c load = 0 and reset =0
d load = 0 and reset =0 Ans: b load = 1 and reset =0
18. The initial count of the counter is Q0Q1Q2= 010. After 3 clocks the output
Q0Q1Q2 will be

a 101
b 010
c 000
d 111 Ans: a
19. Mod 2 counter and mod 17 counter are cascaded. The modulus of the resultant
counter will be
a mod 34
b mod 9
c mod 17
d mod 2 Ans: a mod 34
20. Among the control signals available in a presettable counter, the least priority is
given to
a clock
b enable
c load
d reset Ans: a clock
21. The final count in a counter designed with 10 T-FFs is
a 1023
b 1024
c 10
d 1025 Ans: a 1023

22. A Seven-segment, common-anode LED display is designed for

a) All cathodes to be wired together
b) One common LED
c) A high signal to turn off each segment
d) Disorientation of segment module
23. Which counter is used for minutes in digital clock?
a) Mod 2 & Decade
b) Mod 12
c) Mod 6 & Decade
d) Mod 5
24 A device which converts BCD to seven segment is called
a) Encoder
b) Decoder
c) Multiplexer
d) Shift register
25. What is the frequency for digital clock circuit
a. 1Hz
b. 50Hz
c. 1KHz
d. 60 Hz
26. The flash type ADC each comparator output is connected to an input
of_________
 a. priority encoder
b. multiplexer
c. demultiplexer
d. decoder
27. The practical use of binary weighted digital to analog converter is limited to
a. R/2R ladder DAC
b. 4 bit DAC
c. Switched resistor DAC
d. Successive-approximation converter.
28. The resolution of a 6 bit digital to analog converter is
a. 1.56%
b. 15.6%
c. 63%
d. 64%

29. What is the purpose for sample and hold circuit in analog to digital converter?
a. sample and hold the D/A converter staircase waveform during the conversion
process
b. stabilize the input analog signal during the conversion process
c. stabilize the comparator's threshold voltage during the conversion process
d. sample and hold the output of the binary counter during the conversion pro
30. Analog to digital conversion includes
(A) quantization
(B) simulation
(C) Data accumulation
(D) summation
31. An ‘n’ bit analog to digital converter is required to convert analog input in the
range (0-5) V to an accuracy of 10 mV. What should be the value of n?
(A) 6
(B) 12
(C) 9
(D) 11
32. An analog voltage in the range of 0-8 V is divided in eight equal intervals for
conversion to a 3 bit digital output. The maximum quantization error is
 (A) 2 V
(B) 1.32 V
(C) 0.5 V
(D) 1 V
33. A digital volt meter uses a
(A) flash ADC
(B) dual-slope ADC
(C) successive approximation ADC
(D) sigma-delta ADC
34. Which of the following is not a type of ADC?
(A) dual-slope ADC
(B) flash ADC
(C) recessive approximation ADC
(D) sigma-delta ADC
35. The throughput of flash ADC is measured in
(A) distance per second
(B) input voltage per second
(C) samples per second
(D) resolution per second
36 Assume that a 4 bit serial in - parallel out shift register is initially clear. Determine
the binary value of the output at 2nd clock pulse for the serial input 1001(first bit – start
from right most bit?
a. 1001
b. 0100
c. 0010
d. 0000
Answer: 0100
37 Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to
store the nibble 1100. What will be the 4-bit pattern after the second clock pulse?
(Right-most bit first)
a. 1100
b. 0011
c. 0000
d. 1111
Answer: 0000
38 With a 200 kHz clock frequency, eight bits can be serially entered into a shift
register in ________
a. 4 μs
b. 40 μs
c. 400 μs
d. 40 ms
Answer: 4 μs
39 Calculate the delay time SISO shift register with 4 stages and 40 kHz clock
frequency
a. 0.01 s
b. 0.001 s
c. 0.0001 s
d. 0.00001 s
Ans : 0.0001 s
40 Using four cascaded counters with a total of 16 bits, how many states must be
deleted to achieve a modulus of 50,000?
A. 50,000
B. 65,536
C. 25,536
D. 15,536
Answer: D. 15,536
41 A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12
ns propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
Ans: d) 60 ns
42 Find the modulus of the counter shown in figure
 a 1
b 2
c 3
d 4 Ans: c 3
43. For the counter shown in figure, the sequence of counter states (Q0Q1) are given
by (Assume the flipflops are initially reset)

a 10, 01, 00, 10…

b 01, 10, 00, 01…
c 10, 01, 11, 10…
d 01, 10, 11, 01… ANS: a 10, 01, 00, 10…
44. BCD input 1000 is fed to a 7-segment display through a BCD to 7 segment
decoder/driver. The segments which will lit up are
a) a,b,d
b) a,,b,c
c) a,b,g,c,d
d) a,,b,c,d,e,f,g
 Part B (2 Mark)
1. Write the logical expression for the inputs to the D-FF from the state table shown is

2. A 5-bit binary-weighted DAC has an input voltage at each bit as either 0V or +5V for
logic 0 and 1 respectively, Calculate its step size if the feedback resistor is 15Kohm and LSB
resistor is 100Kohm.
3. A digital to analog converter with a full-scale output voltage of 3.5 V has a resolution
close to 14 mV. Find the bit size.
4. Define shift register
5 what are the different types of shift register
6 What is the difference between serial and parallel transfer?
7 What is the minimum number of flip flop required to implement a modulo 21
synchronous counter?
8 Why are shift register considered to be a memory devices?
9 How are shift left or shift right transfer register built?
10 Explain how a flip flop can store a data bit.
11 Write the different application in flip flop

Part-C (3 Mark)
1. Draw the parallel in serial out circuit diagram.
2. Draw the serial in parallel out circuit diagram and consider the shift register is
cleared, assume the input bits are given as ‘1011’ with right most bit as the first bit to enter
the shift register. After 2 clock pulses what will be the output bits?
Answer: 1100
3. Write the state transition table for the given synchronous counter for sequence: 0 → 1
→ 3 → 4 → 5 → 7 → 0, using T flip-flop
4. Design a modulus 5 asynchronous counter using JK Flipflop.
5. Design a synchronous random counter to count the sequence 2,3,0,1,2… using D – FF.
6. Show the seven segment LED display for which segment illuminated in the input codes of
DCBA = 0011.
7. Draw the circuit diagram of R/2R ladder digital to analog converter
8. Write a short note on flash type ADC.