Fault Detection in Digital

Circuits
Presented by
Professor Haranath Kar

Department of Electronics and Communication Engineering

Motilal Nehru National Institute of Technology Allahabad
Allahabad-211004, India
 Types of faults
• Digital circuits may suffer two classes of faults:
a) Temporary faults:
(Occur due to noise and the nonideal transient behaviour of switching
components)
b) Permanent faults:
(Occur due to component failures)

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 Transient Phenomenon
• Consider the function
1→0
𝑧 𝑥𝑦 00 01 11 10

0 1 1→0 ∗1→0→1

1 0→1
1 1 1
0→1

(* if 𝒑𝒅𝟐 𝒑𝒅𝟏

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 Glitch and Hazard
• The output of a combinational circuit may make a transition even
though the patterns applied at its inputs do not imply a change. These
unwanted switching transients are called “glitches”.
• A circuit in which a “glitch” may occur under appropriate inputs is
said to have a “hazard”.

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 Static Hazards
• Static-1 Hazard 𝟏 𝟏
Output pattern: 𝟏 → 𝟎 → 𝟏
(may occur in two-level AND-OR realization) 𝟎

• Static-0 Hazard
𝟏
Output pattern: 𝟎 → 𝟏 → 𝟎
(may occur in two-level OR-AND realization) 𝟎 𝟎

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 Static Hazards (continued…)
• A static hazard is a situation in which a single input-variable change
might cause a momentary incorrect output, when in fact the output
should remain constant.
• A minimal realization of a digital circuit might not be hazard-free.

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 Elimination of Static Hazards
• Consider the function 𝒇 𝒙, 𝒚, 𝒛 = ∑(𝟐, 𝟑, 𝟓, 𝟕)
𝑥̅
𝑧 𝑥𝑦 00 01 11 10 𝑦
0 1 𝑥
𝑧
1
1 1 1 𝑦
𝑧
𝑓 𝑥, 𝑦, 𝑧 = 𝑥̅ 𝑦 + 𝑥𝑧 + 𝑦𝑧
• Static hazard can be removed by including the prime implicant 𝒚𝒛 in the expression
for ‘𝒇’.

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 Dynamic Hazards
• Dynamic hazards are a consequence of multiple static hazards in a multilevel circuit.
1 1 1 1

0 0 0 0
The necessity of eliminating hazards confronts the designer with two conflicting
considerations.
1. Simplicity of the circuit: Minimal functions are most vulnerable to hazards.
2. Reliability of the circuit: To avoid hazards, it is necessary to add some redundant gates.

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 Why do we require testing?
Various types of errors can occur during the manufacturing process.
• Errors during the design phase
• Bugs during synthesis (in the CAD tools used)
• Faults during fabrication
There are billions of transistors in today's chips.
• Possibility of faults creeping in is also significant.
Testing is used to detect the presence of faults in a given circuit.
• No amount of testing can ensure that the circuit is free of faults
• By testing, we can boost our confidence in the correct working of the circuit.

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 When to do testing?
Testing can be done at various levels.
• Chip level: when chips are manufactured
• Board level: when chips are assembled on the boards
• System level: when several boards are assembled together
Rule of thumb:
• Early detection of a fault reduces the cost of testing.
• It is 10 times more expensive to test a digital system as we move to the next
higher level (Chip → Board → System).

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 Problem in Fault Detection
• The number of possible physical defects in the circuit may be excessive.
• Solution: Study the physical defects and construct some fault models. A fault
model identifies the targets for testing. A fault model makes the analysis
possible.

How many faults are getting tested?

• Fault coverage = (Number of detected faults/Total number of faults) 100 %

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 Fault Models

To reduce the complexity of test generation, one needs to

model the actual defects that may occur in a chip with fault
models.

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 Structural Fault Models
• Structural fault models
In structural testing, we need to ensure that the interconnections in the given
structure are fault-free and are able to carry both 0 and 1 signals.
• Stuck-at 0 (s-a-0) fault
• Stuck-at 1 (s-a-1) fault
A stuck-at fault does not always indicate that the line is shorted to ground or a
power line. It could serve as a model for a variety of other cuts and shorts, both
internal and external to a gate.

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 Switch-level Fault Models
• Switch-level fault models
• Switch-level fault modeling is concerned with faults in transistors and
interconnects in a switch-level description of a circuit.
• This fault model has primarily been used with MOS technologies, specifically
CMOS technology.
• Stuck-open fault: A transistor has become permanently nonconducting due to some
defect.
• Stuck-on fault: A transistor has become permanently conducting due to some defect.

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 Bridging Fault Models
 Two or more normally distinct lines are shorted together.
 Input bridging: Can form wired-logic.
 Feedback (Input-to-output) bridging: Can cause oscillations or
latching (additional memory)

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 Fault detection methods for combination
circuits
 Fault table method
 Path-sensitizing method
 Boolean difference method

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 Derivation of minimal set of fault-
detection tests
Inputs 𝒇 Outputs in presence of faults
𝑚 𝐴𝐵𝐶
𝐴 𝑓 𝑓 𝑓 𝑓 𝑓 𝑓 𝑓 𝑓
1
𝐵 𝑛 000 1 1 1 1 0 1 1 1 1
001 0 0 0 0 0 0 0 1 1
𝑝 010 1 1 1 1 0 1 1 1 1
2 011 0 0 0 0 0 1 0 1 1
𝐶′ 𝑓 = 𝐴𝐵 + 𝐶′
𝑞 100 1 1 1 1 0 1 1 1 1
101 0 0 0 0 0 0 1 1 1
110 1 1 1 1 1 1 1 1 1
111 1 0 0 0 1 1 1 1 1

Circuit to be tested Truth Table 17

 Fault Table
Inputs Possible faults
𝐴𝐵𝐶 𝑚 ,𝑛 ,𝑝 𝑞 𝑚 𝑛 𝑝 ,𝑞
000 1
001 1
010 1
011 1 1
100 1
101 1 1
110
111 1

Essential Tests: {3, 5, 7} Minimal Complete Test Set: {3, 5, 7, 0 or 2 or 4} 18

 Path sensitizing method
𝑎 Path Input Other input variables required to Test nos. Faults
𝑥 sensitize the path detected
1
𝑏 𝑎𝑑𝑒 𝑥=0 𝑦 = 1, 𝑧 = 0 2 𝑎 ,𝑑 , 𝑒
𝑦
𝑥=1 𝑦 = 1, 𝑧 = 0 6 𝑎 ,𝑑 , 𝑒
𝑑 𝑏𝑑𝑒 𝑦=0 𝑥 = 1, 𝑧 = 0 4 𝑏 ,𝑑 , 𝑒
2 𝑒 𝑓 𝑦=1 𝑥 = 1, 𝑧 = 0 6 𝑏 ,𝑑 , 𝑒
𝑧
𝑐 𝑐𝑒 𝑧=0 𝑥=𝑦=0 0 or 2 or 4 𝑐 ,𝑒
Circuit or, 𝑥 = 0, 𝑦 = 1
or, 𝑥 = 1, 𝑦 = 0
𝑧=1 𝑥=𝑦=0 1 or 3 or 5 𝑐 ,𝑒
or, 𝑥 = 0, 𝑦 = 1
or, 𝑥 = 1, 𝑦 = 0

Essential Tests: {2, 4, 6} Minimal Complete Test Set: {2, 4, 6, 1 or 3 or 5} 19

 Boolean Difference
• If 𝒇(𝒙) = 𝒇 𝒙𝟏 , … , 𝒙𝒊 , … , 𝒙𝒏 , then
𝒅 𝒇(𝒙)
𝒅𝒙𝒊
= 𝒇 𝒙𝟏 , … , 𝒙𝒊 , … , 𝒙𝒏 ⊕ 𝒇 𝒙𝟏 , … , 𝒙𝒊 , … , 𝒙𝒏

= 𝒇 𝒙𝟏 , … , 𝒙𝒊 𝟏 , 𝟎, 𝒙𝒊 𝟏 , … , 𝒙𝒏 ⊕ 𝒇 𝒙𝟏 , … , 𝒙𝒊 𝟏 , 𝟏, 𝒙𝒊 𝟏 , … , 𝒙𝒏

• If 𝒇(𝒙) = 𝒙𝟏 𝒙𝟐 + 𝒙𝟑, then

𝒅 𝒇(𝒙)
𝒅𝒙𝟏
= 𝟎 . 𝒙𝟐 + 𝒙 𝟑 ⊕ 𝟏 . 𝒙𝟐 + 𝒙 𝟑 = 𝒙 𝟑 ⊕ 𝒙 𝟐 + 𝒙 𝟑 = 𝒙 𝟐 𝒙 𝟑
𝒅 𝒇(𝒙) 𝒅𝒇(𝒙)
• 𝒅𝒙𝒊 𝒅𝒙𝒊
𝒅 𝒇(𝒙) 𝒅 𝒇(𝒙)
• 𝒅𝒙𝒊 𝒅𝒙𝒊

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 Fault Detection using Boolean Difference
• Set of tests which detect s-a-0 fault
𝒅 𝒇(𝒙)
𝒊 𝒅𝒙
𝒊

• Set of tests which detect s-a-1 fault

𝒅 𝒇(𝒙)
𝒊 𝒅𝒙𝒊

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Example

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 Example (continued…)
• To detect s-a-0 fault at line ‘ ’ :
𝒅𝒇
𝒙𝟏 𝒅𝒙𝟏
=𝟏

⇒ 𝒙𝟏 𝒙𝟐 𝒙𝟑 =1
Test no. : 6
• To detect s-a-1 fault at line ‘ ’ :
𝒅𝒇
𝒙𝟏 𝒅𝒙 = 𝟏
𝟏

⇒ 𝒙𝟏 𝒙𝟐 𝒙𝟑 =1
Test no. : 2

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 Example (continued…)
• To detect s-a-0 fault at line ‘ ’ :
𝒅𝒇
𝒈 𝒅𝒈 = 𝟏

⇒ ( 𝒙𝟏 𝒙𝟐 ) . 𝒙𝟑 =1
Test no. : 6
• To detect s-a-1 fault at line ‘ ’ :
𝒅𝒇
𝒈𝒅𝒈 = 𝟏

⇒ (𝒙𝟏 + 𝒙𝟐 ) 𝒙𝟑 = 𝟏
Test no. : 0 or 2 or 4

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Thank You