CHAROTAR UNIVERSITY OF

SCIENCE AND TECHNOLOGY

V. T. Patel Department of Electronics &
Communication

EC-405.01
Digital System Design
Yogesh Tiwari

Course Description & Prerequisites

Introduction to digital system design & How to design a
small digital system
No connection with VLSI
Gate level implementation

Emphasis:
Practical
design
circuit implementation..

techniques

and

Prerequisites: Basic knowledge of Digital electronics

Lab Experiments
The lab for this course is located in AP1&AP2.
Language
VHDL(Xillinx)
Verilog

Lab Kits(CPLD Boards)

Krypton
Helium

Syllabus
Introduction to Programmable logic devices
Electronic Systems Design
MSI & LSI circuits and their Applications
Sequential Machines
Design for Testability
Design Application

Recommended Study Material

Text Books:

Reference books
1.An Engineering Approach To Digital Design,
William I. Fletcher, PHI, Digital System
Design ,John Wakerley. Prentice Hall
International, 2000

1.Digital Logic Applications and Design, John

M. Yarborough, Thomson Publications
6

Are you familiar with these words?

Combinational circuits
Sequential circuits
Kmap,Demorgans law, Propagation delay
Latch,flipflop
Edge triggered flipflop, Level triggered flipflop
Synchrounous and asynchronous sequential circuit
State table,State diagram
Serial adder

Setup Time & Hold Time

Every flip-flop has restrictive time regions around the active

clock edge in which input should not change.
We call them restrictive because any change in the input in
this regions the output may not be the expected one.

 As it may be derived from either the old input,

the new input, or even in between the two..
Here we define, two very important terms in
the digital clocking : Setup and Hold time.
The setup time is the interval before the clock
where the data must be held stable.
The hold time is the interval after the clock
where the data must be held stable.

 In the figure, the shaded region is the restricted

region.
The shaded region is divided into two parts by
the dashed line.
The left hand side part of shaded region is the
setup time period and the right hand side part is
the hold time period.
If the data changes in this region, as shown the
figure. The output may, follow the input, or many
not follow the input, or may go to metastable
state.

Metastability
Whenever there are setup and hold time violations in
any flip-flop, it enters a state where its output is
unpredictable: this state is known as metastable state
(quasi stable state); at the end of metastable state, the
flip-flop settles down to either '1' or '0'. This whole
process is known as metastability.
When a flip-flop is in metastable state, its output
oscillate between '0' and '1' as shown in the figure
(here the flip-flop output settles down to '0') . How
long it takes to settle down, depends on the
technology of the flip-flop.

Metastability IIlustrated as a Ball

Dropped on a Hill

Clock skew
Synchronous design assumes all flip-flops are clocked at the same time.
In real designs, this is not always the case.
The same signal arriving at different parts of the design with different
phase is known as skew. Skew normally refers to clock signals.
Due to:
Wire delay, gates of the path

Behavior of digital circuits :

Steady sate vs Transient
STEADY STATE behavior of a circuit is the value of the
output after the inputs have been stable for a long
time.
TRANSEINT behavior of a circuit is the value of the
output while (or soon after) the input change.
We have been analyzing and designing digital
circuits assuming steady state conditions.
In reality transient behavior is important.

Gate Delays and Timing Diagrams

Gate Delays

Gate Delays and Timing Diagrams

Timing Diagrams
Circuit timing is very important consideration while
designing any electronic system
We will consider the following timing issues:

For flip-flops:
Setup and hold time
Propagation delay
For combinational circuit:
Propagation delay
For sequential circuit:
Combining delay of flip flops and combinational
circuit

Gate Delays and Timing Diagrams

Timing Diagrams

What is Hazards??

A hazard or glitch in digital logic is a fault in the logic

system due to a change at the input
Causes and effects:
Due to some form of delay caused by logic elements (NOT, AND, OR gates etc).
results in the logic not performing its function properly.

Hazards in digital circuits

What are the various types of Hazards in Combinational Circuits?

Static Hazards: "When one input variable changes, the output

changes momentarily when it shouldn't"
Dynamic Hazards:-"A dynamic hazard is the possibility of an
output changing more than once as a result of a single input
change
Function Hazards:-Function hazards are non-solvable hazards
which occurs when more than one input variable changes at
the same time.

Static Hazards:
Static-1 Hazard:
The output should be 1 but goes momentary
to 0 as a result of an input change.
(possible in AND-OR circuits)
Static-0 Hazard:
The output should be 0 but goes momentary
to 1 as a result of an input change.
(possible in OR-AND circuits)

Dynamic Hazards
The output changes more than once ( generally 3 or
more) as a result of a single input change
(impossible in 2-level circuits).
Dynamic hazards often occur in larger logic circuits
where there are different routes to the output (from the
input).

Static 1 Hazard

assume propagation delay 10ns for all gates

1 0 1

A static-1 hazard exists in the following AND-OR circuit

when A = 1, C = 1 and B changes from 1 to 0

Hazard Detection and Removal

When circuits are implemented as 2-level SOP (2-level POS), we can
detect and remove hazards by inspecting the K-Map and adding
redundant product (sum) terms

Observe that when input B changes from 1->0, that we jump from one
product term to another product term.
If adjacent minterms are not covered by the same product term, then a
HAZARD EXISTS!!!

Hazard Detection and Removal

Add a loop to the map covering such adjacent 1s, and then add the
corresponding gate to the circuit

The extra product term(AC) does not include the changing input variable(B),
keeps on 1 (for A=C=1) when B changes from 1 to 0, therefore serves to
prevent possible momentary output glitches due to this variable.

Hazard Free circuit

Important to note
We will only consider hazards which occurs when a single input variable
changes.
Analysis begin by determining the transient output function,Ft,which
represents the behavior of the network under transient conditions.
The transient output for a network is determined in the same way as
ordinary output function except a variable xi and xi are treated as
independent variables.
This must be done since during transient conditions xi and xi may both
momentarily assume the same values. This means the following theorems
of Boolean algebra cannot be used when manipulating Ft:
XX=0,X+X=1,X+XY=X+Y
The associative, distributive and demorgans laws as well as XX=X,X+XY=X
etc. can be used.
Although in steady state B and B are complements under transient
conditions they are not.
Thus in analysis of a network for hazards, we must treat a variable and its
complement as if they were two independent variables.

Practice example(static 1 hazard)

Procedure to find static 1 hazards

1) Determine the transient output function of the network
Ft ,and reduce Ft to sum of products from each variable
and its complement as separate variables.

2)Plot 1 terms of Ft on a K-MAP. (If F is in SOP form

each product term is called a 1 term of F.)
3) Examine each pair of adjacent input states for which Ft is
1.If two 1s in adjacent squares on the map of Ft are
covered by the same 1 term, changing the input to the
network between the corresponding two input states
cannot cause a hazard. However if two 1s in adjacent
squares on the map are covered by single term hazard is
present

Static-0 hazard
"A static-0 hazard occurs in OR-AND circuits when an input
variable and its complement are connected to two different OR
gates.

Ft=(A+B)(B+C)

The procedure to find and eliminate static-0 hazards using K-maps

is done in a dual way to finding static-1 hazards

The new hazard free circuit

Procedure to find static 0 hazards

1) If the sum of products for Ft does not contain the product of
a variable and its complement (e.g.term aa), no 0 Hazards are
present.

2) If sum of products for Ft does contain the product of a

variable and its complement, a 0 hazard may be
present.
3) Obtain the POS for Ft by factoring or other means.

4) Examine each pair of adjacent input states for which Ft

is 0.If there is no 0 term which includes both input
states of the pair, a 0 hazard is present.

Practice example (static 0 hazard)

Dynamic hazard
Definition: A dynamic hazard is the possibility of an output changing more than once
as result of a single input change..

It is caused by structure of a circuit & circuit with more than two levels
It occurs if there are more than 3 paths between input and output.
This is necessary since a dynamic hazards involves triple change in output, so
the effect of the input must reach output by 3 different times.
A network may have a dynamic hazard even if it is free of static hazards.

Detecting and eliminating dynamic hazards in a multi-level circuit is beyond

the scope. One solution for dealing with dynamic hazards in a circuit is to
convert the circuit to it's two-level form and then check for static hazards.
What is relevant is to recognize and trace a dynamic hazard in a circuit.

Example (Dynamic hazard)

Finite State Machine

or
Finite state automata
or
State machine

Introduction:
If a combinational logic circuit is an implementation of
a Boolean function, then a sequential logic circuit can
be considered an implementation of a finite state
machine.
The machine is in only one state at a time; the state it
is in at any given time is called the current state.
It can change from one state to another when initiated
by a triggering event or condition; this is called
a transition.
A particular FSM is defined by a list of its states, and
the triggering condition for each transition.

 Each state is represented with a circle, and each transition with an arrow.
The behavior of state machines can be observed in many devices in
modern society which perform a predetermined sequence of actions
depending on a sequence of events with which they are presented.
Simple examples are :
vending machines which dispense products when the proper combination
of coins is deposited

elevators which drop riders off at upper floors before going down.
traffic lights which change sequence when cars are waiting..
combination locks which require the input of combination numbers in the
proper order.
Turnstile which is used to control the access to mall and subways..

Turnstile
Used to control access to subways and amusement
park rides, airport, mall is a gate with three rotating
arms at waist height, one across the entryway.

 There are two types of FSMs which are

popularly used in the digital design.
Moore machine
Mealy machine

Moore machine
In Moore machine the output depends only on
current state.
Mealy machine
In Mealy machine the output depend on both
current state and input.

FSM can be represented in two forms:

Graph Notation
State Transition Table

Mealy Machine
Output Depends on State and Inputs

transition condition 1 /
output 1
state 2

state 1

transition condition 2 /
output 2

Output is with the transition

Moore Machine
Output Depends on State Only
transition
condition 1
state 1 /
output 1

state 2 /
output 2
transition
condition 2

Output is written within the state

Mealy FSM Example

sequence detector
Mealy FSM that Recognizes Sequence
0/0

1/0

S0
reset

Meaning
of states:

1/0
S1

0/1
S0: No
elements
of the
sequence
observed

S1: 1
observed

Moore FSM - Example 1

Moore FSM that Recognizes Sequence 10

1
S0 / 0

reset
Meaning
of states:

S0: No
elements
of the
sequence
observed

0
S1 / 0

0
S1: 1
observed

S2 / 1

S1: 10
observed

Design of a 101 sequence detector

Melay state machine

101 sequence detector

101 sequence detector

Moore state machine

1010 sequence detector

Melay state machine

11011 sequence detector

Melay state machine

Example 1:

Design a Melay state graph with one input x and one output z.
The output z should be 1 if the input sequence ends either in
010 or 1001,and z should be zero otherwise.

Solution:

Constructing State Graphs

Although there is no one specific procedure which can be
used to derive state graphs or tables for every problem, the
following guidelines should prove helpful:
1. First, construct some sample input and output sequences to
make sure that you understand the problem statement.
2. Determine under what conditions, if any, the circuit should
reset to its initial state.
3. If only one or two sequences lead to a nonzero output, a
good way to start is to construct a partial state graph for
those sequences.

A sequential network has one input x and

output z.
Draw a Melay state graph for:
The output z=1 if the total number of 1s
received is divisible by 3(Note:0,3,6,9 are
divisible by 3

Constructing State Graphs

4. Another way to get started is to determine what sequences
or groups of sequences must be remembered by the circuit
and set up states accordingly.
5. Each time you add an arrow to the state graph, determine
whether it can go to one of the previously defined states or
whether a new state must be added.
6. Check your graph to make sure there is one and only one
path leaving each state for each combination of values of the
input variables.
7. When your graph is complete, test it by applying the input
sequences formulated in part 1 and making sure the output
sequences are correct.

Example 2:
Design a Moore state graph with one input x and one
output z. The output z should be 1 if the total number of
1s received is odd and at least two consecutive 0s have
been received ,and z should be zero otherwise.

Solution:

Example 3:
A sequential circuit has one input (X) and one output
(Z). The circuit examines groups of four consecutive
inputs and produces an output Z = 1 if the input
sequence 0101 or 1001 occurs. The circuit resets after
every four inputs. Find a Mealy state graph. A typical
input and output sequence is:

Solution:

A sequential network has one input (x) and one output (z). The output
becomes 1 and remains 1 thereafter when at least two 0s and at least two
1s have occurred as inputs, regardless of the order of occurrence. Draw a
state graph(Moore type) for the network (9 states are sufficient)

 Design of networks for arithmetic operations:

Objective:

We will see the concept of using control circuit to control

the sequence of operations in a digital system.
A control network is a sequential network which puts out
a sequence of control signals.
These signal cause operation such as addition and
shifting to take place at appropriate times.

Concept of serial addition

Serial adder with accumulator

Timing of serial adder with accumulator

Serial adder with accumulator

Control State Graph and Table:

75

Control unit design of a serial adder

76

Design of a binary multiplier:

77

Block diagram of binary multiplier

78

79

Binary Multiplier
State graph for Binary Multiplier Control

80

Multiplier control with counter:

81

For n=4,2 bit counter is needed.

4-bit array multiplier:

84

85

Design of a binary divider

Block diagram of a binary divider

 Overflow(v) occurs if dividend > divisor

E.g. if we attempt to divide 34 by 4,the content of registers
would be
0100010
100

Since subtraction is carried out, and we enter a quotient

bit of 1 in rightmost place in dividend register.

We can not do this because rightmost place contains the

least significant bit of dividend and entering a quotient bit
her would destroy that dividend bit..

State diagram

State table and state equation

Control circuit design

st
1

Internal Paper Solution:

Q-2(a)
Used to control access to subways and
amusement park rides, airport, mall is a gate
with three rotating arms at waist height, one
across the entryway.

Q-2(c)

 Algorithmic State Machine(ASM)

Chart

Introduction:
Alternative method to represent FSM.
Although it contains same amount of information but it is more
descriptive.
State diagram is useful when machine has a few inputs and
outputs.
ASM chart may be more convenient for larger machines.
ASM charts are also called SM (state machine) charts.
An SM chart differs from an ordinary flowchart in that certain
specific rules must be followed in constructing the SM chart.
When these rules are followed, the SM chart is equivalent to a
state graph, and it leads directly to a hardware realization.

State box represents a state.

Equivalent to a node in a state diagram or a row in a state table.
Moore type outputs are listed inside of the box.
It is customary to write only the name of the signal that has to be asserted
in the given state, e.g., z instead of z=1.

 Decision box
Indicates that a given condition is to be tested and the exit path is to be
chosen accordingly
The condition expression consists of one or more inputs to the FSM.
.

Conditional output box

The conditional output box describes certain outputs which only become active if
certain conditions described in terms of the system inputs become true.
The outputs are given in the conditional output list and the box is always
associated with a decision box which defines the condition.
This box is always associated with a Mealy model state machine

ASM Block:

Each ASM block contains exactly one state box together with the decision
boxes and conditional output boxes associated with that state.
An ASM block has only one entry path, but any number of exit paths.

Example:ASM Block

Example of Link Paths

When state S1 is entered, Z1 and Z2 become 1.
If X1=0, Z3 and Z4 also become 1. If X2=0, then the exit to the next state will occur at
exit path 1 (blue line); if X2=1, then the exit to the next state will occur at exit path 2 (red
line)
If X1=1 and X3=0, then Z5 also becomes 1 and the exit to the next state will occur
at exit path 3 (green line)

a)
If a 1 is received, we have identified the start of a possible sequence, hence, move to
the next state (state S0 detects the first 1)

b)
If a 0 is then received, then we have identified the second digit in the
sequence, move to the next state (state S1 detects the second digit 0)

 c)
If a 1 is received then the sequence has been detected and we need to assert
the output (state S2 detects the final digit 1). As this could also be the start
of another sequence, we move back to state S1 to detect the possible next
0.

e)
If we are in S2 and a 0 is received, then we havent detected a correct
sequence, so return to state S0 and start again.

S3/z

SM Chart for Binary Multiplier

 ASM Chart for Electronic Dice Game

Block Diagram

The input signals to the control circuit are defined as follows:

D7 1 if the sum of the dice is 7
D711 1 if the sum of the dice is 7 or 11
D2312 1 if the sum of the dice is 2, 3, or 12
Eq 1 if the sum of the dice equals the number stored in the point register
Rb 1 when the roll button is pressed
Reset 1 when the reset button is pressed
The outputs from the control circuit are defined as follows:
Roll 1 enables the dice counters
Sp 1 causes the sum to be stored in the point register
Win 1 turns on the win light
Lose 1 turns on the lose light

Electronic Dice Game

Two counters are used to simulate the roll of the
dice.

Each counter counts in the sequence 1, 2, 3,

4,5,6,1,2, . . . .
Thus, after the roll of the dice, the sum of the
values in the two counters will be in the range 2
through 12.

Rules of the Game

1. After the first roll of the dice, the player wins if the
sum is 7 or 11. He loses if the sum is 2, 3, or 12.
Otherwise, the sum which he obtained on the first
roll is referred to as his point, and he must roll the
dice again.

2. On the second or subsequent roll of the

dice, he wins if the sum equals his point, and
he loses if the sum is 7. Otherwise, he must
roll again until he finally wins or loses.

Flowchart for Dice Game

SM Chart for Dice Game

State Graph for Dice Game Controller

 As a final note on dynamic hazards, it should

be noted that if all static hazards have been
eliminated from a circuit, then dynamic
hazards cannot occur.

Function Hazards
Function hazards are non-solvable hazards which occurs
when more than one input variable changes at the same
time. Hazards such as function hazards can not be logically
eliminated as the problem lies with actual specification of
the circuit. The only real way to avoid such problems is to
restrict the changing of input variables so that only one
input should change at any given time.
Restrictions are not always possible, for instance let us
imagine some logic circuit that has two inputs. One input is
used for a clock signal, and the other is connected to a
random noise source that we wish to measure. It should be
clear that restrictions in this case would not be an effective
solution.

Synchronous Sequential Circuit

State changes synchronized by the common
clock pulse
Input changes occur between clock pulses
Outputs are read during (or immediately
proceeding) the clock pulse.
Unsuitable Situation:
Circuit is large, Clock skew can not be avoided

Asynchronous Sequential Circuit

Not Synchronized by a Common Clock

States Change Immediately after Input Changes
Timing is a Major Problem
Unequal delays through various paths in the circuit
There are two modes of operations of asynchronous
sequential machines depending upon the type of
input signals.
Fundamental mode & pulse mode

 Fundamental Mode:
All of the input signals are considered to be levels.
This mode assumes that the input signals will be changed
only when the circuit is in a stable state and that only one
variable can change at a given time.

Pulse mode:
The inputs are pulses rather than levels.
In this mode of operation the width of the input pulses is
critical to the circuit operation.

Wire delay
Gates are connected together with wires and these wires do delay the
signal they carry, these delays become very significant when
frequency increases, say when the transistor sizes are sub-micron.
Sometimes wire delay is also called flight time (i.e. signal flight time
from point A to B). Wire delay is also known as transport delay.

Clock skew

 "A static-0 hazard occurs in OR-AND circuits

when an input variable and its complement
are connected to two different OR gates

Hazards
Hazard a single variable change produces a
momentary output change (commonly referred t
as a glitch) when no output change should occur.
Types: Static-1 hazard
Static-0 hazard
Dynamic hazard

 http://www.cs.ucr.edu/~jtarango/cs122a/code
/example_fsm.vhdl
Good for diff
http://www.rsonline.com/designspark/electronics/knowledg
e-item/how-to-implement-state-machines-inyour-fpga
Good for state ecncoding

Moore machineThe FSM uses only entry actions, i.e., output depends only on the
state. The advantage of the Moore model is a simplification of the behaviour.
Consider an elevator door. The state machine recognizes two commands:
"command_open" and "command_close" which trigger state changes. The entry
action (E:) in state "Opening" starts a motor opening the door, the entry action in
state "Closing" starts a motor in the other direction closing the door. States
"Opened" and "Closed" stop the motor when fully opened or closed. They signal
to the outside world (e.g., to other state machines) the situation: "door is open" or
"door is closed".
Fig. 7 Transducer FSM: Mealy model example
Mealy machineThe FSM uses only input actions, i.e., output depends on input and
state. The use of a Mealy FSM leads often to a reduction of the number of states.
The example in figure 7 shows a Mealy FSM implementing the same behaviour as
in the Moore example (the behaviour depends on the implemented FSM execution
model and will work, e.g., for virtual FSM but not for event driven FSM). There are
two input actions (I:): "start motor to close the door if command_close arrives"
and "start motor in the other direction to open the door if command_open
arrives". The "opening" and "closing" intermediate states are not shown.

 If a combinational logic circuit is an implementation of a Boolean function,

then a sequential logic circuit can be considered an implementation of a
finite state machine. The machine is in only one state at a time; the state it
is in at any given time is called the current state. It can change from one
state to another when initiated by a triggering event or condition; this is
called a transition. A particular FSM is defined by a list of its states, and
the triggering condition for each transition.
The behavior of state machines can be observed in many devices in
modern society which perform a predetermined sequence of actions
depending on a sequence of events with which they are presented. Simple
examples are vending machines which dispense products when the proper
combination of coins is deposited,elevators which drop riders off at upper
floors before going down, traffic lights which change sequence when cars
are waiting, and combination locks which require the input of combination
numbers in the proper order.

Hazards in Combinational Circuits

Types of Hazards

Hazards in Combinational Circuits

Hazards in 2-level Circuits

Introduction

Assignment example (static 0 hazard)

assignment example(static 1 hazard)

Hazards do not hurt synchronous

circuits

Asynchronous circuit
General block diagram

 Just like a synchronous sequential circuits, the

asynchronous sequential circuits are also feedback
circuits.
The difference is that there is no memory element in
asynchronous sequential circuit and they are not clock
driven.
Due to absence of memory element, the
implementation of excitation Boolean function must be
hazard free.
If the designer design the circuit based on minimized
Boolean functions, there will be some possibility of
static hazard in the circuit.

 Therefore during implementation of any asynchronous sequential circuit,

the designer should design the circuit in hazard free form.
Delay element is a gate circuit which can provide propagation delay.
The main characteristic of asynchronous sequential circuit is that only one
input is allowed to change at any instant.
There are two different conditions of any asynchronous sequential circuit,
namely stable and unstable state.
At any instant, the state of circuit is defined by logical values of input
variable and present state of circuit.

When next state is same as present state, the circuit is in stable state

Sequential Circuits