Coa Unit-4 Notes

Input-Output Organization 1
INPUT-OUTPUT ORGANIZATION
• Peripheral Devices
• Input-Output Interface
• Asynchronous Data Transfer
• Modes of Transfer
• Priority Interrupt
• Direct Memory Access
• Input-Output Processor
• Serial Communication
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Input-Output Organization 2 Peripheral Devices
PERIPHERAL DEVICES
Input Devices Output Devices

• Keyboard • Monitor (VDU)
• Optical input devices •Card Puncher, Paper Tape Puncher
- Card Reader • CRT
- Paper Tape Reader • Printer (Impact, Ink Jet,
- Bar code reader Laser, Dot Matrix)
- Digitizer • Plotter
- Optical Mark Reader • Analog
• Magnetic Input Devices • Voice
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices

Input-Output Organization 3 Input/Output Interfaces
INPUT/OUTPUT INTERFACE
• Provides a method for transferring information between internal
storage (such as memory and CPU registers) and external I/O
devices
• Resolves the differences between the computer and peripheral
devices
– Peripherals - Electromechanical Devices
– CPU or Memory - Electronic Device
– Data Transfer Rate

» Peripherals - Usually slower
» CPU or Memory - Usually faster than peripherals
• Some kinds of Synchronization mechanism may be needed
– Unit of Information
» Peripherals – Byte, Block, …
» CPU or Memory – Word
– Data representations may differ

I/O BUS AND INTERFACE MODULES

I/O bus
Data
Processor Address
Control
Interface Interface Interface Interface
Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal
Each peripheral has an interface module associated with it
Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Typical I/O instruction
Op. code Device address Function code
(Command)

I/O BUS AND MEMORY BUS

Functions of Buses
•MEMORY BUS is for information transfers between CPU and the

MM
* I/O BUS is for information transfers between CPU

and I/O devices through their I/O interface

I/O INTERFACE
Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register
Internal bus
CPU Chip select CS
I/O
Register select RS1 Control Control Device
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register
CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Programmable Interface
- Information in each port can be assigned a meaning
depending on the mode of operation of the I/O device
→ Port A = Data; Port B = Command; Port C = Status
- CPU initializes(loads) each port by transferring a byte to the Control Register
→ Allows CPU can define the mode of operation of each port
→ Programmable Port: By changing the bits in the control register, it is
possible to change the interface characteristics
Input-Output Organization 7 Asynchronous Data Transfer
ASYNCHRONOUS DATA TRANSFER

Synchronous and Asynchronous Operations
Synchronous - All devices derive the timing
information from common clock line
Asynchronous - No common clock
Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted
Two Asynchronous Data Transfer Methods

Strobe pulse
- A strobe pulse is supplied by one unit to indicate
the other unit when the transfer has to occur
Handshaking
- A control signal is accompanied with each data
being transmitted to indicate the presence of data
- The receiving unit responds with another control
signal to acknowledge receipt of the data
STROBE CONTROL
* Employs a single control line to time each transfer
* The strobe may be activated by either the source or
the destination unit
Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer
Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit
Timing Diagram Timing Diagram

Valid data Valid data
Data Data
Strobe Strobe

HANDSHAKING
Strobe Methods
Source-Initiated
The source unit that initiates the transfer has

no way of knowing whether the destination unit
has actually received data
Destination-Initiated
The destination unit that initiates the transfer

no way of knowing whether the source has
actually placed the data on the bus
To solve this problem, the HANDSHAKE method

introduces a second control signal to provide a Reply
to the unit that initiates the transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE

Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit
Valid data
Data bus
Timing Diagram
Data valid
Data accepted
Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit
Timing Diagram Ready for data
Data valid
Valid data
Data bus
Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.
Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).
* Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism
Asynchronous Serial Transmission

The transfer of data between two units is serial or parallel.
• In parallel data transmission, n bit in the message must be

transmitted through n separate conductor path. But in serial
transmission, each bit in the message is sent in sequence one at a
time. Parallel transmission is faster but it requires many wires. It is
used for short distances and where speed is important. Serial
transmission is slower but is less expensive.
• In Asynchronous serial transfer, each bit of message is sent a

sequence at a time, and binary information is transferred only when
it is available. When there is no information to be transferred, line
remains idle.

Asynchronous Serial Transmission

In this technique each character consists of three points:
1. Start Bit- First bit, called start bit is always zero and used to indicate the
beginning character.
2. Stop Bit- Last bit, called stop bit is always one and used to indicate end of
characters. Stop bit is always in the 1- state and frame the end of the
characters to signify the idle or wait state.
3. Character Bit- Bits in between the start bit and the stop bit are known as
character bits. The character bits always follow the start bit.

ASYNCHRONOUS SERIAL TRANSFER

Asynchronous serial transfer
Four Different Types of Transfer Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer
Asynchronous Serial Transfer
- Employs special bits which are inserted at both
ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.
1 1 0 0 0 1 0 1
Start Character bits Stop
bit bits
(1 bit) (at least 1 bit)
A character can be detected by the receiver from the knowledge of 4 rules;

- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected
by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last character , a Stop Bit is detected when
the line returns to the 1-state for at least 1 bit time
The receiver knows in advance the transfer rate of the
bits and the number of information bits to expect
UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER
(UART)
A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers
Control Transmitter Transmitter

clock
register control
Internal Bus
and clock
Chip select
CS
Register select Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register
Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether
to generate and check parity, and no. of stop bits

Input-Output Organization 16 Modes of Transfer
MODES OF TRANSFER - PROGRAM-CONTROLLED I/O -

3 different Data Transfer Modes between the central
computer(CPU or Memory) and peripherals; Program-Controlled I/O
Interrupt-Initiated I/O
Direct Memory Access (DMA)
Program-Controlled I/O(Input Dev to CPU)
Data bus Interface I/O bus
Address bus Data register
Data valid I/O
CPU I/O read device
I/O write Status Data accepted
register F
Read status register

Check flag bit
=0 Polling or Status Checking

flag
=1 • Busy waiting in Loop if No Data (F=0)
• Continuous CPU involvement
Read data register
Transfer data to memory • CPU slowed down to I/O speed
• Simple
no
• Least hardware
Operation
complete?
yes
Continue with
program

• When the I/O interface finds that the device is ready for data
transfer it generates an Interrupt Request and sends it to the
computer.
• When the CPU receives such an signal, it temporarily stops

the execution of the program and branches to a service
program (ISR) to process the I/O transfer and after
completing it returns back to task, what it was originally
performing.


Input-Output Organization 19 Priority Interrupt
PRIORITY INTERRUPT
Priority
- Determines which interrupt is to be served first
when two or more requests are made simultaneously
- Also determines which interrupts are permitted to
interrupt the computer while another is being serviced
- Higher priority interrupts can make requests while
servicing a lower priority interrupt
Priority Interrupt by Software(Polling)

- Priority is established by the order of polling the devices(interrupt sources)
- Flexible since it is established by software
- Low cost since it needs a very little hardware
- Very slow
Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts
all the interrupt requests to determine the highest priority request
- Fast since identification of the highest priority
interrupt request is identified by the hardware
- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine
HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

Processor data bus
VAD 1 VAD 2 VAD 3 * Serial hardware priority function
Device 1 Device 2 Device 3 * Interrupt Request Line
To next
PI PO PI PO PI PO
device
- Single common line
* Interrupt Acknowledge Line
- Daisy-Chain
Interrupt request INT
CPU
Interrupt acknowledge
INTACK
Interrupt Request from any device(>=1)

-> CPU responds by INTACK <- 1
-> Any device receives signal(INTACK) 1 at PI puts the VAD on the bus
Among interrupt requesting devices the only device which is physically closest
to CPU gets INTACK=1, and it blocks INTACK to propagate to the next device
One stage of the daisy chain priority arrangement
Priority in VAD
PI Enable
Vector address
Interrupt Priority out PI RF PO Enable
RF PO 0 0 0 0
request S Q
from device 0 1 0 0
R 1 0 1 0
1 1 1 1
Delay
Interrupt request to CPU

PARALLEL PRIORITY INTERRUPT

Interrupt register Bus
Buffer
Disk 0 I0 y
Printer 1 I1 x
Priority 0
Reader 2 I 2 encoder
0 VAD
Keyboard 3 0 to CPU
I3
0
0
0 IEN IST
0
Mask
register 1 Enable
2
Interrupt
to CPU
3
INTACK
from CPU
IEN: Set or Clear by instructions ION or IOF
IST: Represents an unmasked interrupt has occurred. INTACK enables
tristate Bus Buffer to load VAD generated by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from
different Interrupt Source - different priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction
INTERRUPT PRIORITY ENCODER
Determines the highest priority interrupt when

more than one interrupts take place
Priority Encoder Truth table
Inputs Outputs
I0 I1 I2 I3 x y IST Boolean functions
1 d d d 0 0 1
0 1 d d 0 1 1
0 0 1 d 1 0 1 x = I 0' I 1'
0 0 0 1 1 1 1 y = I 0' I 1 + I 0’ I 2’
0 0 0 0 d d 0 (IST) = I0 + I1 + I2 + I3

INTERRUPT CYCLE
At the end of each Instruction cycle

- CPU checks IEN and IST
- If IEN  IST = 1, CPU -> Interrupt Cycle
SP SP - 1 Decrement stack pointer

M[SP]  PC Push PC into stack
INTACK  1 Enable interrupt acknowledge
PC  VAD Transfer vector address to PC
IEN  0 Disable further interrupts
Go To Fetch to execute the first instruction
in the interrupt service routine

INTERRUPT SERVICE ROUTINE

address Memory I/O service programs
7
0 JMP DISK DISK Program to service
1 JMP PTR magnetic disk
VAD=00000011 3
2 JMP RDR PTR Program to service
3 JMP KBD line printer
8
1 Main program RDR
KBD Program to service
749 current instr.
interrupt 750 character reader
4
KBD Program to service
Stack
11 keyboard
5
2 255
256 Disk 256
750 interrupt
6 9 10
Initial and Final Operations
Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt system
Initial Sequence Final Sequence

[1] Clear lower level Mask reg. bits [1] IEN <- 0
[2] IST <- 0 [2] Restore CPU registers
[3] Save contents of CPU registers [3] Clear the bit in the Interrupt Reg
[4] IEN <- 1 [4] Set lower level Mask reg. bits
[5] Go to Interrupt Service Routine [5] Restore return address, IEN <- 1
Input-Output Organization 25 Direct Memory Access
DIRECT MEMORY ACCESS

* Block of data transfer from high speed devices, Drum, Disk, Tape
* DMA controller - Interface which allows I/O transfer directly between
Memory and Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory
address and the block size(number of words)
CPU bus signals for DMA transfer

ABUS Address bus High-impedence
Bus request BR DBUS Data bus (disabled)
CPU when BG is
Bus granted BG RD Read
WR Write enabled
Block diagram of DMA controller

Address bus
Data bus Data bus Address bus

buffers buffers
Internal Bus
DMA select DS Address register

Register select RS
Read RD Word count register
Write WR Control
logic
Bus request BR Control register
Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device

DMA I/O OPERATION

Starting an I/O
- CPU executes instruction to
Load Memory Address Register
Load Word Counter
Load Function(Read or Write) to be performed
Issue a GO command
Upon receiving a GO Command DMA performs I/O

operation as follows independently from CPU
Input
[1] Input Device <- R (Read control signal)
[2] Buffer(DMA Controller) <- Input Byte; and
assembles the byte into a word until word is full
[4] M <- memory address, W(Write control signal)
[5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1
[6] If WC = 0, then Interrupt to acknowledge done, else go to [1]
Output
[1] M <- M Address, R
M Address R <- M Address R + 1, WC <- WC - 1
[2] Disassemble the word
[3] Buffer <- One byte; Output Device <- W, for all disassembled bytes
[4] If WC = 0, then Interrupt to acknowledge done, else go to [1]
DMA TRANSFER
Interrupt
Random-access
BG
CPU memory unit (RAM)
BR
RD WR Addr Data RD WR Addr Data
Read control
Write control
Data bus
Address bus
Address
select
RD WR Addr Data
DS DMA ack.
RS DMA I/O
Controller Peripheral
BR device
BG DMA request
Interrupt

DMA Registers
• Address Register – start address of memory (1000)
• Word Count Register (10 then 9 …)
• Control Register (Read or Write operation)
1000
1010 (10 words)
• Once entire data is transferred then DMA controller

generates Interrupt to CPU so that CPU can take the
control of Bus by making BG = 0

DMA
• Burst transfer mode – all the words of the block is
transferred in one burst.
• Cycle stealing mode – DMA controller transfer each
word by stealing a cycle
from CPU that is DMA
controller always use
BR -> BG -> Interrupt
signal for
transferring each word.

CYCLE STEALING
While DMA I/O takes place, CPU is also executing instructions
DMA Controller and CPU both access Memory -> Memory Access Conflict
Memory Bus Controller
- Coordinating the activities of all devices requesting memory access

- Priority System
Memory accesses by CPU and DMA Controller are interwoven,

with the top priority given to DMA Controller
-> Cycle Stealing
Cycle Steal
- CPU is usually much faster than I/O(DMA), thus

CPU uses the most of the memory cycles
- DMA Controller steals the memory cycles from CPU
- For those stolen cycles, CPU remains idle
- For those slow CPU, DMA Controller may steal most of the memory
cycles which may cause CPU remain idle long time

Input-Output Organization 31 Input/Output Processor
INPUT/OUTPUT PROCESSOR - CHANNEL -

Channel
- Processor with direct memory access capability

that communicates with I/O devices
- Channel accesses memory by cycle stealing
- Channel can execute a Channel Program
- Stored in the main memory
- Consists of Channel Command Word(CCW)
- Each CCW specifies the parameters needed
by the channel to control the I/O devices and
perform data transfer operations
- CPU initiates the channel by executing an
channel I/O class instruction and once initiated,
channel operates independently of the CPU
Central
processing
unit (CPU)
Memory Bus
Peripheral devices
Memory
unit PD PD PD PD
Input-output
processor
(IOP) I/O bus

Input-Output Organization 32 Input/Output Processor
CHANNEL / CPU COMMUNICATION
CPU operations IOP operations

Send instruction
to test IOP.path
Transfer status word
to memory
If status OK, then send
start I/O instruction
to IOP. Access memory
for IOP program
CPU continues with

another program Conduct I/O transfers
using DMA;
Prepare status report.
I/O transfer completed;

Interrupt CPU
Request IOP status
Transfer status word

Check status word to memory location
for correct transfer.
Continue

Serial Communication
Data communication processor
Modem
Modes Of Transmission (Data Transfer Modes)

– Simplex
– Full Duplex
– Half Duplex
Protocols:
Character-Oriented Protocol
Bit-Oriented Protocol
Data Communication Processor:
• A data communication processor is an I/O processor that distributes and
collects data from numerous remote terminals connected through
communication lines to the computer.
• It is a specialized I/O processor designed to communicate with data
communication networks.
• The data communication processor communicates with each terminal
through a single pair of wire.
• It also communicates with CPU and memory in the same manner as any
I/O processor does.

Modem:
• Modem stands for Modulator and Demodulator.
• It is a device that modulates signals to encode
digital information for transmission and
demodulates signals to decode the transmitted
information.
• It is necessary for communication between digital
devices and Analog devices.
• It converts the digital signal to Analog and vice
versa to communicate between devices.
• It encodes the signal and decodes at the other
end and vice versa between the devices.

Modes Of Transmission:
Data can be transmitted between 2 points by three different
modes:
• Simplex:
A simplex line carries information in one direction only. In this
mode receiver cannot communicate with the sender to indicate
the occurrence of errors that means only sender can send data but
receiver cannot. For example: Radio and Television
Broadcasting.

Modes Of Transmission
Half Duplex:
• In half duplex mode, system is capable of transmitting data in
both directions but data can be transmitted in one direction
only at a time. A pair of wires is needed for this mode. For
example: Walkie - Talkie.

Modes Of Transmission
Full Duplex:
• In this mode data can be send and received in both directions
simultaneously. In this four wire link is used. For
example: Video Calling, Audio calling etc.

Protocols
• The communication lines, modems and other devices used in
any transmission are collectively called a Data Link. The
orderly transmission of data in a data link can be accomplished
by a protocol.
• A Protocol is a set of rules that are followed by
interconnecting devices to ensure that all data is passed
correctly without any error.
There are two types of protocols:

– Character Oriented Protocol
– Bit Oriented Protocol

Character Oriented Protocol

• It is based on the binary code of character set. The code is
mostly used in ASCII. It includes upper case and lower case
letters, numerals and variety of special symbols. The characters
that control the transmission is called communication control
characters.
• Point-to-Point Protocol (PPP) is an example of byte-oriented
protocol.
SYN SYN SOH HEADER STX TEXT ETX CRC

Character-oriented Protocol:

Typical Transmission from a Terminal to Processor

Bit Oriented Protocol

• It does not use characters in its control field and is independent
of any code. It allows the transmission of serial bit stream of
any length without the implication of character boundaries.
• Bit-oriented protocols are much less overhead-intensive, as
compared to byte-oriented protocols, also known as character-
oriented protocols.
• Bit-oriented protocols are usually full-duplex (FDX) and
operate over dedicated, four-wire circuits.

Bit Oriented Protocol

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Input-Output Organization 1

• Asynchronous Data Transfer

• Direct Memory Access

Computer Organization Computer Architectures Lab

Input Devices Output Devices

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– Data Transfer Rate

– Data representations may differ

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I/O BUS AND INTERFACE MODULES

Interface Interface Interface Interface

Each peripheral has an interface module associated with it

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I/O BUS AND MEMORY BUS

•MEMORY BUS is for information transfers between CPU and the

* I/O BUS is for information transfers between CPU

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CS RS1 RS0 Register selected

ASYNCHRONOUS DATA TRANSFER

Asynchronous Data Transfer

Two Asynchronous Data Transfer Methods

Source-Initiated Strobe Destination-Initiated Strobe

Block Diagram Block Diagram

Timing Diagram Timing Diagram

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The source unit that initiates the transfer has

The destination unit that initiates the transfer

To solve this problem, the HANDSHAKE method

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SOURCE-INITIATED TRANSFER USING HANDSHAKE

Sequence of Events Source unit Destination unit

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DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Timing Diagram Ready for data

Sequence of Events Source unit Destination unit

Accept data from bus.

* Handshaking provides a high degree of flexibility and reliability because the

Asynchronous Serial Transmission

• In parallel data transmission, n bit in the message must be

• In Asynchronous serial transfer, each bit of message is sent a

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Asynchronous Serial Transmission

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ASYNCHRONOUS SERIAL TRANSFER

A character can be detected by the receiver from the knowledge of 4 rules;

Control Transmitter Transmitter

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MODES OF TRANSFER - PROGRAM-CONTROLLED I/O -

Read status register

=0 Polling or Status Checking

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• When the CPU receives such an signal, it temporarily stops

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Priority Interrupt by Software(Polling)

Priority Interrupt by Hardware

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

Interrupt Request from any device(>=1)

Interrupt request to CPU