SUBJECT: COMPUTER ORGANISATION (18CS34)

QUESTION BANK

MODULE 1
(Basic Structure of Computer AND Machine Instructions & Programs)

Questions Year
1 With a neat diagram explain basic functional units of computer.
With a neat diagram explain basic operational concepts of computer. (OR)
Jan19(17s)
Explain the concept of communication between memory and processor with the
2 Jan19,17
respective registers. (*Also show how to add A + B to form C with the help of same diagram – June19,17,18
June19) (OR) Define the functions of following processor registers: MAR, MDR, IP & IR.
3 Explain Bus structure with diagram. Discuss about memory mapped I/O. Jan17
What is performance measurement? Discuss the basic performance equation. (Also June19
4
explain the methods to improve the performance of the computer) Jan17,18,19
June17
5 Write a note on: (a) Byte addressability (b) Big-Endian and Little-Endian assignment. Jan17, 18
With a memory layout starting at address ‘i’ represent how ‘ABCD’ data is stored in big
6 Jan19
endian and little endian assignment scheme in a system of word length 16 bits.
Jan19(17s),17
7 What is an addressing mode? Explain different types of addressing mode with ex. June19,17,18
8 Explain the basic instruction types with example. Jan19(17s)
9 What is subroutine? How to pass parameters to subroutine? Illustrate with an ex. June18
Jan19(17s),18
10 Explain logical and arithmetic shift and rotate instructions, with example. June19, 17
Compute with initial carry bit as 1 after performing following shift or rotate operations by 2
11 times. (a) SHR R1,2 (b) SAR R1, 2 [Arithmetic shift] Jan19
(c) ROR R2,2 (d) RCR R2, 2 [Rotate right with carry]
12 Write an assembly program that reads a line of character and displays it. Jan19(17s)
13 What are assembler directives? Point out and explain various directives with ex. Jan19(17s)
14 What is stack and queue? Write the line of code to implement the same. June17
15 How to encode assemble instructions into 32-bit words? Explain with example. June18
What is the need of processor stack? Explain a commonly used layout for information in
16 Jan19
a subroutine stack frame.
17 With relevant ex, briefly explain about any 2 encoding types of machine instructions. Jan19
List the steps needed to execute the machine instruction Add LOCA, RO, in terms of
transfers between the processor and the memory along with some simple control
commands. Assume that the instruction itself is stored in the memory at location INSTR
and that this address is initially in register PC. The first 2 steps might be expressed as:
18  Transfer the contents of Register PC to register MAR. Jan18
 Issue a Rad command to the memory and then wait until it has transferred
the requested word into register MDR.
Remember to include the steps needed to update the contents of PC from INSTR to
INSTR+1 so that the next instruction can be fetched.
Consider a computer that has a byte addressable memory organised in 32 bit words
according to the big endian scheme. A program reads ASCII characters entered at a
19 keyboard and store them in successive byte location starting at location 1000. Show the Jan18
contents of the contents of the 2 memory words at locations 1000 and 1004 after the
name “Johnson” has been entered. (ASCII codes J=AH, o=6FH, h=68H, n=6EH, S=73H)

18CS34 - COMPUTER ORGANISATION | QUESTION BANK

Questions Year
1 Explain the concept of accessing of input output devices in detail.
2 What is an interrupt? With an ex, illustrate the concept of interrupt. Jan17,19(17s)
Demonstrate the different approaches of handling interrupts for multiple devices. June18,19(17s)
3 (*Interrupt nesting/priority structure and Daisy chain method–June18)(*simultaneous Interrupt June17, Jan19
request (Jan18,19), Vectored interrupts (Jan18) Priority Interrupts (June17)
4 Write short notes on: Daisy chain, Subroutine, Interrupt hardware, Exception.(4m each) June19
June19, 17
5 With a neat diagram, explain the concept of DMA. Jan17
June18,19(17s)
6 Define BUS arbitration. With a neat diagram, explain different bus arbitration mechanism. June19,17
Jan18
June18,17
7 Explain connection between Processor to Keyword & Processor to Printer with diagrams. Jan19
With the help of neat timing diagram, briefly discuss the main phases of SCSI bus
8 June18
involved in its operation.
9 Explain PCI bus. Jan17
Explain the tree structure of USB with split bus operation. (including operation-USB-Jan19) Jan17,19(17s)
10
(Explain the following w.r.t USB: USB Architecture and USB protocols – June17) June17, Jan18
With a neat diagram, explain about how data is read in asynchronous bus scheme.
11 (OR) With neat timing diagram illustrate the asynchronous bus data transfer during an Jan19,18
input operation. Use Handshake method.
Three devices A, B and C are connected to the bus of a computer. I/O transfers for all
three devices use interrupt control. Interrupt nesting for devices A and B is not allowed,
but interrupt requests from C may be accepted while either A or B is being services.
12 Suggest different ways in which this can be accomplished in each of the following cases: Jan18
(i) The computer has one interrupt request line.
(ii) Two interrupt request line, INTR1 and INTR2 are available with INTR1 having higher
priority. Specify when and how interrupts are enabled and disabled in each case.

18CS34 - COMPUTER ORGANISATION | QUESTION BANK

Questions Year
1 Define: Memory Latency and Memory bandwidth. (2marks) June17
2 Explain synchronous DRAMS with block diagram. Jan19(17s)
With a diagram, explain the internal organisation of 2M X 8 asynchronous DRAM June18, Jan17
3
chip. June 17
4 With diagram, describe the internal organisation of a 128 X 8 memory chip. June19
With a neat diagram, explain the design of 2M X 32 memory module using 1M X 8
5 Jan19
memory chips.
6 Draw and explain the working of 16 Mega Bit DRAM chip configured as 2M X 8. Jan18
7 Describe organisation of a 2M X 32 memory using 512K X 8 memory chips. Jan18
With diagram of basic SRAM (Static RAM) and DRAM (Asynchronous DRAM) chip
8 June19
(cell), explain the read and write operations on each of them.
9 Define ROM. Explain various types of ROMs. Jan19(17s)
10 Write a short note on Flash memories (4marks) June17
Jan17,19(17s)
11 Explain ‘Hit Rate and Miss Penalty’.
June17
12 Define cache memory, explain various types of it with neat block diagram. Jan19(17s)
Define the following with respect to cache memory:
13 Jan18
■ Valid bit ■ Dirty data ■ Stale data ■Flush the cache
June18, 19
14 Describe any 2 mapping functions in cache. (with diagram)
Jan17
15 Explain Associative mapping technique and set associative mapping technique. June17
Explain in detail the working of set associative mapped cache with 2 blocks per set
16 Jan18
with relevant diagram.
In a given system
(i) hit rate (n) = 0.5
17 (ii) miss penalty (M) = 100 ns June19
(iii) Time to access cache memory (c) = 100 ns.
Calculate the average access time (tavg) experienced by the processor.
Calculate the average access time experienced by processor if miss penalty is 17
18 Jan19 (4m)
clock cycles and Miss rate is 10% and cache access time is 1 clock cycle.
Consider a cache consisting of 256 blocks of 16 words each, for a total of 4096
words and assume main memory is addressable by 16 bit address and it consists
19 Jan19 (9m)
of 4K blocks. How many bits are there in each of Tag, block/set and word fields for
different mapping techniques?
A block-set associative cache consists of a total of 64 blocks divided into 4 blocks
sets. The main memory contains 4096 blocks, each consisting of 128 words.
20 Jan18
(i) How many bits are there in a main memory address?
(ii) How many bits are there in each of the TAG, SET and WORD fields?

18CS34 - COMPUTER ORGANISATION | QUESTION BANK

Questions Year
Jan17,19(17s)
1 Draw 4-bit carry look ahead adder and explain (its operation) June18,17
2 Explain the generation and propagation functions used in Carry look ahead adder. June19
3 Design 16 bit carry look ahead adder using 4-bit adder. Unite the expression for Ci+1. Jan18
Design and explain the working of 16 bit carry look ahead adder built from 8 bit carry look
4 ahead adder. Compare its performance with 16 bit ripple carry adder built from 8 bit ripple Jan19
carry adder.
Explain the concept of carry save addition for the multiplication operation, M (X) Q = P for
5 June17
4- bit operands with diagram and suitable example.
6 Design a logic circuit to perform addition/subtraction of ‘n’ bit number X and Y Jan17,18
Perform the operations on 5-bit signed numbers using 2’s complement system. Also
indicate whether overflow has occurred.
June18, 17
7  (i) (-10)+(-13) (ii) (-10) – (-13) (iii) (-2) + (-9) Jan18
 (ii) (-9) + (-7) (ii) (+7) – (-8)
 (iii) 5+10 (iii) -14 + 11 (iii) -5 + 7 (iv) -10 + -13
8 With an example, explain the booths algorithm to multiply 2 signed operands (write steps) Jan18,June19
9 Perform multiplication for -13 and +09 using booth’s algorithm. (explain booth’s process) Jan17,19(17s)
Multiply the following signed 2’s complement numbers using Booth’s algorithm
10 June17
multiplicand = (010111)2 , multiplier = (110110)2
Multiply each of the following pairs of signed 2’s complement number using the Booths
algorithm. (A=Multiplicand and B=Multiplier)
1. A=010111 and B=110110
11 Jan18
2. A=110011 and B=101100
3. A=110101 and B=011011
4. A=001111 and B=001111
12 Perform multiplication of 13 and -6 using Booth algorithm and Bit-pair recording method. June18,19
13 Explain Bit Pair Recording / Fast multiplication with an example. June19
 Calculate the product of -2 and +14 using bit pair recording multiplier method.
14 Jan19
 Why is bit pair method better than booths algorithm?
15 Write steps of restoring division algorithm. Apply restoring division algorithm on 1000/10. June19
16 Perform restoring division for 8÷3 by showing all the steps. June18
Perform division operation on the following unsigned numbers using restoring method.
17 June17
Dividend = (10101)2 Divisor = (00100)2
Perform the non-restoring division for the given binary numbers where dividend is 1011
18 Jan19
and divisor is 0101 with all cycles.
19 Explain with neat figure the circuit arrangement for binary division. Jan19(17s),17

18CS34 - COMPUTER ORGANISATION | QUESTION BANK

Questions Year
1 Describe Multiple Bus Organisation with neat block diagram. (also its advantages) June 19, 18, 17
2 Explain 3-bus organisation with a neat block diagram. Jan19 (17s)
Write down the control sequence for the execution of the instruction Add (R3), R1.
June 19, 18
3 (in execution of a complete instruction)
Jan19(17s)Jan17
[What are the actions required to execute a complete instruction Add (R3), R1]
Jan19 (4marks)
4 Write then control sequence for instruction. Add R4, R5, R6 for 3 bus organisation.
June 17
5 Write the control sequence for an unconditional branch instruction. June 18
6 Explain Hard wired Control unit organisation in a processing unit. (with diagram) Jan19(15 & 17s)
What do you mean by micro-instruction? Design Basic Organisation of a micro
7 June 19
programmed control unit with diagram.
Explain with neat diagram, micro programmed control method for design of control
8 June 17
unit and write the micro-routine for the instruction Branch < 0.
Discuss with neat diagram, single bus organisation of the data path inside a Jan18
9*
processor. Jan17
Write and discuss about micro routine for complete execution of instruction Add
10* Jan19
(R1), R2 in single bus organisation
Write the sequence of control steps required for single bus structure for each of the
following instructions.
11* (i) Add the contents of memory location NUM to register R1. Jan18
(ii) Add the contents of memory location whose address is at memory location
NUM to register R1.

(Note: Pipelining is added newly in 18 Syllabus hence no questions from previous papers)

18CS34 - COMPUTER ORGANISATION | QUESTION BANK