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    Testability of Vlsi: BITS Pilani

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    KrunalKapadiya1
    The document describes a course on testability of VLSI systems. It covers topics like synthesis for test, fault modeling, logic simulation, fault simulation, built-in self-test, boundary scan testing, IDDQ testing, ATPG algorithms, JTAG, BIST, memory testing and system-on-chip design. The evaluation includes a mid-semester test, assignments and a comprehensive exam. The course aims to teach fundamentals of design for testability and issues in testing VLSI chips.

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    © All Rights Reserved
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    Testability of Vlsi: BITS Pilani

    Uploaded by

    KrunalKapadiya1
    149 views31 pages
    The document describes a course on testability of VLSI systems. It covers topics like synthesis for test, fault modeling, logic simulation, fault simulation, built-in self-test, boundary scan testing, IDDQ testing, ATPG algorithms, JTAG, BIST, memory testing and system-on-chip design. The evaluation includes a mid-semester test, assignments and a comprehensive exam. The course aims to teach fundamentals of design for testability and issues in testing VLSI chips.

    Original Title

    TVLSI_ESZG532_1_1627139431633

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    The document describes a course on testability of VLSI systems. It covers topics like synthesis for test, fault modeling, logic simulation, fault simulation, built-in self-test, boundary scan testing, IDDQ testing, ATPG algorithms, JTAG, BIST, memory testing and system-on-chip design. The evaluation includes a mid-semester test, assignments and a comprehensive exam. The course aims to teach fundamentals of design for testability and issues in testing VLSI chips.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    149 views31 pages

    Testability of Vlsi: BITS Pilani

    Uploaded by

    KrunalKapadiya1
    The document describes a course on testability of VLSI systems. It covers topics like synthesis for test, fault modeling, logic simulation, fault simulation, built-in self-test, boundary scan testing, IDDQ testing, ATPG algorithms, JTAG, BIST, memory testing and system-on-chip design. The evaluation includes a mid-semester test, assignments and a comprehensive exam. The course aims to teach fundamentals of design for testability and issues in testing VLSI chips.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 31

    TESTABILITY OF VLSI

    MEL ZG531 / ES ZG532

    BITS Pilani
    Pilani|Dubai|Goa|Hyderabad

    1
    BITS Pilani
    Pilani|Dubai|Goa|Hyderabad

    Course Overview

    2
    Course Description

    • Synthesis for test


    • Stuck-at faults, Test Generation Algorithms
    • Logic simulation and Fault simulation
    • Built In Self Test (BIST)
    • Boundary scan (BSCAN) & IDDQ testing
    • Pseudo-random test techniques, other test methods

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    Scope and Objective of the
    course

    • The course deals with the fundamentals of DFT


    (Design for Testability )

    • The course also covers the design issues involved in


    making a VLSI chip testable both at the end of
    manufacturing and at the user level.

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    Prescribed & Reference
    Books
    T1. “Essentials of Electronic Testing, for Digital, Memory
    and Mixed-Signal VLSI Circuits”,
    Michael L. Bushnell and Vishwani D. Agrawal,
    – Kluwer Academic Publishers (2000).

    R1. “Digital Systems Testing & Testable Design ”,


    Miron Abromavicici , Melvi Breuer & Friedman

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    INTRODUCTION

    • Introduction to VLSI testing and DFT

    • Technology Issues

    • Failure patterns

    • Automated Test Equipment

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    FAULT MODELING & LOGIC
    SIMULATION

    • Stuck at faults

    • Propagation & detectability of faults

    • Check Point Theorem

    • Fault equivalence

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    BASIC FAULT SIMULATION &
    TESTABILITY MEASURES

    • Fault simulation – Primary Inputs , Primary Outputs ,


    fault sensitization.

    • ROTH’s Test Detect algorithm

    • SCOAP measures for circuit nodes and Observation


    measures for combinational circuits.

    • SCOAP measures for sequential circuits.

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    BASICS OF COMBINATIONAL
    ATPG

    • ATPG search space.

    • Fault propagation & detection

    • Fault cone and D-Frontier approach.

    • Algorithmic procedure for sensitization – propagation


    and detection of stuck-at faults.

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    ATPG ALGORITHMS

    • ROTH’s D algorithm
    • example

    • PODEM algorithm
    • example

    10

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    JTAG Boundary scan

    • TAP Controller

    • Boundary Scan

    11

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    IDDQ TESTS & BOUNDARY
    SCAN

    • IC configuration for Boundary Scan


    • Boundary Scan control features.
    • Boundary scan Test Cell.
    • TAP controller and states.
    • TEST instructions.
    • Basics of IDDQ Testing.

    12

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    MID-SEMESTER TEST

    Syllabus for Mid-Semester Test (Closed Book):

    13

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    SEQUENTIAL CIRCUIT TEST
    GENERATION

    • Time Frame expansion approach

    • Use of nine-valued Logic

    • Multi cycle test process with test vectors ; example

    14

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    DELAY TEST METHODOLOGY
    & SCAN BASED DFT

    • Path delay testing for timing critical paths.


    • ON & OFF PATH segregation.
    • Path delay sensitization
    • 5 valued logic usage.
    • Scan design rules.
    • SCAN sequence
    • Used of LSSD cells for delay testing.
    • DFT error fixes for digital circuits to enable SCAN based
    testing

    15

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    BIST – PATTERN GENERATION
    AND RESPONSE COMPACTION.

    • BIST architectures.
    • Pseudo Random Pattern Generation.
    • LFSR as pattern generator and signal analyzer.
    • LFSR theory.
    • Modular LFSR & characteristic polynomial.
    • Primitive Polynomial and Companion Matrix.
    • Response compaction – Polynomial division
    • MISR

    16

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    MEMORY TEST & BIST FOR
    MEMORY

    • Functional memory model

    • Types of faults

    • MARCH tests

    • Memory BIST

    17

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    Comprehensive Exam

    Syllabus for Comprehensive Exam (Open Book): All


    topics given in the Plan of Self Study

    18

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    Evaluation Scheme

    EC No. Evaluation Component & Duration Weightage


    Type of Examination
    EC-1 Mid-Semester Test
    (Closed Book)* 2 hrs 30%

    Assignment 20%

    EC-2 Comprehensive Exam


    (Open Book)* 3 Hours 50%
    Quiz

    19

    BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


    BITS Pilani
    Pilani|Dubai|Goa|Hyderabad

    INTRODUCTION

    20
    System On Chip (SoC)

    Clk & GLUE


    ANALOG GLUE LOGIC
    Rst LOGIC
    ROM
    RAM ➢ Digital Logic

    PLATFORM ➢ Memories
    DIGITAL IPs
    ➢ IOs
    DIGITAL
    IPs
    FLASH
    RAM ➢ Analog blocks
    ANALOG

    PADI
    IOSS TCU
    Design Structures

    • Combinational Logic
    • Sequential Logic
    • Inputs & Outputs (I/O)
    • Memories
    • Analog
    Combinational Logic

    A3 n1
    A2
    Y

    n2 n3
    A1
    A0
    Sequential Logic

    Step Q

    0 111

    1 011 CLK
    Q[0] Q[1] Q[2]

    Flop

    Flop

    Flop
    2 101 D D D
    3 010

    4 001

    5 100

    6 110

    7 111 (repeats)
    Memory
    ANALOG Block

    SYSTEM I/P SYSTEM O/P


    Filter DAC Analo
    g

    SYSTEM O/P SYSTEM I/P


    AD Analog
    C
    Inputs & Outputs
    Digital Basics

    • Combinational logic

    • Sequential logic
    Digital Basics

    • Logic gates
    – AND, OR , NOT, XOR..
    – NAND, NOR..

    • Logic gates build with transistors

    • Truth tables
    Digital Basics

    • Flip flops
    HDL - Verilog

    • Hardware description language


    • ASIC Design
    • RTL and Gate level
    • Module definition
    • Module instantiation

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