Mel ZG531 Course Handout

Birla Institute of Technology & Science, Pilani
Work Integrated Learning Programmes Division

Digital Learning Handout
Course Title TESTABILITY OF VLSI

Course No(s) ES ZG532 / MEL ZG531
Credit Units 5
Credit Model Theory
Content A uthor Venkat Totakura
Instructor Incharge Venkat Totakura
Course Description:
COURSE OBJECTIVES
CO1 Understand the basics of designing a testable chip to increase the yield
CO2 To understand differences between defects and faults related to chip design
CO3 To learn various fault models, design rules, test pattern generation for combinational
and sequential circuits
Text Book(s):
T1 Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI Circuits”, Michael
L. Bushnell and Vishwani D. Agrawal, –Kluwer Academic Publishers (2000).
Reference Book(s) & other resources:
R1 Digital Systems Testing & Testable Design ”, Miron Abromavicici , Melvi Breuer & Friedman
R2 VLSI Test Principles and Architectures: Design for Testability. Laung-Terng Wang, Cheng-Wen
Wu, Xiaoqing Wen. Elsevier, 14-Aug-2006
R3 Digital System Test and Testable Design: Using HDL Models and Architectures. Zainalabedin
Navabi.Springer Science & Business Media, 10-Dec-2010
COURSE OUTCOMES
LO1 Apply the concepts of chip testing to help design a better yield in IC design.
LO2 Analyze the problems associated with testing of integrated circuits at earlier design levels to
reduce the testing costs.
LO3 Identify the design for testability methods for combinational & sequential circuits
LO4 Apply appropriate fault verification techniques to minimize chip faults after fabrication
Experiential Learning Components:

Students will be given case studies to refer from various conferences and journals in the area of
testability and present.
Content Structure:
Contact Hour List of Topic Title Sub-Topics Reference

Introduction to VLSI testing and DFT T1-Chapter
Technology Issues Failure patterns 1, 2 & 3
Automated Test Equipment
1-2 Introduction
Stuck at faults. Propagation & T1-Chapter
detectability of faults Check Point 4
Fault Modeling and Theorem Fault equivalence.
3-4 Logic Simulation
Fault simulation – primary Inputs, T1-Chapter

Primary Outputs, fault sensitization. 5&6
ROTH’s Test Detect algorithm, SCOPA
measures for circuit
Basic Fault Simulation nodes and Observation measures for
5-6 and Testability combinational circuits. SCOPA
Measures measures for sequential circuits.
ATPG search space. T1-Chapter 7
Fault propagation & detection
Fault cone and D-Frontier

Basics of Combinational approach.
7-10 ATPG Algorithmic procedure for
sensitization – propagation
and detection of stuck-at
faults.
ROTH’s D algorithm ; example T1-Chapter 7
PODEM algorithm ; example
Other Algorithms.
11-14 ATPG Algorithms
Time Frame expansion approach T1-Chapter 8

Use of nine-valued Logic .
Sequential Circuit Test
15-18 Generation
Multi cycle test process with
test vectors ; example
Path delay testing for timing T1-Chapter 12
critical paths. & 14
ON & OFF PATH
segregation.
Path delay sensitization
5 valued logic usage. Scan design
Delay Test Methodology rules.
19-22 and Scan Based DFT SCAN sequence
Use of LSSD cells for delay
testing.
DFT error fixes for digital
circuits to enable SCAN
based testing
BIST architectures. Pseudo T1-Chapter 15
Random Pattern Generation.
BIST – Pattern LFSR as pattern generator and
23-26 Generation and Response signal analyzer.
Compaction
LFSR theory.
Modular LFSR &
characteristic polynomial.
Primitive Polynomial and
Companion Matrix.
Response compaction –
Polynomial division
MISR
BILBO structures.
Functional memory model Types T1-Chapter 9
of faults & 15
27-28 Memory Test and BIST MARCH tests
for Memory
Memory BIST
IDDQ testing T1-Chapter 13
IC configuration for & 16
Boundary Scan
Boundary Scan control
features.
IDDQ Tests and Boundary scan Test Cell. TAP
29-32 Boundary Scan controller and states.
TEST instructions.
Test Bus configuration
Basics of Boundary Scan
Description Language
Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
Evaluation Name Type Weight Duration Day, Date, Session,

Component Time
EC – 1* Quiz Online 10% 1 week August 16-30, 2021
Assignment/Lab Assignment Online 20 % 10 days October 16-30, 2021
EC - 2 Mid-Semester Test Open Book 30% 2 hours Friday, 24/09/2021
(AN)
2 PM – 4 PM
EC - 3 Comprehensive Exam Open Book 40% 2 hours Friday, 12/11/2021
(AN)
2 PM – 4 PM
EC1* (20% - 30%): Quiz (optional): 5-10 %, Lab Assignment/Assignment: 20% - 30%
Syllabus for Mid-Semester Test (Open Book): Topics in Contact Hours: 1 to 16
Syllabus for Comprehensive Exam (Open Book): All topics
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with
the latest announcements and deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on
the Elearn portal.
Evaluation Guidelines:
EC-1 consists of either two Assignments or three Quizzes. Students will attempt them through
the course pages on the Elearn portal. Announcements will be made on the portal, in a timely
manner.
For Closed Book tests: No books or reference material of any kind will be permitted.
For Open Book exams: Use of books and any printed / written reference material (filed or
bound) is permitted. However, loose sheets of paper will not be allowed. Use of calculators is
permitted in all exams. Laptops/Mobiles of any kind are not allowed. Exchange of any material
is not allowed.
If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the
student should follow the procedure to apply for the Make-Up Test/Exam which will be made
available on the Elearn portal. The Make-Up Test/Exam will be conducted only at selected exam
centres on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self-study
schedule as given in the course handout, attend the online lectures, and take all the prescribed
evaluation components such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam
according to the evaluation scheme provided in the handout.

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Birla Institute of Technology & Science, Pilani

Work Integrated Learning Programmes Division

Course Title TESTABILITY OF VLSI

Reference Book(s) & other resources:

Experiential Learning Components:

Contact Hour List of Topic Title Sub-Topics Reference

Fault simulation – primary Inputs, T1-Chapter

Fault cone and D-Frontier

Time Frame expansion approach T1-Chapter 8

Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session

Evaluation Name Type Weight Duration Day, Date, Session,

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