COURSE INFORMATION SHEET

PROGRAMME: Electrical And Electronics Engineering DEGREE: BTECH

COURSE: Switching Theory and logic Design SEMESTER: II SEM CREDITS: 4
COURSE CODE: A40407 REGULATION: R16 COURSE TYPE: CORE
COURSE AREA/DOMAIN: : CORE CONTACT HOURS: 4 hours/Week.
CORRESPONDING LAB COURSE CODE (IF ANY): LAB COURSE NAME: N/A

Syllabus:
UNIT DETAILS HOURS
I Number System and Boolean Algebra And Switching Functions: Number Systems, Base Conversion 15
Methods, Complements of Numbers, Codes- Binary Codes, Binary Coded Decimal Code and its
Properties, Unit Distance Codes, Alpha Numeric Codes, Error Detecting and Correcting Codes.
Boolean Algebra: Basic Theorems and Properties, Switching Functions, Canonical and Standard Form,
Algebraic Simplification of Digital Logic Gates, Properties of XOR Gates, Universal Gates, Multilevel
NAND/NOR realizations.
II Minimization and Design of Combinational Circuits: Introduction, The Minimization with theorem, The 11
Karnaugh Map Method, Five and Six Variable Maps, Prime and Essential Implications, Don’t Care Map
Entries, Using the Maps for Simplifying, Tabular Method, Partially Specified Expressions, Multi-output
Minimization, Minimization and Combinational Design, Arithmetic Circuits, Comparator, Multiplexers,
Code Converters, Wired Logic, Tristate Bus System, Practical Aspects related to Combinational Logic
Design, Hazards and Hazard Free Relations.
III Sequential Machines Fundamentals: Introduction, Basic Architectural Distinctions between 10
Combinational and Sequential circuits, The Binary Cell, Fundamentals of Sequential Machine Operation,
The Flip-Flop, The D-Latch Flip-Flop, The “Clocked T” Flip-Flop, The “ Clocked J-K” Flip-Flop, Design of a
Clocked Flip-Flop, Conversion from one type of Flip-Flop to another, Timing and Triggering Consideration,
Clock Skew.
IV Sequential Circuit Design and Analysis: Introduction, State Diagram, Analysis of Synchronous Sequential 11
Circuits, Approaches to the Design of Synchronous Sequential Finite State Machines, Design Aspects,
State Reduction, Design Steps, Realization using Flip-Flops Counters - Design of Single mode Counter,
Ripple Counter, Ring Counter, Shift Register, Shift Register Sequences, Ring Counter Using Shift Register.
V Sequential Circuits: Finite state machine-capabilities and limitations, Mealy and Moore models- 8
minimization of completely specified and incompletely specified sequential machines, Partition
techniques and Merger chart methods-concept of minimal cover table.
Algorithmic State Machines: Salient features of the ASM chart-Simple examples-System design using data
path and control subsystems-control implementations-examples of Weighing machine and Binary
multiplier.
TOTAL HOURS 55
Tutorial Classes 10
Descriptive Tests 02
Classes for beyond syllabus 03
Remedial Classes/NPTL 04
Total Number of Classes 74

TEXT/REFERENCE BOOKS:
T/R BOOK TITLE/AUTHORS/PUBLICATION
T Switching and Finite Automata Theory- Zvi Kohavi & Niraj K. Jha, 3rd Edition, Cambridge.
T Digital Design- Morris Mano, PHI, 3rd Edition.
R Fundamentals of Logic Design – Charles H. Roth, Thomson Publications, 5th Edition, 2004
R Introduction to STLD –Fredriac J. Hill, Gerald R. Peterson
 COURSE OBJECTIVES:
1 To learn basic techniques for the design of digital circuits and fundamental concepts used in the design
of digital systems.
2 To design combinational logic circuits, sequential logic circuits.
3 To implement synchronous state machines using flip-flops.

COURSE OUTCOMES:
SNO DESCRIPTION PO’ MAPPING
1 Be able to manipulate numeric information in different forms, e.g. different bases, signed
4,5
integers, various codes such as ASCII, Gray, and BCD.
2 Be able to manipulate simple Boolean expressions using the theorems and postulates of
1,4,9
Boolean algebra and to minimize combinational functions
3 Be able to design and analyze small combinational circuits and to use standard combinational
8,2,3
functions/building blocks to build larger more complex circuits.
4 Be able to design and analyze small sequential circuits and devices and to use standard
12,6,7
sequential functions/building blocks to build larger more complex circuits

GAPS IN THE SYLLABUS - TO MEET INDUSTRY/PROFESSION REQUIREMENTS:

SNO DESCRIPTION PROPOSED
ACTIONS
1 Inhibit Circuits Student seminars
2 Hybrid logic Student seminars

TOPICS BEYOND SYLLABUS/ADVANCED TOPICS/DESIGN:

1 CPLD Design
2 Threshold Gates

WEB SOURCE REFERENCES:

1 www.ocw.mit.edu.in
2 www.emedia.ee.unsw.edu.au
3 www.nptel.edu.in Video lecturers of 1).Digital Circuits & SystemsProf. R.K.Ravichandran, IITM
4 www.ucberkely.edu.in
5 All 8 units PPTS are Available- Dept. Digital Library

DELIVERY/INSTRUCTIONALMETHODOLOGIES:
√CHALK & TALK √STUD. ASSIGNMENT ☐ WEB RESOURCES ☐ NPTEL
√LCD/SMART BOARDS ☐ STUD. SEMINARS ☐ ADD-ON COURSES √ PPT
ASSESSMENT METHODOLOGIES-DIRECT
√ ASSIGNMENTS √ STUD. SEMINARS √ TESTS/MODEL EXAMS √ UNIV. EXAMINATION
☐STUD. LAB PRACTICES ☐STUD. VIVA ☐ MINI/MAJOR PROJECTS ☐ CERTIFICATIONS
☐ ADD-ON COURSES ☐ OTHERS √ SPECIAL TEST
ASSESSMENT METHODOLOGIES-INDIRECT
√ASSESSMENT OF COURSE OUTCOMES (BY FEEDBACK, ONCE) √STUDENT FEEDBACK ON FACULTY (TWICE)
☐ ASSESSMENT OF MINI/MAJOR PROJECTS BY EXT. EXPERTS ☐ OTHERS

Prepared by Approved by
M BHOJARAJU

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

II Year B.Tech. EEE-II Sem
L T/P/D C
 4 -/-/- 4
(EC401ES )SWITCHING THEORY AND LOGIC DESIGN
UNIT -I:
Number System and Boolean Algebra And Switching Functions: Number Systems, Base Conversion
Methods, Complements of Numbers, Codes-Binary Codes, Binary Coded Decimal Code and its Properties, Unit
Distance Codes, Alpha Numeric Codes, Error Detecting and Correcting Codes.
Boolean Algebra: Basic Theorems and Properties, Switching Functions, Canonical and Standard Form,
Algebraic Simplification of Digital Logic Gates, Properties of XOR Gates, Universal Gates, Multilevel
NAND/NOR realizations.
UNIT -II:
Minimization and Design of Combinational Circuits: Introduction, The Minimization with theorem, The
Karnaugh Map Method, Five and Six Variable Maps, Prime and Essential Implications, Don’t Care Map
Entries,Using the Maps for Simplifying, Tabular Method, Partially Specified Expressions, Multi-output
Minimization, Minimization and Combinational Design, Arithmetic Circuits, Comparator, Multiplexers, Code
Converters, Wired Logic, Tristate Bus System, Practical Aspects related to Combinational Logic Design, Hazards
and Hazard Free Relations.
UNIT -III:
Sequential Machines Fundamentals: Introduction, Basic Architectural Distinctions between Combinational and
Sequential circuits, The Binary Cell, Fundamentals of Sequential Machine Operation, The Flip-Flop, The D-Latch
Flip-Flop, The “Clocked T” Flip-Flop, The “ Clocked J-K” Flip-Flop, Design of a Clocked Flip-Flop,
Conversion from one type of Flip-Flop to another, Timing and Triggering Consideration, Clock Skew.
UNIT -IV:
Sequential Circuit Design and Analysis: Introduction, State Diagram, Analysis of Synchronous
Sequential Circuits, Approaches to the Design of Synchronous Sequential Finite State Machines, Design
Aspects, State Reduction, Design Steps, Realization using Flip-Flops Counters - Design of Single mode
Counter, Ripple Counter, Ring Counter, Shift Register, Shift Register Sequences, Ring Counter Using Shift
Register.
UNIT -V:
Sequential Circuits:Finite state machine-capabilities and limitations, Mealy and Moore models-minimization of
completely specified and incompletely specified sequential machines, Partition techniques and Merger
chart methods-concept of minimal cover table.
Algorithmic State Machines: Salient features of the ASM chart-Simple examples-System design using
data path and control subsystems-control implementations-examples of Weighing machine and Binary multiplier.
TEXT BOOKS:
1. Switching and Finite Automata Theory-ZviKohavi&Niraj K. Jha, 3rd Edition, Cambridge.
2. Digital Design-Morris Mano, PHI, 3rd Edition.
REFERENCE BOOKS:
1. Introduction to Switching Theory and Logic Design –Fredriac J. Hill, Gerald R. Peterson, 3 rdEd,John Wiley &
Sons Inc.
2. Digital Fundamentals –A Systems Approach –Thomas L. Floyd, Pearson, 2013.
3. Digital Logic Design -Ye Brian and HoldsWorth, Elsevier
4. Fundamentals of Logic Design-Charles H. Roth, Cengage LEanring, 5th, Edition, 2004.

Faculty M. BHOJARAJU
Text Books (to be acquired by the Students)
Book-1 Switching & Finite Automata theory – Zvi Kohavi, TMH,2nd Edition.
Book-2 Digital Design – Morris Mano, PHI, 3rd Edition, 2006,PHI
Reference Books
Book-3 Introduction to STLD –Fredriac J. Hill, Gerald R. Peterson
Book-4 Fundamental of Logic Design- Charles H Roth
Chapters No of
Unit Topic
Book 1 Book 2 Book 3 Classes
Number systems & Boolean
I algebra and switching 1,2 1,2 1,2 15
functions
Minimization & design of
II Combinational Circuits 3,4 3,4 3,4 11

Sequential Machines
III 5,6 5,6 5,6 10
Fundamentals
Sequential Circui Design
IV 7 7 7 11
and analysis

Sequential Circuits and

V 8 8 8 8
Algorithmic State Machines

Contact classes for syllabus coverage 55

Tutorial Classes 10

Descriptive Tests 02

Classes for beyond syllabus 03

Remedial Classes/NPTL 04

Total Number of Classes 74

Model Lesson Plan - Switching Theory and Logic Design

(II Year B.Tech. II SEM)
No. of Cumulative Teaching aid
Sl. No. Name of the Topic Classes number of
required periods
UNIT-I Number systems & Boolean algebra & Switching functions

1 Number Systems 1 1 Chalk & Talk

2 Basic Conversion methods 2 3 Chalk & Talk

3 Compliments of numbers 2 5 Chalk & Talk

Codes- Binary Codes, BCD Codes and its Chalk & Talk
4 properties 1 6
5 Unit Distance Code, alphanumeric Codes 1 7 Chalk & Talk

6 Error Detecting and Correcting Codes 2 9 Chalk & Talk

Basic Theorems and Properties of Boolean Chalk & Talk

7 algebra 1 10

8 Switching functions 1 11 Chalk & Talk

9 Canonical and Standard Forms 1 12 Chalk & Talk

Algebraic Simplification of digital logic Chalk & Talk

10 gates 1 13

Properties of Ex-OR Gate, Universal Chalk & Talk

11 Gates 1 14

12 Multilevel NAND /NOR Realization 1 15 Chalk & Talk

Threshold Gates(Topics beyond Chalk & Talk

Syllabus) 1 16

UNIT-II Minimization & Design of Combinational Circuits

13 Minimization Theorem 1 17 Chalk & Talk

K-Map Method, 5 & 6 Variable 2 19 Chalk & Talk

14 maps,Prime and Essential Prime
implicants, Don’t care map Entries

Tabular Method, partially specified Chalk & Talk

15 expressions 2 21

Multi output minimization, minimization Chalk & Talk

16 and combinational design 1 22

17 Arithmetic Circuits 1 23 Chalk & Talk

18 Comparator, MUX, Code Converters 1 24 Chalk & Talk

19 Wired Logic. Tristate Bus system 1 25 Chalk & Talk

Practical Aspects related to combinational Chalk & Talk
20 1 26
logic design
21 Hazards and Hazard Free realization 1 27 Chalk & Talk
PLD Design(Topics beyond Syllabus) 2 29 Chalk & Talk
UNIT-III Sequential Machines and Fundamentals
Basic architectural distinctions between Chalk & Talk
22 combinational and sequential circuits, 1 30
Binary Cell
Fundamentals of Sequential machine Chalk & Talk
23 2 32
operation, Flip Flop
24 D Latch, Flip Flop, Clocked T Flip flop 2 34 VIDEOS
Clocked JK Flip flop, Design Of Clocked PPT
25 2 36
Flip Flops
26 Conversion Of Flip Flops, Timing and 2 38 Chalk & Talk
 Triggering Considerations
27 Clock Skew 1 39 PPT
UNIT-IV Sequential Circuit Design and analysis
State Diagram, Analysis of Synchronous PPT
28 1 40
Sequential circuits
Approaches to the design of synchronous PPT
29 sequential finite state machines, Design 2 42
aspects
State reduction design steps, Realization PPT
30 2 44
using Flip Flops
31 Shift Registers, Shift Registers sequences 2 46 PPT
32 Design of Single mode Counters, 2 48 Chalk & Talk
Ripple Counter, Ring Counter(using Shift
33 2 50
registers)
UNIT-V Sequential Circuits and ASM
34 FSM- Capabilities and limitations 1 51 OHP
35 Mealy and Moore Models 1 52 OHP
Minimization of Completely Specified Chalk & Talk
36 Machines(Partition Technique) 2 54

Minimization of Incompletely Specified Chalk & Talk

37 Machines using Merger Graph and Chart 2 56

38 Concept of Minimal cover table 2 58 Chalk & Talk

Total Classes(Lecture Classes(55) + Beyond The syllabus(03))
58
Tutorial Classes 10

Descriptive Tests 10
2

Remedial Classes/NPTEL 02
4

Total Number of Classes 04

74

74

Course objectives
To learn basic techniques for the design of digital circuits and fundamental concepts used in
1
the design of digital systems.
To design combinational logic circuits, sequential logic circuits.
2

3 To implement synchronous state machines using flip-flops.

Course outcomes
Course Bloom’s
Course Outcome Statement
Outcome Taxonomylevel

C221.1 Be able to manipulate numeric information in different forms, e.g. Comprehension

different bases, signed integers, various codes such as ASCII, Gray,
 and BCD.

Be able to manipulate simple Boolean expressions using the theorems Application

and postulates of Boolean algebra and to minimize combinational
C221.2
functions

Be able to design and analyze small combinational circuits and to use Application
standard combinational functions/building blocks to build larger
C221.3
more complex circuits.

Be able to design and analyze small sequential circuits and devices Application
and to use standard sequential functions/building blocks to build
C221.4
larger more complex circuits

CO-PO MAPPING
PO PO PO PO PO PO PO PO PO PO PO PO
1 2 3 4 5 6 7 8 9 10 11 12

C221.1 3 1 2
C221.2 2 1 3 1
C221.3 2 3
C221.4 3 1 2
AVG 2.5 1.5 2 2.5 2.3 2 1

C221.1: Be able to manipulate numeric information in different forms, e.g. different bases, signed
integers, various codes such as ASCII, Gray, and BCD. (Comprehension)

Justification
PO1 Understand the knowledge of Basic Number Systems and Boolean Algebra, (Level 3)
PO3 Able to Know students the basic methodology to perform analysis of different combinational
circuits. (Level 2)
PO2 Determines problems in minimizing the functions using different laws and theorems (Level 1)

C221.2 Be able to manipulate simple Boolean expressions using the theorems and postulates of
Boolean algebra and to minimize combinational functions (Application)

Justification
 PO5 Determines basic concepts of designing of combinational Circuits as well as Multi-Output
Minimization. (Level 3)
PO2 Able To make the students understand the difference between Combinational and Sequential
Circuits (Level 2)
PO3 To make the students Analyze and Design Sequential Circuits and apply them to different areas of
Communication Engineering. (Level 1)

C221.3. Be able to design and analyze small combinational circuits and to use standard
combinational functions/building blocks to build larger more complex circuits. (Application)

Justification
PO3 To make the Complete number systems and different codes and can manipulate the numerical
information in different forms (Level 3)
PO1 Solve simple Boolean expressions to minimize various combinational functions which are used in
real time operations. (Level 2)

C221.4.. Be able to design and analyze small sequential circuits and devices and to use standard
sequential functions/building blocks to build larger more complex circuits (Application)

Justification
PO4 Differentiate Combinational and Sequential Circuits with respect to Digital applications. (Level
3)
PO10 Able to Design and analyze the digital Circuits and Systems (Level 2)
 PROGRAM OUTCOMES
1. ENGINEERING KNOWLEDGE: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. PROBLEM ANALYSIS: Identify, formulate, research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences,
and engineering sciences.
3. DESIGN/DEVELOPMENT OF SOLUTIONS: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. CONDUCT INVESTIGATIONS OF COMPLEX PROBLEMS: Use research-based knowledge
and research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.
5. MODERN TOOL USAGE: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
6. THE ENGINEER AND SOCIETY: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
7. ENVIRONMENT AND SUSTAINABILITY: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
8. ETHICS: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. INDIVIDUAL AND TEAM WORK: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
10. COMMUNICATION: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, give and receive clear
instructions.
11. PROJECT MANAGEMENT AND FINANCE: Demonstrate knowledge and understanding of
the engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. LIFE-LONG LEARNING: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological change.

PSO1 An ability to endeavor the public and private sector, national level examination
and interviews successfully.
PSO2. An ability to design solutions for Electrical transmission and distribution
systems.
PSO3 An ability to undertake research in power electronics and power systems.
Programme Educational Objectives (PEOs)

PEO-1.Graduates shall have a solid foundation in Mathematics, Science, Electrical, and

Electronics and allied Engineering, capable of analyzing, design and development of

systems for Energy Generation, Transmission, Distribution, Operation and Control.

PEO-2.Graduates will have a successful career in industry/Technical profession and

undertake post-graduation studies, research and lifelong learning.

PEO-3. Graduates shall have professional and ethical attitudes, team work skills,

leadership qualities and good oral and written communication skills.

 IMPORTANT QUESTIONS

Unit-I

2-MARKS

1 What do u mean by abit?

2 How are negative numbers representd?

3 How are binary codes classified?

4 What do u mean by numeric codes?

5 Why are BCD codes required?

3-MARKS
1 What is Boolean Algebra?

2 What are Expandable Gates?

3 What are the Basic operations in Boolean algebra?

4 Write the Boolean Algebric Laws?

5 What are the advantage of SOP and POS forms of realization?

5-MARKS

a) Convert the following numbers (127.75)8 to base 10,base 16 and base 2

1
b) Perform the binary arithmetic operation on 12-4 using signed 2 s compliment.

Develop a Gray code (42)10 and (97)10 and convert the same to hexa sequence
2

Prove that NAND and NOR gates are universal gates.

3

a). Determine the canonical POS and SOP form of T(x, y, z)= x´(y’+z’).
b). State and prove demorgans theorem of Boolean Algebra.
4

Express the following functions in sum of minterms and product of maxterms.

 (i) F(A, B, C, D)= B’D+D’BD
(ii) F(x, y, z)= (xy +z) (xz+y)
5
(iii)

Unit-II

2-MARKS

1 What is a K-MAP?

2 What are the advantages and disadvantages of K-MAP?

3 What is astandard SOP form?

4 What is a true MINTERM?

5 What is a MAXTERM?

3-MARKS
What is an Essential prime implicant?
1

2 What is aredundant prime implicant?

3 What do u mean by looping?

4 What are prime implicants?

5 What are don’t cares?

5-MARKS

Use the tabulation procedure to generate set of prime implicants and to obtain all
minimal expression for the following function.
1
F(A, B, C, D)= ∑ (1, 5, 6, 12, 13, 14)+ ∑ d (2, 4).

Simply the following function

2 F(A,B, C, D)= ∑ (3, 7, 8, 12, 15)+ ∑ d (9, 14).

Design 2-bit comparator which compares the magnitude of two numbers X and Y
3 and generate three outputs

Design 32x1 MUX 8x1 MUX and 2 to 4 decorder.

4
Design a code converter that converts BCD code into Excess-3 Code

Unit-III
 2-MARKS

1 What is half-adder?

2 What is a half-subtractor?

3 What is aripple carry adder?

What is priority Encoder?

4
What is an Encoder?
5

3-MARKS

What are code converters?

1
2 What is Decoder?
Why is a Demultiplexer called a distributor?
3
What are applications of Multiplexers?
4
What is a Multiplexing?
5

5-MARKS
Write the differences between Combinational and Sequential Circuits
1

Write the characteristic table, excitation table for JK, SR, T and D flip-flops
2

3 Convert the given flip-flop to D flip-flop and T flip-flop.

Q(t)(present X(External
State) Inputs)

0 0 0 0

1 0 0 1

0 0 1 0

1 0 1 0

0 1 0 1

1 1 0 1

0 1 1 1
 1 1 1 1

Write the differences between Latch and a Flip Flop

4
Explain the term race around condition and how it is overcome by master slave flip
5 flop.

Unit-IV
2-MARKS

What do u mean by stable states?

1
What is an asynchronous latch?
2
What is adynamic triggering?
3
List the different types of Latches and Flip-Flops?
4
Which Flip-Flops are not widely available commercially?
5
3-MARKS

What is a Master slave Flip-Flop?

1
What is Register?
2
What is a Trigger?
3
What are Buffer registers?
4
What is meant by state of the counter?
5
5-MARKS

1 Find a modulo-6 gray code using k-Map & design the corresponding counter.

2 Explain the differences between synchronous and asynchronous counters

3 Design a 4-bit ring counter using right shift register

4 Design modulo -10 counter using JK Flip flop

Design a 4-bit ripple counter.

Unit-V
 2-MARKS

What is Sequential Machine?

1
What is the Melay Machine?
2
state ‘State equivalence theorem’?
3

4 What are Maximal compatibles?

5 What is a minimal cover table?

3-MARKS

1 What is an algorithm?

2 What is meant by the term ASM/

3 What is an ASM block?

How many MUXs are required for the control subsystems?
4
What is the advantage of using the MUXs for control?
5

5-MARKS

What are the conditions for the two machines are to be equivalent? For the
machine given below, and the equivalence partition and a corresponding reduced
machine in standard form:
PS NS,Z
X=0 X=1
A F,0 B,1
B G,0 A,1
1
C B,0 C,1
D C,0 B,1
E D,0 A,1
F E,1 F,1
G E,1 G,1.

2 Draw the merger graph and chart and obtain the set of maximal compatibles for the
incompletely specified machine given below
PS NS,Z
I1 I2 I3 I4
A _ _ C,1 E,1 B,1
B E,0 _,_ _,_ _,_
C F,0 F,1 _,_ _,_
D _,_ _,_ B,1 _,_
 E _,_ F,0 A,1 D,1
F C,0 _,_ B,0 C,1

Explain in detail the block diagram of ASM chart.

3
Compare Mealy and Moore models with block diagram.
4

Draw the ASM chart and state table for the Synchronous circuit having following
description “The circuit has control input X , Clock and output A and B. if X=1, on
every clock pulse the code BA changes from 00->01->10->11->00 and if X=0, the
5
circuit holds present state.”

ASSIGNMENT QUESTIONS

Unit-I
a). Convert the number(11110.1011)2 to base 10
1 b).Convert the number(1596.675)10 to base 16
c).Convert the number(235.0657)8 to base 2
Perform the binary arithmetic operation on (231) 10 –(54) 10 using signed 1’s
2 compliment.

Generate 15 bit hamming code for the given 11 bit message 10001110101 and
3 rewrite the entire message with hamming code

What are universal gates? Realise AND, OR NOT, XOR gates using universal
4 gates

Express the following functions in sum of minterms and product of maxterms.

(i) F(A, B, C, D)= B’D+D’BD
5
(ii) F(x, y, z)= (xy +z) (xz+y)

Unit-II
Simply the following function using K-map
1 F(A, B, C, D)=∑ (1, 3, 4, 5, 6 11, 13, 14, 15)

Reduce the following function using K map and implement it in AOI logic as well
2 as NAND logic

3 Simply the following using prime implicant chart method

 F(A, B, C, D,E)=∑(0, 4,8,12,16,20,24,28)+. ∑ d (1,5,7,23)

Design a 4 bit parallel adder/subtractor using full adder modules

4
Design 32x1 MUX 8x1 MUX and 2 to 4 decoder.
5

Unit-III
1 Convert SR to D and T Flip Flops
2 Design 2 bit asynchronous counter using JK Flip Flop
3 Explain in brief about Clock Skew
4 Explain the operation of clocked JK flip flop
Draw the timing diagrams

Unit-IV
1 Design Mod 10 Counter using JK flip Flops
2 Design a Universal Shift Register
3 Design any counter using T Flip flops(Mod 20)
4 Design Mod 14 synchronous counter using D FF
5. Draw the state diagram and state table for JK FF.
Unit-V
What are the conditions for the two machines are to be equivalent? For the
machine given below, and the equivalence partition and a corresponding reduced
machine in standard form: (Jan2010)
PS NS,Z
X=0 X=1
A E,0 D,1
1
B F,0 D,1
C E,0 B,0
D F,0 B,0
E C,0 F,1
F B,0 C,1
.
Draw the merger graph and obtain the set of maximal compatibles for the
incompletely specified machine given below
PS NS,Z
I1 I2 I3 I4
A _ _ C,1 E,1 B,1
2 B E,0 _,_ _,_ _,_
C F,0 F,1 _,_ _,_
D _,_ _,_ B,1 _,_
E _,_ F,0 A,1 D,1
F C,0 _,_ B,0 C,1
 Minimize the following state machine using merge table
PS NS,Z
X=0 X=1
A E,0 B,0
B F,0 A,0
3
C E,_ C,0
D F,1 D,0
E C,1 C,0
F D,_

Explain steps in designing the sequential circuit using ASM technique.

4
(a) Draw the ASM chart for the following state transition, start from the initial
state T1, then if xy=00 go to T2, if xy=01 go to T3, if xy=10 go to T1, other wise
go to T3.
5
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state.
 SWITCHING THEORY AND LOGIC DESIGN
UNIT -1

1. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.

A. A = 1, B = 1, C = 0

B. A = 0, B = 0, C = 0

C. A = 1, B = 1, C = 1

D. A = 1, B = 0, C = 1

2. If a 3-input NOR gate has eight input possibilities, how many of those possibilities will result in a HIGH
output?

A. 1 B. 2

C. 7 D. 8

3. If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is
HIGH, the gate is a(n):

A. AND B. NAND

C. NOR D. OR

4. The output of an OR gate with three inputs, A, B, and C, is LOW when ________.

A. A = 0, B = 0, C = 0

B. A = 0, B = 0, C = 1

C. A = 0, B = 1, C = 1

D. all of the above

5. Which of the following logical operations is represented by the + sign in Boolean algebra?

A. inversion B. AND

C. OR D. complementation

6. Output will be a LOW for any case when one or more inputs are zero for a(n):
 A. OR gate

B. NOT gate

C. AND gate

D. NOR gate

7. How many pins does the 4049 IC have?

A. 14 B. 16

C. 18 D. 20

8. Which of the following choices meets the minimum requirement needed to create specialized waveforms
that are used in digital control and sequencing circuits?

A. basic gates, a clock oscillator, and a repetitive waveform generator

B. basic gates, a clock oscillator, and a Johnson shift counter

C. basic gates, a clock oscillator, and a DeMorgan pulse generator

D. basic gates, a clock oscillator, a repetitive waveform generator, and a Johnson shift counter

9. TTL operates from a ________.

A. 9-volt supply

B. 3-volt supply

C. 12-volt supply

D. 5-volt supply

10. The output of a NOR gate is HIGH if ________.

A. all inputs are HIGH

B. any input is HIGH

C. any input is LOW

D. all inputs are LOW

11. The switching speed of CMOS is now ________.

 A. competitive with TTL

B. three times that of TTL

C. slower than TTL

D. twice that of TTL

12. The format used to present the logic output for the various combinations of logic inputs to a gate is called
a(n):

A. Boolean constant

B. Boolean variable

C. truth table

D. input logic function

13. The power dissipation, PD, of a logic gate is the product of the ________.

A. dc supply voltage and the peak current

B. dc supply voltage and the average supply current

C. ac supply voltage and the peak current

ac supply voltage and the average supply current

D.

14. If a 3-input AND gate has eight input possibilities, how many of those possibilities will result in a HIGH
output?

A. 1 B. 2

C. 7 D. 8

15. The Boolean expression for a 3-input AND gate is ________.

A. X = AB

B. X = ABC

C. X=A+B+C

D. X = AB + C

16. A CMOS IC operating from a 3-volt supply will consume ________.

 A. less power than a TTL IC

B. more power than a TTL IC

C. the same power as a TTL IC

D. no power at all

17. What does the small bubble on the output of the NAND gate logic symbol mean?

A. open collector output

B. tristate

C. The output is inverted.

none of the above

D.

18. The output of a NOT gate is HIGH when ________.

A. the input is LOW

B. the input is HIGH

C. power is applied to the gate's IC

D. power is removed from the gate's IC

19. If the input to a NOT gate is A and the output is X, then ________.

A. X=A

B.

C. X=0

D. none of the above

20. How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate to go
HIGH?
 A. any one of the inputs

B. any two of the inputs

C. any three of the inputs

D. all four inputs

21. If the output of a three-input AND gate must be a logic LOW, what must the condition of the inputs be?

A. All inputs must be LOW.

B. All inputs must be HIGH.

C. At least one input must be LOW.

D. At least one input must be HIGH.

22. Logically, the output of a NOR gate would have the same Boolean expression as a(n):

A. NAND gate immediately followed by an inverter

B. OR gate immediately followed by an inverter

C. AND gate immediately followed by an inverter

D. NOR gate immediately followed by an inverter

23. A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of
the input terminals, but the output indication does not change. What is wrong?

A. The dim indication on the logic probe indicates that the supply voltage is probably low.

B. The output of the gate appears to be open.

C. The dim indication is the result of a bad ground connection on the logic probe.

D. The gate is a tristate device.

24. What is the Boolean expression for a three-input AND gate?

A. X=A+B+C

B. X = A BC

C. A–B–C

D. A$B$C
25. Which of the following gates has the exact inverse output of the OR gate for all possible input
combinations?

A. NOR B. NOT

C. NAND D. AND

26. Write the Boolean expression for an inverter logic gate with input C and output Y.

A. Y=C

B. Y=

27. The output of an exclusive-OR gate is HIGH if ________.

A. all inputs are LOW

B. all inputs are HIGH

C. the inputs are unequal

D. none of the above

28. A clock signal with a period of 1 s is applied to the input of an enable gate. The output must contain six
pulses. How long must the enable pulse be active?

A. Enable must be active for 0 s.

B. Enable must be active for 3 s.

C. Enable must be active for 6 s.

D. Enable must be active for 12 s.

29. The AND function can be used to ________ and the OR function can be used to ________ .

A. enable, disable

B. disable, enable

C. enable or disable, enable or disable

D. detect, invert

30. A 2-input NOR gate is equivalent to a ________.

 A. negative-OR gate

B. negative-AND gate

C. negative-NAND gate

D. none of the above

31. If a 3-input OR gate has eight input possibilities, how many of those possibilities will result in a HIGH
output?

A. 1 B. 2

C. 7 D. 8

32. Fan-out is specified in terms of ________.

A. voltage

B. current

C. wattage

D. unit loads

33. How many input combinations would a truth table have for a six-input AND gate?

A. 32 B. 48

C. 64 D. 128

34. The NOR logic gate is the same as the operation of the ________ gate with an inverter connected to the
output.

A. OR

B. AND

C. NAND

D. none of the above

35. The logic expression for a NOR gate is ________.

 A.

B.

C.

D.

36. With regard to an AND gate, which statement is true?

A. An AND gate has two inputs and one output.

B. An AND gate has two or more inputs and two outputs.

C. If one input to a 2-input AND gate is HIGH, the output reflects the other input.

A 2-input AND gate has eight input possibilities.

D.

37. The basic logic gate whose output is the complement of the input is the:

A. OR gate

B. AND gate

C. inverter

D. comparator

38. When reading a Boolean expression, what does the word "NOT" indicate?

A. the same as

B. inversion

C. high

D. low

39. The output of an exclusive-NOR gate is HIGH if ________.

A. the inputs are equal

B. one input is HIGH, and the other input is LOW

C. the inputs are unequal

D. none of the above

40. Which of the following equations would accurately describe a four-input OR gate when A = 1, B = 1, C =
0, and D = 0?
 A. 1 + 1 + 0 + 0 = 01

B. 1+1+0+0=1

C. 1+1+0+0=0

D. 1 + 1 + 0 + 0 = 00

UNIT-2

1.The number of digits in octal system is

a.8
b.7
c.10
d. none

2..The number of digits in Hexadecimal system is

a.15
b.17
c.16
d. 8

3.The number of bits in a nibble is

a.16
b.5
c.4
d.8

4.The digit F in Hexadecimal system is equivalent to ------ in decimal system

a.16
b.15
c.17
d. 8

5.Which of the following binary numbers is equivalent to decimal 10

a.1000
b.1100
c.1010
d.1001

6.The number FF in Hexadecimal system is equivalent to ------ in decimal system

a.256
b.255
c.240
d.239

7.IC s are
a. analog
b. digital
c. both analog and digital
d. mostly analog

8.The rate of change of digital signals between High and Low Level is
a. very fast
b. fast
c. slow
d. very slow

9. Digital circuits mostly use

a. Diodes
b. Bipolar transistors
c. Diode and Bipolar transistors
d. Bipolar transistors and FETs

10.Logic pulser
a. generates short duration pulses
b. generate long duration pulses
c. generates long and short duration
d. none of above

11.What is the output state of an OR gate if the inputs are 0 and 1?

a.0
b.1
c.3
d.2

12.What is the output state of an AND gate if the inputs are 0 and 1?
a.0
b.1
c.3
d.2

13.A NOT gate has...

a. Two inputs and one output
b. One input and one output
c. One input and two outputs
d. none of above

14.An OR gate has...

a. Two inputs and one output
b. One input and one output
c. One input and two outputs
d. none of above

15.The output of a logic gate can be one of two _____?

a. Inputs
b. Gates
c.States
d. none
16.Logic states can only be ___ or 0.
a. 3
b. 2
c.1
d.0

17.The output of a ____ gate is only 1 when all of its inputs are 1
a. NOR
b. XOR
c. AND
d. NOT

18.A NAND gate is equivalent to an AND gate plus a .... gate put together.
a. NOR
b. NOT
c. XOR
d. none

19.Half adder circuit is ______?

a. Half of an AND gate
b. A circuit to add two bits together
c. Half of a NAND gate
d. none of above

20. Numbers are stored and transmitted inside a computer in

a. binary form
b. ASCII code form
c. decimal form
d. alphanumeric form

21.The decimal number 127 may be represented by

a. 1111 1111B
b. 1000 0000B
c. EEH
d. 0111 1111

22.. A byte corresponds to

a. 4 bits
b. 8 bits
c. 16 bits
d. 32 bits

23.A gigabyte represents

a.1 billion bytes
b. 1000 kilobytes
c. 230 bytes
d. 1024 bytes

24. A megabyte represents

a. 1 million bytes
b. 1000 kilobytes
c. 220 bytes
d. 1024 bytes
25.. A Kb corresponds to
a. 1024 bits
b. 1000 bytes
c.210 bytes
d. 210 bits

26.A parity bit is

a. used to indicate uppercase letters
b. used to detect errors
c. is the first bit in a byte
d. is the last bit in a byte

27. Which of these devices are two state.

a. lamp
b. punched card
c. magnetic tape
d. all the above

The output impedance of of a logic pulser is

a. low
b. high
c. may be low or high
d. none of above

28.The number of LED display indicators in logic probe are

a.1
b.2
c.1 or 2
d.4

29.In hexadecimal number system,A is equal to decimal number

a.10
b.11
c.17
d.18

30.Hexadecimal number F is equal to octal number

a.15
b.16
c.17
d.18

31.Hexadecimal number E is equal to binary number

a.1110
b.1101
c.1001
d.1111

32.Binary number 1101 is equal to octal number

a.15
b.16
c.17
d.14

33.Octal number 12 is equal to decimal number

a.8
b.11
c.9
d. none

34.Decimal number 10 is equal to binary number

a.1110
b.1000
c.1001
d.1010

35.Binary number 110011011001 is equal to decimal number

a.3289
b.2289
c.1289
d.289

36.1111+11111=
a.101111
b.101110
c.111111
d.011111

37.Binary multiplication 1*0=

a.1
b.0
c.10
d.11

38.110012 -100012=
a.10000
b.01000
c.00100
d.00001

39.10112*1012=
a.55
b.45
c.35
d.25

40.1110112*100012=
a.111101101
b.111101100
c.111110
d.1100110
 UNIT-3
41.4 bits is equal to
a. 1 nibble
b.1 byte
c. 2 byte
d. none of above

42. which is non-volatile memory

a. RAM
b. ROM
c. both
d. none

43. The contents of these chips are lost when the computer is switched off?
a. ROM chips
b. RAM chips
c. DRAM chips
d. none of above

44.What are responsible for storing permanent data and instructions.?

a. RAM chips
b. ROM chips
c. DRAM chips
d. none of above

45. Which parts of the computer perform arithmetic calculations?

a. ALU
b. Registers
c. Logic bus
d. none of above
46.How many bits of information can each memory cell in a computer chip hold?
a. 0 bits
b. 1 bit
c. 8 bits
d. 2 bits

47.What type of computer chips are said to be volatile?

a. RAM chips
b. ROM chips
c. DRAM
d. none of above

48.Which generation of computer uses more than one microprocessor?

a. Second generation
b. Fifth generation
c.Third generation
d .none of above

49.Which generation of computer developed using integrated circuits?

a. Second generation
b. Fifth generation
c. Third generation
d. none of above

50.Which generation of computer was developed from microchips?

a. Second generation
b. Third generation
c. Fourth generation
d. none of above

51.RAM can be expanded to a

a. increase word size
b. increase word number
c. increase word size or increase word number
d. none of above

52. Which memory is available in all technologies

a. PROM
b. EEPROM
c. ROM
d. EPROM

53. Which memory does not require programming equipment

a. PROM
b. EEPROM
c. ROM
d. EPROM

54. In CCD
a. small charge is deposited for logical 1
b. small charge is deposited for logical 0 or 1
c. small charge is deposited for logical 0 and large charge for logical 1
d. none of above

55. The internal structure of PLA is similar to

a. RAM
b. ROM
c. both RAM or ROM
d. neither RAM nor RAM

56.An output of combinational ckt depends on

a. present inputs
b. previous inputs
c. both present and previous
d .none of above

57.Which are combinational gates

a. NAND & NOR
b. NOT & AND
c. X-OR & X-NOR
d. none of above

58.. As access time is decreased, the cost of memory

a. remains the same
b. increases
c. decreases
d. may increase or decrease

59. Which is correct:

a. A.A=0
b. A+1=A
c. A+A=A'
d. A'.A'=0

60.A counter is a
a. Sequential ckt
b. Combinational ckt
c. both combinational and sequential ckt
d. none of above

61.The parity bit is

a. always 1
b. always 0
c.1 or 0
d.none of above

62.In 2 out of 5 code,decimal number 8 is

a.11000
b.10100
c.1100
d.1010

63.In number of information bits is 11,the number of parity

Bits in hamming code is
a.5
b.4
c.3
d.2

64.For a 4096*8 EPROM ,the number of address lines is

a.14
b.12
c.10
d.8

65. 23.6 10=……….2

a.11111.10011
b.10111.10011
c.00111.101
d.10111.1

66.BCD number 0110011=…….10

a.66
b.67
c.68
d.69

67.The total number of input states for 4 input or gate is

a.20
b.16
c.12
d.8

68.In a 4 input OR gate,the total number of High outputs for the 16 input states are
a.16
b.15
c.13

d. none of above
69.In a 4 input AND gate,the total number of High outputs for the 16 input states are
a.16
b.8
c.4
d.1

70.a buffer is
a. always non-inverting
b.always inverting
c. inverting or non-inverting
d.none of above

71.An AND gate has two inputs A and B and ine inhibits input S.Output is 1 if
a.A=1,B=1,S=1
b. A=1,B=1,S=0
c. A=1,B=0,S=1
d. A=1,B=0,S=0

72. An AND gate has two inputs A and B and ine inhibits input S.Out of total 8 input states,Output is 1
in
a. 1 states
b. 2 states
c. 3 states
d. 4 states

73.In a 3 input NOR gate,the number of states in which output is 1 equals

a. 1
b. 2
c. 3
d. 4

74.Which of these are universal gates

a. only NOR
b. only NAND
c. both NOR and NAND
d. NOT,AND,OR

75. In a 3 input NAND gate,the number of gates in which output in 1equals

a.8
b.7
c.6
d..5

76. A XOR gate has inputs A and B and output Y.Then the output equation is
a.Y=A+B
b.Y=AB+A’B
c.AB+ AB’
d.AB’+A’B’

77.A 14 pin NOT gate IC has………..NOT gates

a.8
b.6
c.5
d.4

78.A 14 pin AND gate IC has………..AND gates

a.8
b.6
c.4
d.2

79.The first contribution to logic was made by

a. George Boole
b. Copernicus
c. Aristotle
d. Shannon

80.Boolean Alzebra obeys

a. commutative law
b. associative law
c. distributive law
d. commutative, associative, distributive law
 UNIT-4
81. A+(B.C)=
a. A.B+C
b. A.B+A.C
c. A
d.(A+B).(A+C)

82.A.0=
a. 1
b. A
c. 0
d. A or 1

83.A+A.B=
a. B
b. A.B
c. A
d. A or B
84.Demorgan’s first theorem is
a. A.A’=0
b. A’’=A
c. (A+B)’=A’.B’
d. (AB)’=A’+B’
85. Demorgan’s second theorem is
a. A.A’=0
b. A’’=A
c. (A+B)’=A’.B’
d. (AB)’=A’+B’

86. Which of the following is true

a. SOP is a two level logic
b. POS is a two level logic
c. both SOP and POS are two level logic
d. Hybrid function is two level logic

87.The problem of logic race occurs in

a. SOP functions
b. Hybrod functions
c. POS functions
d. SOP and POS functions

88. In which function is each term known as min term

a. SOP
b. POS
c. Hybrid
d. both SOP and POS

89. In which function is each term known as max term

a. SOP
b. POS
c. Hybrid
d. both SOP and Hybrid

90. In the expression A+BC, the total number of min terms will be
a.2
b. 3
c.4
d. 5

91.The min term designation for ABCD is

a.m0
b. m10
c. m14
d. m15

92. The function Y=AC+BD+EF is

a. POS
b. SOP
c. Hybrid
d. none of above
93. The expression Y=∏M(0,1,3,4) is
a. POS
b. SOP
c. Hybrid
d. none of above

94. AB+AB’=
a. B
b. A
c.1
d. 0

95. In a four variable Karnaugh map eight adjacent cells give a

a. Two variable term
b. single variable term
c. Three variable term
d. four variable term

96.A karnaugh map with 4 variables has

a. 2 cells
b. 4 cells
c. 8 cells
d.16 cells

97.In a karnaugh map for an expression having ‘don’t care terms’ the don’t cares
can be treated as
a. 0
b. 1
c. 1 or 0
d. none of above

98. The term VLSI generally refers to a digital IC having

a. more than 1000 gates
b. more than 100 gates
c. more than 1000 but less than 9999 gates
d. more than 100 but less than 999 gates

99.Typical size of an IC is about

a.1”*1”
b. 2”*2”
c. 0.1”*0.1”
d. 0.0001”*0.0001”

100.A digital clock uses…………..chip

a. SSI
b. LSI
c. VLSI
d. MSI

101. Digital technologies being used now-a-days are

a. DTL and EMOS
b. TTL, ECL, CMOS and RTL
c. TTL, ECL and CMOS
d. TTL, ECL, CMOS and DTL

102. A TTL circuit with totem pole output has

a. high output impedance
b. low output impedance
c. very high output impedance
d. any of above

103. TTL uses

a. multi emitter transistors
b. multi collector transistors
c. multi base transistors
d. multi emitter or collector transistors

104. Advanced schottky is a part of

a. ECL family
b. CMOS family
c. TTL family
d. none of above

105. For wired AND connection we should use

a. TTL gates with active pull up
b. TTL gates with open collector
c. TTL gates without active pull up and with open collector
d. any of above

106. Time delay of a TTL family is about

a. 180ns
b. 50ns
c. 18ns
d. 3 ns

107. As compared to TTL, ECL has

a. lower power dissipation
b. lower propagation delay
c. higher propagation delay
d. higher noise margin

108. As compared to TTL, CMOS logic has

a. higher speed of operation
b. higher power dissipation
c. smaller physical size
d. all of above

109. 74HCT00 series is

a.NAND IC
b. interface between TTL and CMOS
c. inverting IC
d. NOR IC

110.CD 4010 is a
a. inverting buffer
b. non inverting hex buffer
c. NOR IC
d. NAND IC

111. Current requirement of a piezo buffer is about

a. 100mA
b. 20mA
c. 4 mA
d. 0.4 mA

112. TSL inverter has

a. one input
b. two inputs
c. one or two inputs
d. three inputs

113. Parallel adder is

a. sequential circuits
b. combinational circuits
c. either sequential or combinational circuits
d. none of above

114. The inputs to a 3 bit binary adder are 1112 and 1102. The output will be
a.101
b.1101
c.1111
d.1110

115. A half adder can be used only for adding

a. 1s
b. 2s
c. 4s
d. 8s

116. A 3 bit binary adder should be

a. 3 full adders
b. 2 full adders and 1 half adder
c. 1 full adder and 2 half adder
d. 3 half adders

117. when two 4 bit parallel adders are cascaded we get

a. 4 bit parallel adder
b. 8 bit parallel adder
c. 16 bit parallel adder
d. none of above

118. The widely used binary multiplication method is

a. repeated addition
b. add and shift
c. shift and add
d. any of above

119.When microprocessor processes both positive and negative numbers, the representation used is
a. 1’s complement
b. 2’s complement
c. signed binary
d. any of above

120. Decimal -90 =………….in 8 bit 2s complement

a.1000 1000
b.1010 0110
c.1100 1100
d.0101 0101

UNIT-5
121. In 2’s complement addition, the carry generated in the last stage is
a. added to LSB
b. neglected
c. added to bit next to MSB
d. added to the bit next to LSB

122. The number of inputs and outputs in a full adder are

a. 2 and 1
b. 2 and 2
c. 3 and 3
d. 3 and 2

123.In a 7 segment display the segments a,c,d,f,g are lit. The decimal number
displayed will be
a. 9
b. 5
c. 4
d. 2

124. In a 7 segment display the segments b and c are lit up. The decimal number
displayed will be
a. 9
b. 7
c. 3
d. 1

125 .A device which converts BCD to seven segments is called

a. encoder
b. decoder
c. multiplexer
d. none of these

126. Which device use the nematic fluid

a. LED
b. LCD
c. VF display
d. none of these

127. Which of these is the most recent device

a. LED
b. LCD
c. VF display
d. a and c

128. VF glows with ………. Colour when activated

a. red
b. orange
c. bluish green
d. none of these

129. Which display device resembles vacuum tube

a. LED
b. LCD
c. VF
d. none of these

130.Which device changes parallel data to serial data

a. decoder
b. multiplexer
c. demultiplexer
d. flip flop

131.A 1 of 4 multiplexer requires…… data select line

a. 1
b. 2
c. 3
d. 4

132. It is desired to route data from many registers to one register. The device needed is
a. decoder
b. multiplexer
c. demultiplexer
d. counter

133.Which device has one input and many outputs

a. flip flop
b. multiplexer
c. demultiplexer
d. counter

134.Two 16:1 and one 2:1 multiplexers can be connected to form a

a. 16:1 multiplexer
b. 32:1 multiplexer
c. 64:1 multiplexer
d. 8:1 multiplexer

135. A flip flop is a

a. combinational circuit
b. memory element
c. arithmetic element
d. memory or arithmetic

136. I n a D latch
a. data bit D is fed to S input and D’ to R input
b. data bit D is fed to R input and D’ to S input
c. data bit D is fed to both R and S inputs
d. data bit D’ is not fed to any input

137. I n a D latch
a. a high D sets the latch and low D resets it
b. a low D sets the latch and high D resets it
c. race can occur
d. none of above

138.In a positive edge triggered JK flip flop

a. High J and High K produce inactive state
b. Low J and High K produce inactive state
c. High J and Low K produce inactive state
d. Low J and Low K produce inactive state

139.In a positive edge triggered D flip flop

a. D input is called direct set
b.Preset is called direct reset
c. present and clear are called direct set and reset respectively
d. D input overrides other inputs

140. In a positive edge triggered JK flip flop

J=1,K=0 and clock pulse is rising.Q will
a. be 0
b. be 1
c. show no change
d. toggle

141. For edge triggering in flip flops manufacturers use

a. RC circuit
b. direct coupled design
c. either RC circuit or direct coupled design
d. none of these

142. In a JK flip flop toggle means

a. set Q=1 and Q’=0
b. set Q=0 and Q’=1
c. change the output to the opposite state
d. no change in input

143. A mod 4 counter will count

a. from 0 to 4
b. from 0 to 3
c. from any number n to n+4
d. none of above

144.A counter has N flip flops. The total number of states are
a. N
b. 2N
c. 2N
d. 4N

145.A counter has modulus of 10. The number of flip flops are
a. 10
b. 5
c. 4
d. 3

146.In a ripple counter

a. whenever a flip flop sets to 1,the next higher FF toggles
b. whenever a flip flop sets to 0,the next higher FF remains unchanged
c. whenever a flip flop sets to 1,the next higher FF faces race condition
d. whenever a flip flop sets to 0,the next higher FF faces race cond

147.A counter has 4 flip flops.It divides the input frequency by

a.4
b. 2
c. 8
d. 16

148. A decade counter skips

a. binary states 1000 to 1111
b. binary states 0000 to 0011
c. binary states 1010 to 1111
d. binary states 1111 and higher

149.The number of flip flops needed for Mod 7 counter are

a. 7
b. 5
c. 3
d. 1

150.A presettable counter with 4 flip flops start counting from

a. 0000
b. 1000
c. any number from 0000 to 1111
d. any number from 0000 to 1000
151.A 4 bit down counter can count from
a. 0000 to 1111
b. 1111 to 0000
c. 000 to 111
d. 111 to 000

152. A 3 bit up-down counter can count from

a. 000 to 111
b. 111 to 000
c. 000 to 111 and also from 111 to 000
d. none of above

153.IC counters are

a. synchronous only
b. asynchronous only
c. both synchronous and asynchronous
d. none of above

154. Shifting digits from left to right and vice versa is needed in
a. storing numbers
b. arithmetic operations
c. counting
d. storing and counting

155. The basic storage element in a digital system is

a. flip flop
b. counter
c. multiplexer
d. encoder

156. The simplest register is

a. buffer register
b. shift register
c. controlled buffer register
d. bidirectional register

157. The basic shift register operations are

a. serial in serial out
b. serial in parallel out
c. parallel in serial out
d. all of above

158. A universal shift register can shift

a. from right to left b. from left to right
c. both from right to left and left to right
d. none of above

159. In a shift register, shifting a bit by one bit means

a. division by 2
b. multiplication by 2
c. subtraction by 2
d. any of above

160. An 8 bit binary number is to be entered into an 8 bit serial shift register. The number of clock pulses
required is
a. 1
b. 2
c. 4
d. 8