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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY

ELECTRONIC ENGINEERING DEPARTMENT

COURSE INFORMATION SHEET

Session: 2021
Course Title: Digital Logic Design
Course Code: EE-220 L
Credit Hours: 0+1
Semester: 3rd
Pre-Requisites: EE-110 Basic Electronic
Instructor Name: Sadaf Raza
Email and Contact Information: sminhaj@ssuet.edu.pk and 03218998100
WhatsApp Group : EE 220 DLD Section A
Office Hours: 8:30am to 5:00pm
Mode of Teaching: Synchronous/Asynchronous/ Hybrid/Blended

COURSE OBJECTIVE:
This lab introduces the principle and application of digital devices and systems. Digital Logic
Design Laboratory helps students to understand Digital Circuits Analysis. The lab learning
process is centered on building these circuits from discrete components and analyzing them

COURSE OUTLINE:
Particularly these labs help to understand the concept of basic logic gates, hardware
implementation of combinational logic circuits such as multiplexers and de-multiplexers,
encoders/decoders, implementation of sequential circuits such as flip-flops, registers, shift
registers, counters and other digital circuits.

COURSE LEARNING OUTCOMES (CLOs) and its mapping with Program Learning Outcomes
(PLOs):

CLO Bloom’s
Course Learning Outcomes (CLOs) PLOs
No. Taxonomy
Follow the concept of digital electronics for PLO_3 P3
1. sequential and combinational circuits and use (Design/Development (Guided
these concepts in designing projects. of Solutions) Response)
Explain the knowledge acquired in design of PLO_10 A4
2.
digital logic system. (Communication) (Organization)

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
COMPLEX ENGINEERING ACTIVITY:

Complex Engineering Included: Yes

Activity Details Nature and details of Complex Engineering Problem
(CEA):
It will be given as Subject Project assigned to 2-4
students in a group.
CEA will be based on CLO_4. To investigate the
problem, students have to use in-depth knowledge of
combinational and sequential circuits and diverse
resources are required
Attributes could be: EA1, WK5, WA3
EA1: Diverse Resources required
WK5: Engineering Design
WA3: Design/Development of Solutions
Assessment in: Subject Project

RELATIONSHIP BETWEEN ASSESSMENT TOOLS AND CLOS:

Assessment Tools CLO-1 (40) CLO-2 (10)

Lab Manual 37.5% (15) -
Subject Project
25% (10)

Lab Exam 37.5% (15) -

Viva 100% (10)

GRADING POLICY:

Assessment Tools Percentage

Lab Manual 30% (15 Marks)
Subject Project 30% (15 Marks)
Lab Exam 40% (20 Marks)
Total 100% (50 Marks)

Recommended Book:

 Thomas I. Floyd, Digital Fundamental, published by Pearson Education, 09th Edition.

Reference Books:
 M. Morris Mano, Digital Logic and Computer Design, published by Prentice Hall, 2002,
ISBN: 0-13-062121-8

 Parag K. Lala, Principle of Modern Digital Design, published by John Wilsey & Sons.

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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
COURSE BREAKDOWN WITH LAB SYNCHRONIZATION:

Week
Topics Laboratory Titles
No.
Introduction to digital and analog quantities, binary
digits, logic levels and digital waveforms, introduction LOGIC GATES[1]
1 to basic logic operation [1]. Decimal Number, Binary
Number, Decimal-to-Binary Conversion, Binary-to-
Decimal.
Binary Arithmetic, 1’s and 2’s Complement of Binary
Numbers. Signed Number, Arithmetic Operation with
signed numbers, Hexadecimal Numbers, Octal BOOLEAN ALGEBRA AND
2 Numbers, and Binary Coded Decimal (BCD). Boolean DEMORGAN’S LAW[2]
Operation and Expressions Law and Rules of Boolean
Algebra, DeMorgan’s Theorem[2]

BOOLEAN FUNCTION BY LOGIC

Boolean Analysis of Logic Circuits[3]. Simplification GATES[3]
3
using Law and Rules of Boolean Algebra.

Standard Forms of Boolean Expressions, Boolean

Expressions and Truth Tables. Basic Combinational COMBINATIONAL LOGIC CIRCUITS
Logic Circuits, implementing Combinational Logic.
4 WITH NAND AND NOR GATES[4]
The Universal Property of NAND and NOR Gates[4].

The Karnaugh Map, Karnaugh Map SOP Minimization. DESIGN COMBINATIONAL CIRCUIT
Karnaugh Map POS minimization, Five- Variable
5 USING KARNAUGH MAP[5]
Karnaugh Maps[5].

Basic Adders, half adder, Full adder, Parallel Binary

Adders, Ripple Carry versus Look-Ahead Carry BINARY ADDER[6]
6
Adders[6].

OPEN ENDED LAB

Comparator, The 4 bit Magnitude Comparators[7],
7
Decoders, and Encoders[8].

8 MID TERM

9 Code converters, Multiplexers (Data Selectors), BINARY COMPARATORS[7]

Demultiplexer[9], Parity Generator
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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT

DECODER and ENCODER[8]

Latches, Edge-Triggered Flip-Flops[10]. Flip-Flop
10
Operation Characteristics, Flip-Flop Application.

Asynchronous Counter Operation, Synchronous MULTIPLEXER and

11 Counter[11] Operation, Up/ Down Synchronous DEMULTIPLEXER[9]
Counters.
Design of Synchronous Counters, Cascaded Counters, RS, D FLIP-FLOP and
12 Counter Decoding, Counter Applications. J-K Flip Flop[10].

Basic Shift Register Functions, Serial In/ Serial Out Shift

13 Registers[12], Serial In/ Parallel Out Shift Registers, Digital Counters [11]
Parallel In/ Serial Out Shift Registers,
Parallel In/ Parallel Out Shift Registers. Bidirectional SERIAL IN SERIAL OUT SHIFT
14 Shift Registers, Shift Register Applications. REGISTER [12]

Basic of Semiconductors Memory, Random-Access

Memories (RAMs) Read - only Memories (ROMs),
Programmable ROMs (PROMs and EPROMs. Flash
15 Memories, Memory Expansion, and Special type of OPEN ENDED LAB
memories. Bipolar-Transistors Characteristics, RTL and
DTL Circuits.

Introduction to TTL logic family. Comparison of TTL and

CMOS logic family’s levels. Interfacing of TTL with
16 FINAL VIVA
CMOS. Introduction to programmable logic devices
(PLA, SPLDs, CPLDs and FPGAs)

LAB PLAN
Course Title: Digital Logic Design
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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
Course Code: EE 220 L

Week Required
Lab Date Objective
No. Reading
15-02-2021 Follow the concepts of basic logic gates and Floyd
1 to verifies their truth tables. Pg.: 114-143
19-02-2021
22-02-2021 Follow the De Morgan’s theorem, Boolean
Floyd
2 to algebra law, rule and verifies them by using
Pg.: 184-191
26-02-2021 logic gates
Reproduce the following Boolean functions
using basic logic gates.
01-03-2021
to a) A + A’B Floyd
3
b) AB + BC (B +C) Pg.:192-199
05-03-2021
c) ((A + BC)’ + (A.B’)’)’

08-03-2021
Reproduce the combinational logic gates Floyd
4 to
using NOR and NAND gates. Pg.:256-262
12-03-2021
15-03-2021 Follow the concept of a Karnaugh map
Floyd
5 to implement a combinational circuits and 3 bit
Pg: 210-220
19-03-2021 even parity.
Reproduce Half Adder Circuit, Full Adder
22-03-2021 Circuit using basic gates and verify the Floyd
6
to results of Pg: 298-307
26-03-2021 4 – Bit Full Adder Circuit using IC 7483.

29-03-2021
7 to Open Ended Lab
02-04-2021
Mid Term Examination
8
(05-04-2021 to 10-04-2021)
12-04-2021 Reproduce a 1 – Bit Binary Comparator
Floyd
9 to using basic gates and 4 – Bit Binary
Pg: 311-315
16-04-2021 Comparator using IC 7485.
19-04-2021 Follow the concept of Decoder and Encoder Floyd
10 to using IC 74154 and 74147. Pg: 316-320
23-04-2021
Reproduce the 4 X 1 MUX using basic
26-04-2021 Floyd
to
gates, 16 X 1 MUX using IC 74150, 1 X 4
11 Pg: 331-343
30-04-2021 DEMUX using basic gates, 1 X 8 DEMUX
using basic gates.
12 03-05-2021 Reproduce RS Flip Flop using NAND & Floyd
to NOR gates, D Flip Flop using NAND gates, Pg: 372-385
07-05-2021
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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT

JK Flip Flop using NAND Gates.

Follow the concept of 3 bit Up/Down

10-05-2021
13
to Counter and BCD counter using IC 74190 Floyd
and 7447. Pg:444-446
14-05-2021

17-05-2021 Reproduce 4 bit serial in serial out (SISO) Floyd

14 to shift register by using 7494A IC. Pg:494-498
21-05-2021
24-05-2021
15 to Open Ended Lab
28-05-2021
Lab Examination
16 (31-05-2021 to 04-06-2021)

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