GUJARAT TECHNOLOGICAL UNIVERSITY

Bachelor of Engineering
Subject Code: 3131102
Semester III
Digital System Design

Type of course: Design and Analysis of Digital Circuits

Prerequisite: Basic Electronics and Number Systems.

Rationale: The students need to learn basic concepts of digital circuits and system which leads to design of
complex digital system such as microprocessors. The students need to know combinational and sequential
circuits using digital logic fundamentals. The students will learn the design of combinational and sequential
circuit. This is the first course by which students get exposure to digital electronics world.

Teaching and Examination Scheme:

Teaching Scheme Credits Examination Marks Total

L T P C Theory Marks Practical Marks Marks
ESE PA ESE PA
(E) (M) Viva (V) (I)
4 0 2 5 70 30 30 20 150

Sr. Content Total %

No. hours Weightage

1 Review of number systems, logic gates, Boolean algebra - postulates and 7 15

theorems, SOP & POS forms, canonical forms, logic minimization using
Karnaugh Map and tabulation methods up to 6 variables, Realizing logic
functions using gates.
2 Combinational logic circuit design: half adder full adder, BCD adder, code 8 15
converters, magnitude comparator, multiplexers and decoders, MSI digital
circuit design problems.
3 Sequential logic circuit design: Flip Flops-SR, JK, T, D and master-slave FF, 7 15
ripple and synchronous counters, shift registers.
4 Introduction to Finite State Machines (FSM): The need for state machines, 5 10
The state machine, basic concepts in state machine analysis.
5 Synchronous state machine design: Sequential counters, state changes 9 15
referenced to clock, number of state flip-flops, input forming logic, output
forming logic, generation of a state diagram from a timing chart, redundant
states, general state machine architecture. Concept of asynchronous state
machine and comparison to synchronous state machine.
6 Logic families: Specifications, noise margin, propagation delay, fan-in, fan- 5 10
out, Transistor-Transistor Logic (TTL), Emitter-Coupled Logic (ECL),
CMOS Logic, TTL and CMOS Gates,Introduction to basics of FINFET
7 Programmable Logic Devices: Introduction to Programmable Logic Devices, 5 10
Read-Only Memory, Programmable Logic Arrays (PLA), Programmable
Array Logic (PAL), Combinational PLD-Based State Machines, State
Machines on a Chip.
8 VLSI Design flow: Design entry: Schematic, FSM & HDL, different 5 5
modeling styles in Verilog: Behavioral and Structural Modeling, Data types
and objects, Synthesis and Simulation Verilog constructs and codes for
combinational and sequential circuits.
9 A to D Converter and D to A Converter: Introduction, Digital to Analog 5 5
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 GUJARAT TECHNOLOGICAL UNIVERSITY
Bachelor of Engineering
Subject Code: 3131102
Conversion : Weighted Resistor D/A Converter, R-2R Ladder D/A
Converter, Specifications for D/A Converters,An Example of D/A Converter
IC: Digital Input Codes, Analog output, Calibration, Sample and Hold,
Analog to Digital Converters: Quntization and Encoding, Parallel
Comparator A/D Converter, Counting A/D Converter, Dual Slope A/D
Converter, A/D Converter Using Voltage to frequency conversation, A/D
Converter Using Voltage to time conversation, Specification of A/D
Converters An Example of A/D Converter IC: Operation , Digital Output,
Analog Input, Calibration
Total 56 100

Suggested Specification table* with Marks (Theory):

Distribution of Theory Marks
R Level U Level A Level N Level E Level C Level
20 20 10 10 5 5

Legends: R: Remembrance; U: Understanding; A: Application, N: Analyze and E: Evaluate C:

Create and above Levels (Revised Bloom’s Taxonomy).ode: 2921103

*This specification table shall be treated as a general guideline for students and teachers. The
actual distribution of marks in the question paper may vary from above table.

Reference Books:
1. Digital Logic & State Machine Design By David J. Comer, Third Indian Edition, Oxford
University Press
2. Digital Logic and Computer Design By M Morris Mano, Fourth Edition, Prentice Hall Publication
3. Digital Principles and Applications By Malvino & Leach, Seventh Edition, McGraw-Hill Education
4. Modern Digital Electronics By R.P.Jain, Fourth Edition, Tata McGraw-Hill Education.
5. Digital Electronics: Principles and Integrated Circuits By A.K. Maini, Wiley India Publications
6. Digital Design M. Morris Mano and Michael D. Ciletti, Pearson Education
7. A Verilog HDL Primer by J. Bhaskar, Third Edition, BS Publication
8. Fundamentals of Digital Logic with Verilog Design by Brown and Vrenesic, Second Edition,
McGrawHill publication.

Course Outcomes:
After learning the course the students should be able to

Sr. No. CO statement Marks %

weightage
CO-1 apply the knowledge of digital number systems, Boolean algebra, and logic gates 25
for logic function minimization.
CO-2 design and analysis combinational and sequential circuits 30
CO-3 design synchronous and asynchronous circuits FSM. 20
CO-4 comprehend the digital logic families and PLDs 10
CO-5 implement digital circuits using Verilog based VLSI design flow 15

List of Experiments:
1. Getting familiar with various digital integrated circuits of different logic families. Study of data
sheet of these circuits and see how to test these circuits using Digital IC Tester.
2. Digital IC Testers and Logic State Analyzer as well as digital pattern generators should be
demonstrated to the students.
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 GUJARAT TECHNOLOGICAL UNIVERSITY
Bachelor of Engineering
Subject Code: 3131102
3. Configure transistor as logic gates and Digital ICs for verification of truth table of logic gates
4. Configuring NAND and NOR logic gates as universal gates.
5. Implementation of Boolean Logic Functions using logic gates and combinational circuits. Measure
digital logic gate specifications such as propagation delay, noise margin, fan in and fan out.
6. Study and configure various digital circuits such as adder, subtractor, decoder, encoder, code
converters.
7. Study and configure multiplexer and demultiplexer circuits.
8. Study and configure flip-flop, registers and counters using digital ICs. Design digital system using
these circuits.
9. Perform an experiment which demonstrates function of 4 bit or 8 bit ALU.
10. Introduction to HDL. Use of Verilog HDL in simulation of digital circuits studied in previous
sessions using integrated circuits. Illustrative examples using FPGA or CPLD boards.

Design based Problems (DP)/Open Ended Problem:

1. Design of combinational lock circuits with varying number of bits (For example 4, 8 …..)
2. Design of various types of counters.
3. Design of Arithmetic and Logic Unit using digital integrated circuits.
4. Design of digital integrated circuit tester
5. Measurement of logic family specifications.
6. Design project for example digital clock, digital event counter, timers, and various multi-vibrator
Circuits, small processor, ports or scrolling display.

A student and faculty may choose any other such problem which includes the concept used in the course.

Major Equipments:
1. Pattern Generators
2. Logic State Analyzers
3. Digital Storage Oscilloscopes
4. Digital Integrated Circuits Tester.
5. Complete Bread Board Systems, switches and I/O indicators, multimeters, pulse, square wave generators
and display facility.

List of Open Source Software/learning website:

1. Web packages for HDL, GHDL, Free HDL
2. PSpices and NGSpice
3. Xcircuit and Scilab
4. NPTEL website and IITs virtual laboratory

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Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE- SEMESTER–III (NEW) EXAMINATION – WINTER 2020
Subject Code:3131102 Date:04/03/2021
Subject Name:Digital System Design
Time:10:30 AM TO 12:30 PM Total Marks:56
Instructions:
1. Attempt any FOUR questions out of EIGHT questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
MARKS

Q.1 (a) State and prove De-Morgan’s Theorem. 03

(b) Explain Moore machine. 04
(c) Simplify the following Boolean expression by means of the Tabulation 07
method.
F(A,B,C,D) = ∑m (1,2,3,5,6,7,8,9,12,13,15).
Q.2 (a) Give comparison of TTL and CMOS family. 03
(b) Implement the given function using 8 X 1 multiplexer. 04
F(A,B,C,D) = ∑m (0,1,2,3,5,8,9,11,14).
(c) Design synchronous BCD counter using JK flip flop. 07

Q.3 (a) Explain universal gates. 03

(b) Compare ROM, PLA and PAL. 04
(c) Design a counter to generate the repetitive sequence 0,1,2,4,3,6. 07

Q.4 (a) Explain half adder circuit. 03

(b) Convert SR Flip Flop to JK Flip Flop. 04
(c) Design a counter to generate the repetitive sequence 0,3,5,7,4. 07

Q.5 (a) Define: i) Fan-in ii) Fan-out iii) Propagation delay 03

(b) Construct a Johnson counter with ten timing signals. 04
(c) Design BCD to Excess 3 code converter. 07

Q.6 (a) Compare combinational and sequential logic circuits. 03

(b) Explain different modeling styles in Verilog. 04
(c) Explain Dual Slope A/D converter in detail. 07

Q.7 (a) Describe magnitude comparator. 03

(b) Express the Boolean function F=AB+A’C in a product of max term. 04
(c) Explain Emitter Coupled Logic (ECL) in detail. 07

Q.8 (a) Explain briefly 3 line to 8 line decoder. 03

(b) Explain Mealy machine. 04
(c) Write a short note on 4-bit Universal Shift Register. 07
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Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–III (NEW) EXAMINATION – SUMMER 2021
Subject Code:3131102 Date:11/09/2021
Subject Name:Digital System Design
Time:10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

MARKS
Q.1 (a) Convert as below 3
(i) (10101010)2 = ( )8 = ( )16
(ii) (673.10)8 = ( )2
(iii) (ACE)16 = ( )10
(b) Show that NAND & NOR are universal gates 4
(c) Minimize the following function in SOP minimal form using K-Maps: 7
F(A, B, C, D) = m(1, 2, 6, 7, 8, 13, 14, 15) + d(3, 5, 12)
Q.2 (a) Explain SOP & POS form. 3
(b) Implement the 8× 1 MUX using two 4 ×1 MUX. 4
(c) Design a 4 bit binary to gray code converter and implement using EX-OR gates 7
only.
OR
(c) Design a combination circuit to display 0 to 9 on seven segment. 7
Q.3 (a) State and prove De Morgan’s theorem 3
(b) Implement Full Adder using 3×8 decoder. 4
(c) Explain about JK & RS Flip Flop circuit using its symbol, block diagram, truth 7
table and characteristics equation.
OR
Q.3 (a) Distinguish between combinational and sequential logic circuits. 3
(b) Implement the following Boolean function F(w, x, y, z) = Σ (2, 3, 5, 6, 11, 14, 4
15) with a multiplexer.
(c) Explain Bidirectional Shift Register with parallel load. 7

Q.4 (a) Derive excitation tables for R-S, J-K and T flip-flops. 3
(b) Implement T flip flop using D flip flop. 4
(c) What is a PLA circuit? Explain in details about it. 7

OR
Q.4 (a) What is sample & Hold? 3
(b) Compare TTL, ECL and CMOS Logic. 4
(c) Explain Master Slave JK flip-flop with truth table and circuit diagram 7

Q.5 (a) Define Noise margin, Propagation delay, fan-in and fanout 3
(b) Design 3-bit synchronous up counter using T flip flop 4
(c) Explain about a synchronous counter using 3 bits. 7
OR
Q.5 (a) Explain any one D/A converter. 3
(b) Draw and explain Ring counter 4
(c) Describe the operation of 4-bit bidirectional shift register with logic diagram 7
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Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–III (NEW) EXAMINATION – WINTER 2021
Subject Code:3131102 Date:21-02-2022
Subject Name:Digital System Design
Time:10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

Q.1 (a) Draw the logic circuit for the following Boolean function using NAND gates only. 03
F(x, y, z) = xy + yz + xz
(b) State the De-Morgan’s Law and find the complement of the following Boolean 04
function in Product-of-Sum (POS) form using De-Morgan’s Law.
F(A, B, C, D) = AB’(C+D) + C’D(A’+B)
(c) Simplify the following Boolean function using Karnaugh Map (K-map) method. 07
F(A, B, C, D) = (A’ + B’ + D’)(A + B’ + C')(A’ + B + D’)(B + C’ + D’)
Realize the simplified function using NOR Gates only.

Q.2 (a) State the duality theorem. Also find the dual of the following Boolean expression. 03
(x + y)(x’ + z)(y + z) = (x + y)(x’ + z)
(b) Simplify the following Boolean expression using Boolean Algebra. 04
(i) x’ + xy + xz’ + xy’z’
(ii) A’B(D’ + C’D) + B(A + A’CD)
(c) Explain the working of Master-Slave SR Flip-flop with Logic diagram and 07
waveforms.
OR
(c) Draw the logic circuit of 4-to-1 Multiplexer and explain its working with the help 07
of truth-table.

Q.3 (a) Draw truth-table and logic circuit for 2-bit magnitude comparator. 03
(b) Explain the following parameters for Digital Integrated Circuits. 04
(i) Fan-out
(ii) Fan-in
(iii)Propagation Delay
(iv) Noise Margin
(c) Find the prime implicants for the following Boolean function by means of the 07
Tabulation Method.
F(A, B, C, D, E) = Σm (2, 3, 8, 9, 12, 13, 18, 19, 25, 27, 29, 31)
OR
Q.3 (a) Explain working of 4-bit Binary Adder circuit with the neat logic diagram. 03
(b) Compare TTL and CMOS logic families. 04
(c) Simplify the following Boolean function F together with the don't-care conditions 07
d in sum-of-products (SOP) using Karnaugh Map (K-map) method.
F(A, B, C, D) = Σm(3, 4, 13, 15) and d(A, B, C, D) = Σm(l, 2, 5, 6, 8, 10, 12, 14)

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Q.4 (a) State the difference between asynchronous and synchronous sequential logic 03
circuits with suitable example.
(b) What is State Machine? Explain the need of State Machine in Digital Systems. 04
(c) A sequential circuit with two D flip-flops (A and B); one input (x); and one output 07
(y) is specified by the following state table:
Present State Next State (AB) Output (y)
(AB) x=0 x=1 x=0 x=1
00 01 00 1 0
01 01 11 0 1
10 00 10 0 1
11 11 10 1 0
Derive the next-state equations, output equation and draw the state diagram.
OR
Q.4 (a) State and explain different types of triggering for Flip-flops. 03
(b) State the different types of Shift-Registers and explain working of the Serial-In 04
Serial-Out shift register with neat diagram.
(c) Design modulo-10 ripple up counter and explain its working using neat logic 07
diagram and waveforms.

Q.5 (a) Define: Register, Ripple counter, Synchronous counter. 03

(b) State various types of Digital-to-Analog converters and briefly explain working 04
principle of any.
(c) Draw and explain PLA block diagram. Also draw the Programmable Logic Array 07
with three inputs, three product terms, and two outputs.
OR
Q.5 (a) Briefly explain the steps for VLSI design flow. 03
(b) Realize T Flip-flop functionality using D Flip-flop only. 04
(c) Explain dual slope type Analog-to-Digital converter in detail with neat diagram. 07

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