Introduction

This chapter provides a brief history of the development of VHDL and describes the major
capabilities that differentiate it from other hardware description languages. The chapter also
explains the concept of an entity.

1.1 What Is VHDL?

VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for
Very High Speed Integrated Circuits). It is a hardware description language that can be used
to model a digital system at many levels of abstraction ranging from the algorithmic level to
the gate level. The complexity of the digital system being modelled could vary from that of a
simple gate to a complete digital electronic system, or anything in between. The digital
system can also be described hierarchically. Timing can also be explicitly modelled in the
same description.

The VHDL language can be regarded as an integrated amalgamation of the following languages:
sequential language +
concurrent language +
net-list language +
timing specifications +
waveform generation language => VHDL

Therefore, the language has constructs that enable you to express the concurrent or sequential
behaviour of a digital system with or without timing. It also allows you to model the system
as an interconnection of components. Test waveforms can also be generated using the same
constructs. All the above constructs may be combined to provide a comprehensive
description of the system in a single model.

The language not only defines the syntax but also defines very clear simulation
semantics for each language construct. Therefore, models written in this language can be
verified using a VHDL simulator. It is a strongly typed language and is often verbose to
write. It inherits many of its features, especially the sequential language part, from the Ada
programming language. Because VHDL provides an extensive range of modelling
capabilities, it is often difficult to understand. Fortunately, it is possible to quickly assimilate
a core subset of the language that is both easy and simple to understand without learning the
more complex features. This subset is usually sufficient to model most applications. The
complete language, however, has sufficient power to capture the descriptions of the most
complex chips to a complete electronic system.

(Ada is a registered trademark of the U.S. Government, Ada Joint Program Office)
1.2 History

The requirements for the language were first generated in 1981 under the VHSIC program. In
this program, a number of U.S. companies were involved in designing VHSIC chips for the
Department of Defence (DoD). At that time, most of the companies were using different
hardware description languages to describe and develop their integrated circuits. As a result,
different vendors could not effectively exchange designs with one another. Also, different
 vendors provided DoD with descriptions of their chips in different hardware description
languages. Re-procurement and reuse was also a big issue. Thus, a need for a standardized
hardware description language for design, documentation, and verification of digital systems
was generated.

A team of three companies, IBM, Texas Instruments, and Intermetrics, were first
awarded the contract by the DoD to develop a version of the language in 1983. Version 7.2 of
VHDL was developed and released to the public in 1985. There was strong industry
participation throughout the VHDL language development process, especially from the
companies that were developing VHSIC chips. After the release of version 7.2, there was an
increasing need to make the language an industry-wide standard. Consequently, the language
was transferred to the IEEE for standardization in 1986. After a substantial enhancement to
the language, made by a team of industry, university, and DoD representatives, the language
was standardized by the IEEE in December 1987; this version of the language is now known
as the IEEE Std 1076-1987. The official language description appears in the IEEE Standard
VHDL Language Reference Manual made available by the IEEE. The language described in
this book is based on this standard. The language has since also been recognized as an
American National Standards Institute (ANSI) standard.

The Department of Defence, since September 1988, requires all its digital
Application-Specific Integrated Circuit (ASIC) suppliers to deliver VHDL descriptions of the
ASICs and their subcomponents, at both the behavioural and structural levels. Test benches
that are used to validate the ASIC chip at all levels in its hierarchy must also be delivered in
VHDL. This set of government requirements is described in military standard 454.

1.3 Capabilities
The following are the major capabilities that the language provides along with the features
that
Differentiate it from other hardware description languages.

• The language can be used as an exchange medium between chip vendors and CAD tool users.
Different chip vendors can provide VHDL descriptions of their components to system
designers. CAD tool users can use it to capture the behaviour of the design at a high level of
abstraction for functional simulation.

• The language can also be used as a communication medium between different CAD and CAE
tools, for example, a schematic capture program may be used to generate a VHDL description
for the design which can be used as an input to a simulation program.

• The language supports hierarchy, that is, a digital system can be modelled as a set of
interconnected
Components; each component, in turn, can be modelled as a set of interconnected
subcomponents.
• The language supports flexible design methodologies: top-down, bottom-up, or mixed.
• The language is not technology-specific, but is capable of supporting technology-specific
features. It can also support various hardware technologies, for example, you may define new
logic types and new components, and you may also specify technology-specific attributes. By
being technology independent, the same behaviour model can. be synthesized into different
vendor libraries.

• It supports both synchronous and asynchronous timing models.

• Various digital modelling techniques such as finite-state machine descriptions, algorithmic
descriptions,
And Boolean equations can be modelled using the language.
• The language is publicly available, human readable, machine readable, and above all, it is
not proprietary.
• It is an IEEE and ANSI standard, and therefore, models described using this language is
portable. The government also has a strong interest in maintaining this as a standard so that
re-procurement and second-sourcing may become easier.
• The language supports three basic different description styles: structural, dataflow, and
behavioural. A design may also be expressed in any combination of these three descriptive
styles.

• It supports a wide range, of abstraction levels ranging from abstract behavioural descriptions
to very precise gate-level descriptions. It does not, however, support modelling at or below
the transistor level. It allows a design to be captured at a mixed level using a single coherent
language.

•Arbitrarily large designs can be modelled using the language and there are no limitations
that are imposed by the language on the size of a design.
• The language has elements that make large scale design modelling easier, for example,
components, functions, procedures, and packages.
• There is no need to learn a different language for simulation control. Test benches can be
written using the same language to test other VHDL models.
• Nominal propagation delays, min-max delays, setup and hold timing, timing constraints,
and spike detection can all be described very naturally in this language.
• The use of generics and attributes in the models facilitate back-annotation of static
information such as timing or placement information.
• Generics and attributes are also useful in describing parameterized designs.
• A model can not only describe the functionality of a design, but can also contain
information about the design itself 'in terms of user-defined attributes, for example, total area
and speed.

• A common language can be used to describe library components from different vendors. Tools
that understand VHDL models will have no difficulty in reading models from a variety of
vendors since the language is a standard.

• Models written in this language can be verified by simulation since precise simulation
semantics are defined for each language construct.
• Behavioural models that conform to a certain synthesis description style are capable of
being synthesized to gate-level descriptions.
• The capability of defining new data types provides the power to describe and simulate a
new design technique at a very high level of abstraction without any concern about the
implementation details.
1.4 Hardware Abstraction

VHDL is used to describe a model for a digital hardware device. This model specifies the
external view of the device and one or more internal views. The internal view of the device
specifies the functionality or structure, while the external view specifies the interface of the
device through which it communicates with the other models in its environment. Figure I.I
shows the hardware device and the corresponding software model.

The device to device model mapping is strictly a one to many. That is, a hardware
device may have many device models. For example, a device modelled at a high level of
abstraction may not have a clock as one of its inputs, since the clock may not have been used
in the description. Also the data transfer at the interface may be treated in terms of say,
integer values, instead of logical values. In VHDL, each device model is treated as a distinct
representation of a unique device, called an entity in this text. Figure 1.2 shows the VHDL
view of a hardware device that has multiple device models, with each device model
representing one entity. Even though entity I through N represents N different entities from
the VHDL point of view, in reality they represent the same hardware device

-Vishi Agrawal

ECE-5th sem

GGITM