5

Sequential MOS Logic Circuits

Contents:

5.1 Introduction
5.2 Behaviour of Bistable elements
5.3 The SR Latch Circuit
5.4 Clocked Latch and Flip-flop Circuit
5.5 CMOS D-latch and Edge-triggered Flip-flop

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5.1 Introduction

In combinational logic, the output levels can be determined as Boolean functions of the
input variables applied at that time. They don’t have any capability of storing any
previous events, or displaying an output behavior that is dependent upon the previous
inputs. They are classified as non-regenerative circuits, since there is no feedback
relationship between the output and the input.

In sequential circuits, the output is determined by the current inputs as well as the
previous inputs. Figure 5.1 shows a sequential circuit consisting of a combinational
circuit and a memory block in the feedback loop. They are classified as non-
regenerative circuits, since there is no feedback relationship between the output and the
input. The regenerative circuits are critical components of sequential systems that can
be classified into three main groups: bistable circuits, monostable circuits, and astable
circuits. The general classification of logic circuits is shown in Fig. 5.2

Fig. 5.1 Sequential circuit

Bistable circuits have two stable states. Monostable circuits have only one stable
operating point (state). If the circuit experiences an external perturbation, the output
returns to the single stable state after a certain time period. In astable circuits, there is
no stable operating point or state, which the circuit can preserve. The output of an
astable circuit must oscillate without settling into a stable operating mode Ring

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oscillator is an example of astable circuit while all basic latch and flip-flop circuits,
registers, and memory elements used in digital systems fall into bistable category.

Fig. 5.2 Classification of logic circuits

5.2 Behaviour of Bistable elements

The basic bistable element consists of two identical cross-coupled inverter circuits, as
shown in Fig. 5.3(a). Here, the output voltage of inverter (1) is equal to the input
voltage of inverter (2), and the output voltage of inverter (2) is equal to the input voltage
of inverter (1).

Figure 5.3(b) shows voltage transfer characterisitcs (VTC) of cross coupled inverters
shown in Fig. 5.3(a). The two VTCs intersect at three points; two of these operating
points are stable. If the circuit is operating at one of these two stable points, it will
preserve this state unless it is forced externally to change its operating point. The slope
of the respective VTC (gain) is smaller than unity at the two stable operating points.
Thus, in order to change the state by moving the operating point from one stable point
to the other, a sufficiently large external voltage must be applied so that the voltage

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gain of the inverter loop becomes larger than unity. The voltage gains of both inverters
are larger than unity at the third operating point(unstable).

Fig. 5.3 Static behavior of the two-inverter basic bistable element:

(a) Circuit schematic. (b) Intersecting voltage transfer curves of the two inverters.
(c) Qualitative view of the energy levels corresponding to the three operating points.

Fig. 5.4 (a) Circuit diagram of a CMOS bistable element. (b) Time-domain behavior of the output
voltages, if the circuit is initially set at its unstable operating point.

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The circuit is called bistable as it has two stable operating points. The bistable behavior
of the cross-coupled inverter circuit can also be visualized through the total potential
energy level at each of the three possible operating points (Fig. 5.3(c)). It can be seen
that the potential energy is at its minimum at two of the three operating points, since
the voltage gains of both inverters are equal to zero. The energy attains a maximum at
the operating point at which the voltage gains of both inverters are maximum. Thus,
two stable operating points correspond to the two energy minima, and one unstable
operating point corresponds to the potential energy maximum.

Figure 5.4(a) shows the circuit diagram of a CMOS two-inverter bistable element. The
unstable operating point of this circuit, all four transistors are in saturation, resulting in
maximum loop gain for the circuit. The output voltages of the two inverters settle at
VOH and VOL, respectively, as shown in Fig. 5.4(b).

Fig. 5.5 Small-signal input and output currents of the inverters.

Fig. 5.5 shows, small signal current and voltage for two inverters. Here,

. Using small signal analysis approach, time domain

behavior of output voltage Vo1 can be written as follows:

5.3 The SR Latch Circuit

The simple two-inverter circuit discussed above has no provision for allowing its state
to be changed from one stable operating mode to the other. To allow such a change of
state, simple switches can be used to force or trigger the circuit from one operating
point to the other. Figure 5.6 shows the gate level schematic of SR latch, which has two

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triggering inputs, S (set) and R (reset). The SR latch is also called an SR flip-flop, since
two stable states can be switched back and forth. The circuit consists of two NOR gates.
One of the input terminals of each NOR gate is used to cross-couple to the output of
the other NOR gate, while the second input enables triggering of the circuit.

Fig. 5.6 Gate-level schematic and block diagram of the NOR-based SR latch

The SR latch has two complementary outputs, Q and Q . Here, set state means Q is equal to
logic “1" and Q is equal to logic "0." The reset state indicates output Q is equal to logic "0"
and Q is equal to "1."

Here, when both input signals are equal to logic "0," the SR latch preserves its previous
state (hold). If the S input is equal to logic "1" and the R input is equal to logic "0," then
the output Q is equal to logic “1 " and output Q is equal to logic "0." This indicates set
condition of SR latch. Similarly, if S is equal to "0" and R is equal to "1," then the
output node Q will be forced to "0" while Q is forced to "1." Thus, the latch is reset, for
this condition of inputs. Finally, when both of the inputs S and R are equal to logic “1”,
both output nodes will be forced to logic "0." However, Q and Q must be
complementary. Therefore, this input combination is not permitted during normal
operation and is considered to be a not allowed condition. The truth table of the NOR-
based SR latch is summarized in the following:

Table 5.1 Truth table of the NOR-based SR latch circuit

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Figure 5.7 shows CMOS implementation of NOR based SR latch. The operation can be
understood well based on conduction of four nMOS transistors - M1 to M4. If the S
input is equal to VOH and the R input is equal to VOL, both of the parallel-connected
transistors Ml and M2 will be on. Hence, the voltage on node Q will be VOL = 0. Under
this condition, both M3 and M4 are turned off, which results in a logic-high voltage
VOH at node Q. If the R input is equal to VOH and the S input is equal to VOL, the
situation will be reversed (Ml and M2 turned off and M3 and M4 turned on). Hence Q
and Q will be at VOL and VOH respectively. When both of the input voltages are
equal to VOL, there are two possibilities. Depending on the previous state of the SR
latch, either M2 or M3 will be on, while both of the trigger transistors M1 and M4 are
off. This will generate a logic-low level of VOL = O at one of the output nodes, while
the complementary output node is at VOH. Table 5.2 summarized all above mentioned
possibilities.

Fig. 5.7 CMOS SR latch circuit based on NOR gates.

Table 5.2. Operation of nMOS transistors in the NOR-based CMOS SR latch.

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The NOR-based SR latch can also be implemented by using two cross-coupled
depletion-load nMOS NOR gates, as shown in Fig.5.8. The operation of this circuit is
identical to that of the CMOS SR latch discussed above. However, CMOS circuit
implementation offers advantage in terms of power dissipation and noise margins. This
is due to the fact that the CMOS NOR gates dissipate virtually no static power for
preserving a state, and the output voltages can exhibit a full swing between 0 and VDD.

The SR latch can also be implemented through NAND gates as shown in Fig. 5.9. Here,
one input of each NAND gate is used to cross-couple to the output of the other NAND
gate, while the second input enables external triggering.

Here, when both input signals are equal to logic "0," both output nodes will be at logic-
high, which is not allowed because it violates the complementarity of the two outputs.
Now, if S is equal to "0" and R is equal to “1," the output Q becomes logic “1” value
and the Q becomes logic "0." Assuming S and R active low inputs, the latch is in set
condition. If S is equal to "1" and R is equal to “0," the output Q becomes logic “0”
value and the Q becomes logic "1." This is reset condition of latch. The NAND based
SR latch preserves its state when both of the inputs equal to logic “1." The truth table
of the NAND SR latch is also shown in the following. Figure 5.10 shows CMOS
implementation of NAND SR latch.

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The NAND-based SR latch can also be implemented by using two cross-coupled
depletion-load NAND gates, as shown in Fig. 5.11. The operation principle is identical
to that of the CMOS NAND SR latch (Fig. 5.10), the CMOS circuit implementation
again offers a better alternative in terms of static power dissipation and noise margins.

5.4 Clocked Latch and Flip-flop Circuit

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The SR latch circuits described in the previous section are asynchronous sequential
circuits, which respond to the changes in input signals. The synchronous circuit can be
designed by adding a gating clock signal. In the synchronous circuits, outputs will
respond to the input levels only during the active period of a clock pulse.

The gate-level schematic of a clocked NOR-based SR latch is shown in Fig. 5.12. The
clock pulse is a periodic square waveform. If the clock (CK) is equal to logic "0," the
outputs of the two AND gates will remain at logic "0," which forces the SR latch to
hold its state. The input signals have no influence upon the circuit response. When the
clock input goes to logic " 1," state changes as per input conditions.

Fig. 5.12 Gate-level schematic of the clocked NOR-based SR latch.

To understand the operation of the clocked SR latch, a sample sequence of CK, S, and
R waveforms and the corresponding output waveform Q are shown in Fig. 5.13. The
circuit is high level-sensitive during active clock phases, i.e., output follows input when
the CK level is equal to " 1 ". Even a narrow spike or glitch occurring during an active
clock phase can set or reset the latch, if the loop delay is shorter than the pulse width.

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 Fig. 5.13 Sample input and output waveforms for the clocked NOR based SR latch.

Figure 5.14 shows a CMOS implementation of the clocked NOR-based SR latch circuit,
using two AND-OR-INVERT (AOI) gates. The AOI-based implementation results in a
very small transistor count.

Fig. 5.14 AOI-based implementation of the clocked NOR-based SR latch circuit.

The clocked based NAND SR latch can also be implemented, as shown in Fig. 5.15.
The latch is low level sensitive. This means that output changes as per input

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combinations when the clock is active, i.e., CK = "0." For the circuit implementation
of this clocked NAND-based SR latch, OR-AND-INVERT (OAI) structure can be
used.

Fig. 5.15 Gate-level schematic of the clocked NAND SR latch circuit,

with active low inputs.

All NAND based implementation of SR latch is shown in Fig. 5.16. Here, both input
signals and the CK signal are active high. This means latch is set when CK=”1”, S=”1”
and R=”0”. Similarly, the latch will be reset when CK = "1," S = "0," and R = "1." The
latch preserves its state as long as CK = "0". However, this implementation requires
higher transistor count than the active low version shown in Fig. 5.15.

Fig. 5.16 All NAND based SR latch circuit

Clocked JK Latch

All SR latch circuits suffer from the not-allowed state. This problem can be overcome
through a JK latch. Figure 5.17 shows an all-NAND implementation of the JK latch
with active high inputs and its block diagram. The JK latch is commonly called a JK
flip-flop.

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 Fig. 5.17 Gate-level schematic and block diagram of the clocked NAND-based JK latch circuit

When the clock is active, the latch can be set with the input combination (J = '1," K =
"0"), and it can be reset with the input combination (J = "0," K = "1"). If both inputs are
equal to logic "0," the latch preserves its current state. If, both inputs are equal to " 1 "
during the active clock phase, the latch simply switches its state due to feedback. The
JK latch does not have a not-allowed input combination. The JK latch holds its state
when the clock is inactive (CK = "0"). The operation of the clocked JK latch is
summarized in Table 5.3.

Table 5.3 Truth table of JK latch

Figure 5.18 shows NOR-based clocked JK latch, and CMOS realization of it. The AOI-
based implementation results in a relatively low transistor count, and hence, a more
compact circuit compared to the all-NAND realization shown in Fig. 5.17.

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In JK latch, if both inputs are equal to logic " 1 " during the active phase of the clock
pulse, the output of the circuit will oscillate (toggle) continuously until either the clock
becomes inactive (goes to zero), or one of the input signals goes to zero, which is a
limitation of JK latch. To prevent continuous toggling, the clock pulse width must be
made smaller than the input-to-output propagation delay. However, this is difficult to
implement practically.

Master-Slave Flip-Flop

Two latch stages in a cascaded configuration can prevent most of the timing limitations
of clocked latch circuits. The principle is that the two-cascaded stages are activated with
opposite clock phases. This configuration is called the master-slave flip-flop.

The Master-Slave Flip-Flop is basically two JK flip-flops connected together in a series

configuration with the Slave having an inverted clock pulse. The outputs from Q and
Q from the "Slave" flip-flop are fed back to the inputs of the "Master" with the outputs
of the "Master" flip-flop being connected to the two inputs of the "Slave" flip-flop. This
feedback configuration from the slave's output to the master's input gives the
characteristic toggle of the JK flip-flop as shown in Fig. 5.19.

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 Fig. 5.19 Master Slave JK flip flop based on all NAND

The input signals J and K are connected to the "master" flip-flop which "locks" the
input condition while the clock (Clk) input is at logic level "1". As the clock input of
the "slave" flip-flop is the inverse (complement) of the "master" clock input, the "slave"
flip-flop does not toggle. The outputs from the "master" flip-flop are only "seen" by the
"slave" flip-flop when the clock input goes to logic level "0". When the clock is "LOW",
the outputs from the "master" flip-flop are latched and any additional changes to its
inputs are ignored. The gated "slave" flip-flop now responds to the state of its inputs
passed over by the "master" section. Because the master and the slave stages are
decoupled from each other, the circuit allows for toggling when J = K = "1," but it
eliminates the possibility of uncontrolled oscillations since only one stage is active at
any given time.

Figure 5.20 shows waveforms of the master-slave flip-flop. When the clock pulse is
high, a narrow spike or glitch in one of the inputs, cause an unwanted state transition,
which will then be propagated into the slave stage during the following phase. This
problem can be eliminated by using an edge-triggered master-slave flip-flop. A NOR-
based realization for the master-slave JK flip-flop circuit is shown in Fig. 5.21.

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 Fig. 5.20 Sample input and output waveforms of the master-slave JK flip-flop.

Fig. 5.21 NOR-based realization of the JK master-slave flip-flop.

5.5 CMOS D-latch and Edge-triggered Flip-flop

The D-latch circuit is shown in Fig. 5.22. The gate-level representation of the D-latch
can be obtained by modifying the clocked NOR-based SR latch circuit. Here, single D
input is directly connected to the S input of the latch. The inverted input ( D ) is
connected to the R input of the latch. Therefore output Q follows D when the clock is
active, i.e., for CK = "1." When the clock signal goes to zero, the output will simply
preserve its state.

The D-latch can be used in digital circuit design, for temporary storage of data or as a
delay element. Figure 5.23 shows a basic two-inverter loop and two CMOS

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transmission gate (TG) switches. The TG at the input is activated by the CK signal,
whereas the TG in the inverter loop is activated by the inverse of the CK signal ( CK ).
The operation of the CMOS D-latch circuit can be better understood by replacing the
CMOS transmission gates with simple switches, as shown in Fig. 5.24. A timing
diagram accompanying this figure shows the time intervals during which the input and
the output signals should be valid (unshaded).

Fig. 5.22 Gate-level schematic and the block diagram of the D-latch.

Fig. 5.23 CMOS implementation of the D-latch

Here, setup time is the minimum amount of time the data signal should be held steady
before the clock event so that the data are reliably sampled by the clock. Similarly, hold
time is the minimum amount of time the data signal should be held steady after the
clock event so that the data are reliably sampled. Once the inverter loop is completed
by closing the loop switch, the output will preserve its valid level. The metastability in
flip-flops can be avoided by ensuring that the data and control inputs are held valid and
constant for specified periods before and after the clock pulse, called the setup time and
the hold time respectively.

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The D-latch shown in Fig. 5.23 is transparent, when the clock is high. The transparency
makes the application of this D-latch unsuitable for counters and some data storage
implementations. Figure 5.25 shows a different version of the CMOS D-latch. The
circuit contains two tri-state inverters, driven by the clock signal and its inverse. The
basic operation is identical to Fig. 5.23. The first tri-state inverter acts as the input
switch, accepting the input signal when the clock is high. At this time, the second tri-
state inverter is at its high-impedance state, and the output Q is following the input
signal. When the clock goes low, the input buffer becomes inactive, and the second tri-
state inverter completes the two-inverter loop, which preserves its state until the next
clock pulse.

Fig. 5.24 Schematic view and the timing diagram of the CMOS D latch
circuit, showing the setup time and the hold time.

Fig. 5.25 CMOS implementation of the D-latch (version 2).

Master-Slave D flip-flop

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The master-slave flip-flop is constructed by cascading two D-latch circuits as shown in
Fig. 5.26. The first stage (master) is driven by the clock signal, while the second stage
(slave) is driven by the inverted clock signal. Thus, the master stage is positive level-
sensitive, while the slave stage is negative level-sensitive. When the clock is, high, the
master stage follows the D input while the slave stage holds the previous value. The
master latch stores the value of D when the clock changes from logic "1" to logic "0".
At the same time, the slave latch becomes transparent, passing the stored master value
Qm to the output of the slave stage, Qs. The input cannot affect the output because the
master stage is disconnected from the D input. When the clock changes again from
logic 0" to 1," the slave latch locks in the master latch output and the master stage starts
sampling the input again. Thus, this circuit is a negative edge-triggered D flip-flop.

Fig. 5.26 CMOS negative (falling) edge-triggered master-slave D flip-flop.

Edge Triggered D flip-flop

Figure 5.27 shows implementation of edge-triggered D flip-flop. It consists of six 3-

input NAND gates. The operation can be understood through timing diagram shown in
Fig. 5.28. Initially, all the signal values except for S are 0, i.e., (S, R, CK, D) = (1, 0, 0,
0), and Q = 0. In the second phase, both D and R switch to 1, i.e., (S, R, CK, D) = (1,
0, 1, 1), but no change in Q occurs and the Q value remains at 0. In the third phase, if
CK goes to high, i.e., (S, R, CK, D) = (1, 1, 1, 1), the output of gate 2 switches to 0,
which sets the output of the last stage SR latch to 1. Thus, the output of this D flip-flop
switches to 1 at the positive-going edge of the clock signal, CK. In the ninth phase of

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the waveform diagram, the Q output is not affected by the negative-going edge of CK,
nor by other signal changes.

Fig. 5.27 NAND-based positive edge-triggered D flip-flop.

Fig. 5.28 Timing diagram of positive edge-triggered D flip-flop.

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Exercise

Brief Questions:

1. Differentiate Sequential and Combinational logic circuits.

2. Classify various logic circuits.
3. Draw depletion load nMOS SR latch based on NOR gates.
4. Draw OAI implementation of clocked NAND based SR latch.
5. What is the limitation of SR latch?
6. What is the limitation of clocked JK latch?
7. Define Set up time and Hold time.
8. Draw CMOS implementation of D latch using TG.

Detailed Questions:

1. Explain behavior of bistable elements.

2. Describe NAND based SR latch using gate level schematic, truth table and
CMOS implementation.
3. Discuss clocked NOR based SR latch using gate level schematic, truth table and
AOI implementation.
4. Discuss clocked JK latch in detail.
5. Describe master slave JK flip-flop with necessary waveforms.
6. Explain edge triggered D flip-flop.

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