a Low Noise, Matched

Dual PNP Transistor

MAT03
FEATURES PIN CONNECTION
Dual Matched PNP Transistor TO-78
Low Offset Voltage: 100 mV max (H Suffix)
Low Noise: 1 nV/√Hz @ 1 kHz max
High Gain: 100 min
High Gain Bandwidth: 190 MHz typ
Tight Gain Matching: 3% max
Excellent Logarithmic Conformance: rBE . 0.3 V typ
Available in Die Form

GENERAL DESCRIPTION Each transistor is individually tested to data sheet specifications.

The MAT03 dual monolithic PNP transistor offers excellent Device performance is guaranteed at 25°C and over the extended
parametric matching and high frequency performance. Low industrial and military temperature ranges. To insure the long-
noise characteristics (1 nV/√Hz max @ 1 kHz), high bandwidth term stability of the matching parameters, internal protection
(190 MHz typical), and low offset voltage (100 µV max), makes diodes across the base-emitter junction clamp any reverse base-
the MAT03 an excellent choice for demanding preamplifier ap- emitter junction potential. This prevents a base-emitter break-
plications. Tight current gain matching (3% max mismatch) and down condition which can result in degradation of gain and
high current gain (100 min), over a wide range of collector cur- matching performance due to excessive breakdown current.
rent, makes the MAT03 an excellent choice for current mirrors.
A low value of bulk resistance (typically 0.3 Ω) also makes the
MAT03 an ideal component for applications requiring accurate
logarithmic conformance.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
MAT03–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ TA = +258C, unless otherwise noted.)
MAT03A MAT03E MAT03F
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units
1
Current Gain hFE VCB = 0 V, –36 V
IC = 1 mA 100 165 100 165 80 165
IC = 100 µA 90 150 90 150 70 150
IC = 10 µA 80 120 80 120 60 120
Current Gain Matching 2 DhFE IC = 100 µA,VCB = 0 V 0.5 3 0.5 3 0.5 6 %
Offset Voltage3 VOS VCB = 0 V, IC = 100 µA 40 100 40 100 40 200 µV
Offset Voltage Change DVOS/DVCB IC = 100 µA
vs. Collector Voltage VCB1 = 0 V 11 150 11 150 11 200 µV
VCB2 = –36 V 11 150 11 150 11 200 µV
Offset Voltage Change DVOS/DIC VCB = 0 V 12 50 12 50 12 75 µV
vs. Collector Current IC1 = 10 µA, IC2 = 1 mA 12 50 12 50 12 75 µV
Bulk Resistance rBE VCB = 0 V 0.3 0.75 0.3 0.75 0.3 0.75 Ω
10 µA ≤ IC ≤ 1 mA 0.3 0.75 0.3 0.75 0.3 0.75 Ω
Offset Current IOS IC = 100 µA, VCB = 0 V 6 35 6 35 6 45 nA
Collector-Base
Leakage Current ICB0 VCB = –36 V = VMAX 50 200 50 200 50 400 pA
Noise Voltage Density 4 eN IC = 1 mA, VCB = 0
fO = 10 Hz 0.8 2 0.8 0.8 nV/÷ Hz
fO = 100 Hz 0.7 1 0.7 0.7 nV/÷ Hz
fO = 1 kHz 0.7 1 0.7 0.7 nV/÷ Hz
fO = 10 kHz 0.7 1 0.7 0.7 nV/÷ Hz
Collector Saturation
Voltage VCE(SAT) IC = 1 mA, IB = 100 µA 0.025 0.1 0.025 0.1 0.025 0.1 V

ELECTRICAL CHARACTERISTICS (at –558C ≤ T ≤ +1258C, unless otherwise noted.) A

MAT03A
Parameter Symbol Conditions Min Typ Max Units
Current Gain hFE VCB = 0 V, –36 V
IC = 1 mA 70 110
IC = 100 µA 60 100
IC = 10 µA 50 85
Offset Voltage VOS IC = 100 µA, VCB = 0 V 40 150 µV
Offset Voltage Drift5 TCVOS IC = 100 µA, VCB = 0 V 0.3 0.5 µV/°C
Offset Current IOS IC = 100 µA, VCB = 0 V 15 85 nA
Breakdown Voltage BVCEO 36 54 V

ELECTRICAL CHARACTERISTICS (at –408C ≤ T ≤ +858C, unless otherwise noted.) A

MAT03E MAT03F
Parameter Symbol Conditions Min Typ Max Min Typ Max Units

Current Gain hFE VCB = 0 V, –36 V

IC = 1 mA 70 120 60 120
IC = 100 µA 60 105 50 105
IC = 10 µA 50 90 40 90
Offset Voltage VOS IC = 100 µA, VCB = 0 V 30 135 30 265 µV
Offset Voltage Drift5 TCVOS IC = 100 µA, VCB = 0 V 0.3 0.5 0.3 1.0 µV/°C
Offset Current IOS IC = 100 µA, VCB = 0 V 10 85 10 200 nA
Breakdown Voltage BVCEO 36 36 V

NOTES
1
Current gain is measured at collector-base voltages (V CB) swept from 0 to V MAX at indicated collector current. Typicals are measured at V CB = 0 V.
100 ( ∆I B ) hFE (min )
2Current gain matching (∆hFE) is defined as: ∆hFE =
.
IC
KT  I C1 
3Offset voltage is defined as: V OS = VBE1 – VBE2, where VOS is the differential voltage for I C1 = IC2: VOS = VBE1 – VBE2 = q In I .
4
 C2 
Sample tested. Noise tested and specified as equivalent input voltage for each transistor.
5
Guaranteed by V OS test (TCVOS = VOS/T for VOS ! VBE) where T = 298°K for TA = 25°C.
Specifications subject to change without notice.

–2– REV. B
 MAT03
WAFER TEST LIMITS (at 258C, unless otherwise noted.)
MAT03N
Parameter Symbol Conditions Limits Units

Breakdown Voltage BVCEO 36 V min

Offset Voltage VOS IC = 100 µA, VCB = 0 V 200 µV max
10 µA ≤ IC ≤ 1 mA 200 µV max
Current Gain hFE IC = 1 mA, VCB = 0 V, –36 V 80 min
IC = 10 µA, VCB = 0 V, –36 V 60 min
Current Gain Match ∆hFE IC = 100 µA, VCB = 0 V 6 % max
Offset Voltage Change vs. VCB ∆VOS/∆VCB VCB1 = 0 V, IC = 100 µA 200 µV max
VCB2 = –36 V 200 µV max
Offset Voltage Change ∆VOS/∆IC VCB = 0 75 µV max
vs. Collector Current IC1 = 10 µA, IC2 = 1 mA 75 µV max
Bulk Resistance rBE 10 µA ≤ IC ≤ 1 mA 0.75 Ω max
Collector Saturation Voltage VCE (SAT) IC = 1 mA, IB = 100 µA 0.1 V max
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

DICE CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS 1
1. COLLECTOR (1 ) Collector-Base Voltage (BVCBO) . . . . . . . . . . . . . . . . . . . . 36 V
2. BASE (1 ) Collector-Emitter Voltage (BVCEO) . . . . . . . . . . . . . . . . . . 36 V
3. EMITTER (1 ) Collector-Collector Voltage (BVCC) . . . . . . . . . . . . . . . . . . 36 V
4. COLLECTOR (2) Emitter-Emitter Voltage (BVEE) . . . . . . . . . . . . . . . . . . . . . 36 V
5. BASE (2) Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
6. EMITTER (2 )
Emitter Current (IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
SUBSTRATE CAN BE Total Power Dissipation
CONNECTED TO V– OR Ambient Temperature ≤ 70°C2 . . . . . . . . . . . . . . . . 500 mW
FLOATED Operating Temperature Range
MAT03A . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
MAT03E/F . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Operating Junction Temperature . . . . . . . . . . –55°C to +150°C
ORDERING GUIDE1 Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
VOS max Temperature Package Junction Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Model (TA = +258C) Range Option
NOTES
MAT03AH2 100 µV
1
–55°C to +125°C TO-78 Absolute maximum ratings apply to both DICE and packaged devices.
2
MAT03EH 100 µV –40°C to +85°C TO-78 Rating applies to TO-78 not using a heat sink, and LCC; devices in free air only. For
TO-78, derate linearly at 6.3 mW/°C above 70°C ambient temperature; for LCC,
MAT03FH 200 µV –40°C to +85°C TO-78 derate at 7.8 mW/°C.
NOTES
1
Burn-in is available on industrial temperature range parts.
2
For devices processed in total compliance to MIL-STD-883, add/883 after part
number. Consult factory for 883 data sheet.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the MAT03 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B –3–
MAT03

Figure 1. Current Gain vs. Figure 2. Current Gain Figure 3. Gain Bandwidth vs.
Collector Current vs. Temperature Collector Current

Figure 4. Base-Emitter Voltage Figure 5. Small-Signal Input Resistance Figure 6. Small Signal Output Con-
vs. Collector Current (hie) vs. Collector Current ductance (hoe) vs. Collector Current

–4– REV. B
 MAT03

Figure 7. Saturation Voltage Figure 8. Noise Voltage Density Figure 9. Noise Voltage Density
vs. Collector Current vs. Frequency

Figure 10. Total Noise vs. Collector Current Figure 11. Collector-Base Capacitance vs. VCB

REV. B –5–
MAT03

Figure 12. SPICE or SABER Model

APPLICATIONS INFORMATION MAT03 NOISE MEASUREMENT

MAT03 MODELS All resistive components (Johnson noise, en2 = 4kTBR, or en =
The MAT03 model (Figure 12) includes parasitic diodes D3 0.13√R nV/√Hz, where R is in kΩ) and semiconductor junctions
through D6. D1 and D2 are internal protection diodes which (Shot noise, caused by current flowing through a junction, pro-
prevent zenering of the base-emitter junctions. duces voltage noise in series impedances such as transistor-
collector load resistors, In = 0.566 √I pA/√Hz where I is in µA)
The analysis programs, SPICE and SABER, are primarily used
contribute to the system input noise.
in evaluating the functional performance of systems. The mod-
els are provided only as an aid in utilizing these simulation Figure 13 illustrates a technique for measuring the equivalent
programs. input noise voltage of the MAT03. 1 mA of stage current is used

Figure 13. MAT03 Voltage Noise Measurement Circuit

–6– REV. B
 MAT03
to bias each side of the differential pair. The 5 kΩ collector re- measurement circuit must be thermally isolated. Effects of extrane-
sistors noise contribution is insignificant compared to the volt- ous noise sources must also be eliminated by totally shielding
age noise of the MAT03. Since noise in the signal path is the circuit.
referred back to the input, this voltage noise is attenuated by the
gain of the circuit. Consequently, the noise contribution of the SUPER LOW NOISE AMPLIFIER
collector load resistors is only 0.048 nV/√Hz. This is consider- The circuit in Figure 14a is a super low noise amplifier with
ably less than the typical 0.8 nV/√Hz input noise voltage of the equivalent input voltage noise of 0.32 nV/√Hz. By paralleling
MAT03 transistor. three MAT03 matched pairs, a further reduction of amplifier
noise is attained by a reduction of the base spreading resistance
The noise contribution of the OP27 gain stages is also negligible
by a factor of 3, and consequently the noise by √3. Additionally,
due to the gain in the signal path. The op amp stages amplify
the shot noise contribution is reduced by maintaining a high col-
the input referred noise of the transistors to increase the signal
lector current (2 mA/device) which reduces the dynamic emitter
strength to allow the noise spectral density (ein × 10000) to be
resistance and decreases voltage noise. The voltage noise is in-
measured with a spectrum analyzer. And, since we assume
versely proportional to the square root of the stage current, and
equal noise contributions from each transistor in the MAT03,
current noise increases proportionally to the square root of the
the output is divided by √2 to determine a single transistor’s
stage current. Accordingly, this amplifier capitalizes on voltage
input noise.
noise reduction techniques at the expense of increasing the cur-
Air currents cause small temperature changes that can appear rent noise. However, high current noise is not usually important
as low frequency noise. To eliminate this noise source, the when dealing with low impedance sources.

Figure 14a. Super Low Noise Amplifier

REV. B –7–
MAT03
This amplifier exhibits excellent full power ac performance, and the VBE of a silicon transistor is predictable and constant (to
0.08% THD into a 600 Ω load, making it suitable for exacting a few percent) over a wide temperature range. The voltage differ-
audio applications (see Figure 14b). ence, approximately 1 V, is dropped across the 250 Ω resistor
which produces a temperature stabilized emitter current.

CURRENT SOURCES
A fundamental requirement for accurate current mirrors and ac-
tive load stages is matched transistor components. Due to the
excellent VBE matching (the voltage difference between VBE’s
required to equalize collector current) and gain matching, the
MAT03 can be used to implement a variety of standard current
mirrors that can source current into a load such as an amplifier
stage. The advantages of current loads in amplifiers versus resis-
tors is an increase of voltage gain due to higher impedances,
larger signal range, and in many applications a wider signal
bandwidth.
Figure 16 illustrates a cascode current mirror consisting of two
MAT03 transistor pairs.
The cascode current source has a common base transistor in se-
Figure 14b. Super Low Noise Amplifier—Total ries with the output which causes an increase in output imped-
Harmonic Distortion ance of the current source since VCE stays relatively constant.
High frequency characteristics are improved due to a reduction
LOW NOISE MICROPHONE PREAMPLIFIER
of Miller capacitance. The small-signal output impedance can
Figure 15 shows a microphone preamplifier that consists of a be determined by consulting “hOF vs. Collector Current” typical
MAT03 and a low noise op amp. The input stage operates at a graph. Typical output impedance levels approach the perfor-
relatively high quiescent current of 2 mA per side, which reduces mance of a perfect current source.
the MAT03 transistor’s voltage noise. The 1/ƒ corner is less than Considering a typical collector current of 100 µA, we have:
1 Hz. Total harmonic distortion is under 0.005% for a 10 V p-p 1
signal from 20 Hz to 20 kHz. The preamp gain is 100, but can be roQ3 = 1.0 µMHOS = 1 MΩ
modified by varying R5 or R6 (VOUT/VIN = R5/R6 + 1).
A total input stage emitter current of 4 mA is provided by Q2.
The constant current in Q2 is set by using the forward voltage of
a GaAsP LED as a reference. The difference between this voltage

Figure 15. Low Noise Microphone Preamplifier

–8– REV. B
 MAT03
Q2 and Q3 are in series and operate at the same current levels so Since Q2 buffers Q3, both transistors in the MAT03, Q1 and Q3,
the total output impedance is: maintain the same collector current. D2 and D3 form a Baker
RO = hFE roQ3 @ (160)(1 MΩ) = 160 MΩ. clamp which prevents Q2 from turning off, thereby improving
the switching speed of the current mirror. The feedback serves
to increase the output impedance and improves accuracy by re-
ducing the base-width modulation which occurs with varying
collector-emitter voltages. Accuracy and linearity performance
of the current pump is summarized in Figure 19.

Figure 16. Cascode Current Source

Figure 17a. Current Matching Circuit

CURRENT MATCHING
The objective of current source or mirror design is generation of
currents that are either matched or must maintain a constant ra-
tio. However, mismatch of base-emitter voltages cause output
current errors. Consider the example of Figure 17a. If the resis-
tors and transistors are equal and the collector voltages are the
same, the collector currents will match precisely. Investigating
the current-matching errors resulting from a nonzero VOS, we
define ∆IC as the current error between the two transistors.
Graph 17b describes the relationship of current matching errors
versus offset voltage for a specified average current IC. Note that
since the relative error between the currents is exponentially pro-
portional to the offset voltage, tight matching is required to de-
sign high accuracy current sources. For example, if the offset
voltage is 5 mV at 100 µA collector current, the current match-
ing error would be 20%. Additionally, temperature effects such
as offset drift (3 µV/°C per mV of VOS) will degrade performance
Figure 17b. Current Matching Accuracy %
if Q1 and Q2 are not well matched.
vs. Offset Voltage
DIGITALLY PROGRAMMABLE BIPOLAR CURRENT
PUMP
The circuit of Figure 18 is a digitally programmable current
pump. The current pump incorporates a DAC08, and a fast
Wilson current source using the MAT03. Examining Figure 18,
the DAC08 is set for 2 mA full-scale range so that bipolar cur-
rent operation of ± 2 mA is achieved. The Wilson current mirror
maintains linearity within the LSB range of the 8-bit DAC08
(± 2 mA/256 = 15.6 µA resolution) as seen in Figure 19. A
negative feedback path established by Q2 regulates the collector
current so that it matches the reference current programmed by
the DAC08.
Collector-emitter voltages across both Q1 and Q3 are matched
by D1, with Q3’s collector-emitter voltage remaining constant,
independent of the voltage across the current source output.

Figure 18. Digitally Programmable Bipolar Current Pump

REV. B –9–
MAT03
The full-scale output of the DAC08, IOUT, is a linear function
of IREF

256 256
IFR = × IREF, and IOUT + IOUT = IREF
256 256

The current mirror output is IOUT – IOUT = 1, so that if

IREF = 2 mA:
I = 2 IOUT – 1.992 mA

 Input Code 
= 2  256  (2 mA) – 1.992 mA.
 

DIGITAL CURRENT PUMP CODING

Figure 19. Digitally Programmable Current
Pump—INL Error as Digital Code Digital Input
B1 . . . B8 Output Current
FULL RANGE 1111 1111 I = 1.992 mA
HALF-RANGE 1000 0000 I = 0.008 mA
ZERO-SCALE 0000 0000 I = –1.992 mA

–10– REV. B
 MAT03
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

TO-78 Metal Can

REFERENCE PLANE
0.750 (19.05)
0.185 (4.70) 0.500 (12.70)
0.165 (4.19) 0.250 (6.35) MIN
0.100 (2.54) BSC
0.050 (1.27) MAX 0.160 (4.06)
0.110 (2.79)
0.370 (9.40) 4
0.335 (8.51)
0.335 (8.51)
0.305 (7.75)
5 0.045 (1.14)
0.200 0.027 (0.69)
(5.08) 3 6
BSC
2
1
0.019 (0.48) 0.100
(2.54)
0.016 (0.41) BSC
0.040 (1.02) MAX 0.034 (0.86)
0.021 (0.53) 0.027 (0.69)
0.045 (1.14) 0.016 (0.41)
0.010 (0.25) 45° BSC
BASE & SEATING PLANE

REV. B –11–
–12–
PRINTED IN U.S.A. 000000000