Infineon TC39x DataSheet v01 00 en

32-Bit
Microcontroller
TC39x
32-Bit Single-Chip Microcontroller
BC/BD-Step
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1, 2019-09
Microcontrollers
OPEN MARKET VERSION
Edition 2019-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2019 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
OPEN MARKET VERSION

TC39x BC/BD-Step
Revision History
Page or Item Subjects (major changes since previous revision)
V 1.1, 2019-09
The history is documented in the last chapter
Data Sheet 3 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Trademarks of Infineon Technologies AG

AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet 4 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table of Contents
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pin Definition and Functions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 LFBGA-516 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 LFBGA-292 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
2.3 LFBGA-292 ADAS Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
2.4 Pin Position Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
2.5 Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
3 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
3.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
3.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
3.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
3.5 5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
3.6 High performance LVDS Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
3.7 VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
3.8 DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
3.9 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
3.10 Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
3.11 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
3.12 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
3.12.1 Calculating the 1.25 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
3.13 Power Supply Infrastructure and Supply Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
3.13.1 Supply Ramp-up and Ramp-down Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
3.13.1.1 Single Supply mode (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
3.13.1.2 Single Supply mode (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
3.13.1.3 External Supply mode (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
3.13.1.4 External Supply mode (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
3.14 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
3.15 EVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
3.16 System Phase Locked Loop (SYS_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
3.17 Peripheral Phase Locked Loop (PER_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
3.18 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
3.19 JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
3.20 DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
3.21 ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
3.22 QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
3.23 MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
3.24 Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
3.24.1 ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
3.24.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . 488
3.24.3 ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
3.24.4 ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
3.24.5 ETH RGMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
3.25 E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
3.26 HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
3.27 Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
3.28 SDMMC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
3.29 FSP Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Data Sheet 5 V 1.1, 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
3.30 Radar Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

3.31 EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
3.31.1 BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
3.31.2 EBU Asynchronous Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
3.31.3 EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
3.31.4 EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
3.32 Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
3.33 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
3.34 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
3.34.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
4 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
4.1 Changes from Version 0.4 to Version 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
4.4 Changes from Version 1.0 to Version 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Data Sheet 6 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Summary of Features
1 Summary of Features
The TC39x product family has the following features:
• High Performance Microcontroller with six CPU cores
• Six 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having the following features:
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– up to 300 MHz operation at full temperature range
– up to 240/96 Kbyte Data Scratch-Pad RAM (DSPR)
– up to 64 Kbyte Instruction Scratch-Pad RAM (PSPR)
– up to 64 Kbyte Data RAM (DLMU)
– 32 Kbyte Instruction Cache (ICACHE)
– 16 Kbyte Data Cache (DCACHE)
• Lockstepped shadow cores for four TC1.6.2P
• Multiple on-chip memories
– All embedded NVM and SRAM are ECC protected
– up to 16 Mbyte Program Flash Memory (PFLASH)
– up to 1 Mbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 768 Kbyte Memory (LMU)
– BootROM (BROM)
• 128-Channel DMA Controller with safe data transfer
• Sophisticated interrupt system (ECC protected)
• High performance on-chip bus structure
– 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– SRI to SPB bus bridges (SFI Bridge)
• Optional Hardware Security Module (HSM) on some variants
• Safety Management Unit (SMU) handling safety monitor alarms
• Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
• Hardware I/O Monitor (IOM) for checking of digital I/O
• Versatile On-chip Peripheral Units
– 8 Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and
J2602) up to 50 MBaud
– 6 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s
– 2 High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s
– 4 serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
– 3 MCMCAN Modules with 4 CAN nodes for high efficiency data handling via FIFO buffering
– 25 Single Edge Nibble Transmission (SENT) channels for connection to sensors
– 2 FlexRayTM module with 2 channels (E-Ray) supporting V2.1
Data Sheet 7 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Summary of Features
– One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality
to realize autonomous and complex Input/Output management
– One Capture / Compare 6 module (Two kernels CCU60 and CCU61)
– One General Purpose 12 Timer Unit (GPT120)
– 4 channel Peripheral Sensor Interface conforming to V1.3 (PSI5)
– 1 Peripheral Sensor Interface with Serial PHY (PSI5-S)
– 2 Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1
– 1 IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)
– 1 external Bus interface (EBU)
• Versatile Successive Approximation ADC (VADC)
– Cluster of 20 independent ADC kernels
– Input voltage range from 0 V to 5.5V (ADC supply)
• Delta-Sigma ADC (DSADC)
– 14 channels
• Digital programmable I/O ports
• On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
• multi-core debugging, real time tracing, and calibration
• four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
• Power Management System and on-chip regulators
• Clock Generation Unit with System PLL and Peripheral PLL
• Embedded Voltage Regulator
Data Sheet 8 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering
code identifies:
• The derivative itself, i.e. its function set, the temperature range, and the supply voltage
• The package and the type of delivery.
Table 1-1 Platform Feature Overview

Feature TC39x
CPUs Type TC1.6.2
Cores / Checker Cores 6/4
Max. Freq. 300 MHz
Cache per CPU Program 32 KB
Data 16 KB
SRAM per CPU PSPR 64 KB
DSPR 240 KB for CPU0,1/ 96 KB else
DLMU 64 KB
SRAM global LMU 768 KB
DAM 128 KB
Extension Memory TCM 2 MB
XCM 2 MB
XTM 16 KB
Program Flash Size 16 MB
Banks 5 x 3 MB, 1 x 1 MB
Data Flash Size (single-ended) 1 MB
DMA Channels 128
CONVCTRL Modules 1
EVADC Primary Groups/Channels 8 / 64
Secondary Groups/Channels 4 / 64
Fast Compare Channels 8
EDSADC Channels 14
Data Sheet 9 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Summary of Features
Table 1-1 Platform Feature Overview (cont’d)

Feature TC39x
GTM Clusters 12 (5 @ 200MHz, 7 @ 100MHz)
TIM (8 ch) 8
TOM (16 ch) 6
ATOM (8 ch) 12
MCS (8 ch) 10
CMU / ICM 1/1
PSM 3
1)
TBU channels 4 (TBU0-3)
SPE 6
CMP / MON 1/1
BRC / DPLL 1/1
CDTM modules 6
DTM modules 24 (10 on TOM, 14 on ATOM)
Timer GPT12 1
CCU6 1
STM Modules 6
FlexRay Modules 2
Channels 2
CAN Modules 3
Nodes 3x4
of which support TT-CAN 1
QSPI Modules 6
HSCI Channels 2
ASCLIN Modules 12
I2C Interfaces 2
SENT Channels 25
PSI5 Modules 4
PSI5-S Modules 1
HSSL Channels 2
MSC Channels 4
EBU External Bus 1
SDMMC eMMC/SD Interface 1
Ethernet (10/100Mbit/1Gbit) Modules 1
FCE Modules 1
Safety Support SMU yes
IOM yes
SPU Modules 2
Data Sheet 10 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Summary of Features
Table 1-1 Platform Feature Overview (cont’d)

Feature TC39x
RIF Modules 2
HSDPM Modules 1
Security HSM+ 1
Debug OCDS yes
MCDS yes
miniMCDS no
miniMCDS TRAM - KB
AGBT yes
Low Power Features Standby RAM 2
SCR yes
Packages Type LFBGA-516 / LFBGA-292
I/O Type 5 V CMOS / 3.3 V CMOS / LVDS
Tambient Range −40 … +150°C

1) TBU3 has special purpose as angle clock.
Data Sheet 11 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Pin Definition and Functions:
2 Pin Definition and Functions:

The following figures are showing the TC39x Logic Symbols for the package variants:
• LFBGA-516 (Figure 2-1)
• LFBGA-292 (Figure 2-2)
• LFBGA-292 ADAS feature set (Figure 2-3)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A NC1 VEXT NC NC P10.15 P10.13 P10.11 NC NC NC P13.15 P13.13 P13.11 P13.9 P13.7 P13.5 NC P14.15 P14.13 P14.11 NC P15.15 P15.13 P15.11 NC NC NC NC VDDP3 VSS A
B NC VSS VEXT NC P10.14 NC P10.10 P10.9 NC NC P13.14 P13.12 P13.10 NC P13.6 P13.4 NC P14.14 P14.12 NC NC P15.14 P15.12 P15.10 NC NC NC VDDP3 VSS VSS B
C NC NC NC NC C
D NC NC NC NC D
E NC NC NC NC E
F P02.13 P02.12 NC1 VEXT P10.7 P10.6 P10.2 P10.3 P10.0 P11.11 P11.9 P11.2 P13.3 P13.1 P14.8 P14.5 P14.1 P15.6 P15.4 P15.1 VDDP3 VSS NC NC F
G P02.15 P02.14 P02.0 VSS VEXT P10.8 P10.5 P10.4 P10.1 P11.12 P11.10 P11.3 P13.2 P13.0 P14.6 P14.3 P14.4 P14.0 P15.3 VDDP3 VSS P15.0 NC NC G
H NC NC P02.2 P02.1 P15.2 P20.14 VSS VSS H
J NC P01.0 P02.4 P02.3 VSS VFLEX P11.15 P11.14 P11.5 P11.6 P11.4 P14.10 P14.9 P14.7 P15.8 P15.7 VDD VSS P20.12 P20.13 VEBU VEBU J
K P01.1 P01.2 P02.6 P02.5 P02.9 VSS P11.13 P11.8 P11.7 P11.1 P11.0 P12.1 P12.0 P14.2 P15.5 VDD VSS P20.9 P20.10 P20.11 P24.14 P24.15 K
L P01.8 P01.9 P02.8 P02.7 P02.11 P02.10 ESR0 P20.6 P20.7 P20.8 P24.12 P24.13 L
VDDSB
M P01.11 P01.10 P00.0 P00.1 P01.4 P01.3 (VDD) VSS DAPE2 DAPE1 VSS VDD ESR1 PORST P20.1 P20.3 P24.10 P24.11 M
VDDSB
P21.7 / P21.6 / N
N P01.13 P01.12 P00.2 P00.3 P01.6 P01.5 (VDD) VSS VSS VSS VSS VDD P20.2 P20.0 P24.8 P24.9
TDO TDI
P P01.15 P01.14 P00.4 P00.5 P00.6 P01.7 VSS VSS VSS VSS VSS VSS TCK P21.1 P21.3 P21.5 P24.6 P24.7 P
AGBTC
R NC NC P00.7 P00.9 P00.8 P00.10 LKP VSS VSS VSS VSS VSS VSS DAPE0 TMS P21.0 P21.2 P21.4 P24.4 P24.5 R
(VSS)
AGBTC AGBTE
T NC P00.13 P00.11 P00.12 AN43 AN42 LKN VSS VSS VSS VSS VSS VSS RR P22.10 P22.11 TRST VSS P24.2 P24.3 T
(VSS) (VSS)
U P00.15 P00.14 AN46 AN47 AN41 AN40 VSS VSS VSS VSS VSS VSS P22.8 P22.9 XTAL2 XTAL1 P24.0 P24.1 U
AN36 / AN38 / V
V AN72 AN73 AN44 AN45 VDD VSS VSS VSS VSS VDD P22.6 P22.7 VDD VEXT NC1 NC1
P40.6 P40.8
AGBTT AGBTT
AN70 / AN71 / AN39 / AN37 / AN32 / W
W AN34 VDD VSS XN XP VSS VDD P22.4 P22.5 P22.1 P22.0 P25.6 NC
P41.2 P41.3 P40.9 P40.7 P40.4
(VSS) (VSS)
AN68 / AN69 / AN33 / Y

Y AN35 AN31 AN23 P23.7 P23.6 P22.3 P22.2 P25.14 P25.15
P41.0 P41.1 P40.5
AN67 / VAREF VAGND VEVRS AA

AA AN66 AN30 AN22 AN15 AN12 AN6 AN4 AN0 P34.2 P34.4 P33.14 P32.5 VSS P23.5 P23.3 P23.4 P25.12 P25.13
P40.15 2 2 B
AN64 / AN29 / AN28 / AN17 / AB

AB AN65 NC1 AN14 AN9 AN7 AN3 AN1 P34.1 P34.3 P34.5 P33.15 P32.6 P32.7 VSS P23.1 P23.2 P25.10 P25.11
P41.8 P40.14 P40.13 P40.10
AN63 / AN62 / AN27 / AN26 / AC

AC VEXT P23.0 P25.8 P25.9
P41.7 P41.6 P40.3 P40.2
P32.1 /
AN25 / AN24 / AN19 / AN18 / AD
AD AN60 AN61 AN16 AN13 AN11 AN8 AN2 P33.0 P33.2 P33.4 P33.6 P33.8 P33.10 P33.12 VGATE P32.4 VSS VEXT P25.7 P25.5
P40.1 P40.0 P40.12 P40.11
1P
P32.0 /
VAREF VAGND AE
AE AN59 AN58 NC1 AN21 AN20 VSSM VDDM AN10 AN5 P33.1 P33.3 P33.5 P33.7 P33.9 P33.11 P33.13 VGATE P32.2 P32.3 VSS P25.4 P25.3
1 1
1N
AF AN56 AN57 P25.2 P25.1 AF
VAREF VAGND AG
AG P26.0 P25.0
3 3
AH NC NC VEXT VEBU AH
AN54 / AJ
AJ NC NC NC AN52 AN50 AN49 VSSM VDDM VSS VEBU P31.0 P31.2 P31.4 P31.6 P31.8 P31.10 P31.12 P31.14 NC P30.0 P30.2 P30.4 P30.6 P30.8 P30.10 P30.12 P30.14 VSS VEXT
P41.4
AN55 / AK
AK NC1 NC NC AN53 AN51 AN48 VSSM VDDM VSS VEBU P31.1 P31.3 P31.5 P31.7 P31.9 P31.11 P31.13 P31.15 VEBU P30.1 P30.3 P30.5 P30.7 P30.9 P30.11 P30.13 P30.15 VEBU VSS
P41.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TC39xed - (top view)
Figure 2-1 Logic Symbol for the package variant LFBGA-516
Data Sheet 12 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A NC1 VEXT P10.7 P10.6 P10.2 P10.3 P10.0 P11.11 P11.9 P11.2 P13.3 P13.1 P14.8 P14.5 P14.1 P15.6 P15.4 P15.1 VDDP3 VSS A
B P02.0 VSS VEXT P10.8 P10.5 P10.4 P10.1 P11.12 P11.10 P11.3 P13.2 P13.0 P14.6 P14.3 P14.4 P14.0 P15.3 VDDP3 VSS P15.0 B
C P02.2 P02.1 P15.2 P20.14 C
D P02.4 P02.3 VSS VFLEX P11.15 P11.14 P11.5 P11.6 P11.4 P14.10 P14.9 P14.7 P15.8 P15.7 VDD VSS P20.12 P20.13 D
E P02.6 P02.5 P02.9 VSS P11.13 P11.8 P11.7 P11.1 P11.0 P12.1 P12.0 P14.2 P15.5 VDD VSS P20.9 P20.10 P20.11 E
F P02.8 P02.7 P02.11 P02.10 ESR0 P20.6 P20.7 P20.8 F
VDDSB
G P00.0 P00.1 P01.4 P01.3 (VDD) VSS DAPE2 DAPE1 VSS VDD ESR1 PORST P20.1 P20.3 G
VDDSB
P21.7 / P21.6 /
H P00.2 P00.3 P01.6 P01.5 (VDD) VSS VSS VSS VSS VDD P20.2 P20.0 H
TDO TDI
J P00.4 P00.5 P00.6 P01.7 VSS VSS VSS VSS VSS VSS TCK P21.1 P21.3 P21.5 J
AGBTC
K P00.7 P00.9 P00.8 P00.10 LKP VSS VSS VSS VSS VSS VSS DAPE0 TMS P21.0 P21.2 P21.4 K
(VSS)
AGBTC AGBTE
L P00.11 P00.12 AN43 AN42 LKN VSS VSS VSS VSS VSS VSS RR P22.10 P22.11 TRST VSS L
(VSS) (VSS)
M AN46 AN47 AN41 AN40 VSS VSS VSS VSS VSS VSS P22.8 P22.9 XTAL2 XTAL1 M
AN36 / AN38 /
N AN44 AN45 VDD VSS VSS VSS VSS VDD P22.6 P22.7 VDD VEXT N
P40.6 P40.8
AGBTT AGBTT
AN39 / AN37 / AN32 /
P AN34 VDD VSS XN XP VSS VDD P22.4 P22.5 P22.1 P22.0 P
P40.9 P40.7 P40.4
(VSS) (VSS)
AN33 /
R AN35 AN31 AN23 P23.7 P23.6 P22.3 P22.2 R
P40.5
VAREF VAGND VEVRS

T AN30 AN22 AN15 AN12 AN6 AN4 AN0 P34.2 P34.4 P33.14 P32.5 VSS P23.5 P23.3 P23.4 T
2 2 B
AN29 / AN28 / AN17 /

U NC1 AN14 AN9 AN7 AN3 AN1 P34.1 P34.3 P34.5 P33.15 P32.6 P32.7 VSS P23.1 P23.2 U
P40.14 P40.13 P40.10
AN27 / AN26 /
V VEXT P23.0 V
P40.3 P40.2
P32.1 /
AN25 / AN24 / AN19 / AN18 /
W AN16 AN13 AN11 AN8 AN2 P33.0 P33.2 P33.4 P33.6 P33.8 P33.10 P33.12 VGATE P32.4 VSS VEXT W
P40.1 P40.0 P40.12 P40.11
1P
P32.0 /
VAREF VAGND
Y NC1 AN21 AN20 VSSM VDDM AN10 AN5 P33.1 P33.3 P33.5 P33.7 P33.9 P33.11 P33.13 VGATE P32.2 P32.3 VSS Y
1 1
1N
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TC39xed - (top view)
Figure 2-2 Logic Symbol for the package variant LFBGA-292
Data Sheet 13 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P51_1
A NC1 VEXT NC P51_9 P51_7 P51_5 P51_3 P51_1 P11.11 P11.9 P11.2 P14.8 P14.5 P14.1 P15.6 P15.4 P15.1 VDDP3 VSS A
1
P51_1
B NC VSS VEXT P51_8 P51_6 P51_4 P51_2 P51_0 P11.12 P11.10 P11.3 P14.6 P14.3 P14.4 P14.0 P15.3 VDDP3 VSS P15.0 B
0
C P50_1 P50_0 P15.2 P20.14 C
D P50_3 P50_2 VSS VFLEX P11.15 P11.14 P11.5 P11.6 P11.4 P14.10 P14.9 P14.7 P15.8 P15.7 VDD VSS P20.12 P20.13 D
E P50_5 P50_4 P10.0 VSS P11.13 P11.8 P11.7 P11.1 P11.0 P12.1 P12.0 P14.2 P15.5 VDD VSS P20.9 P20.10 P20.11 E
F P50_7 P50_6 P10.1 P10.2 ESR0 P20.6 P20.7 P20.8 F
G P50_9 P50_8 P10.3 P10.4 VDD VSS DAPE2 DAPE1 VSS VDD ESR1 PORST P20.1 P20.3 G
P50_1 P50_1 P21.7 / P21.6 /

H P10.5 P10.6 VDD VSS VSS VSS VSS VDD P20.2 P20.0 H
1 0 TDO TDI
J P02.0 P02.1 P10.8 P10.7 VSS VSS VSS VSS VSS VSS TCK P21.1 P21.3 P21.5 J
AGBTC
K P02.2 P02.3 P02.4 P02.5 LKP VSS VSS VSS VSS VSS VSS DAPE0 TMS P21.0 P21.2 P21.4 K
(VSS)
AGBTC AGBTE
L P02.6 P00.0 P02.7 P02.8 LKN VSS VSS VSS VSS VSS VSS RR P22.10 P22.11 TRST VSS L
(VSS) (VSS)
M P00.2 P00.1 P00.3 P00.4 VSS VSS VSS VSS VSS VSS P22.8 P22.9 XTAL2 XTAL1 M
N P00.8 P00.7 P00.6 P00.5 VDD VSS VSS VSS VSS VDD P22.6 P22.7 VDD VEXT N
AGBTT AGBTT
P P00.10 P00.9 AN47 AN45 VDD VSS XN XP VSS VDD P22.4 P22.5 P22.1 P22.0 P
(VSS) (VSS)
AN25 /
R P00.11 P00.12 AN23 P23.7 P23.6 P22.3 P22.2 R
P40.1
VAREF VAGND AN24 / VEVRS

T AN22 AN15 AN12 AN6 AN4 AN0 P34.2 P34.4 P33.14 P32.5 VSS P23.5 P23.3 P23.4 T
2 2 P40.0 B
AN17 /
U AN44 AN46 NC1 AN14 AN9 AN7 AN3 AN1 P34.1 P34.3 P34.5 P33.15 P32.6 P32.7 VSS P23.1 P23.2 U
P40.10
AN39 / AN37 /
V VEXT P23.0 V
P40.9 P40.7
P32.1 /
AN36 / AN38 / AN19 / AN18 /
W AN16 AN13 AN11 AN8 AN2 P33.0 P33.2 P33.4 P33.6 P33.8 P33.10 P33.12 VGATE P32.4 VSS VEXT W
P40.6 P40.8 P40.12 P40.11
1P
P32.0 /
VAREF VAGND
Y NC1 AN21 AN20 VSSM VDDM AN10 AN5 P33.1 P33.3 P33.5 P33.7 P33.9 P33.11 P33.13 VGATE P32.2 P32.3 VSS Y
1 1
1N
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TC39xed_adas - (top view)
Figure 2-3 Logic Symbol for the package variant LFBGA-292 ADAS
Data Sheet 14 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Pin Definition and Functions:LFBGA-516 Package Variant Pin Configuration
2.1 LFBGA-516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions

Ball Symbol Ctrl. Buffer Function
Type
M6 P00.0 I FAST / General-purpose input
GTM_TIM5_IN4_10 PU1 / Mux input channel 4 of TIM module 5
VEXT /
GTM_TIM3_IN0_1 Mux input channel 0 of TIM module 3
ES
CCU61_CTRAPA Trap input capture
CCU60_T12HRE External timer start 12
MSC0_INJ0 Injection signal from port
GETH_MDIOA MDIO Input
P00.0 O0 General-purpose output
GTM_TOUT9 O1 GTM muxed output
IOM_REF0_9 Reference input 0
ASCLIN3_ASCLK O2 Shift clock output
ASCLIN3_ATX O3 Transmit output
IOM_MON2_15 Monitor input 2
— O4 Reserved
CAN10_TXD O5 CAN transmit output node 0
— O6 Reserved
CCU60_COUT63 O7 T13 PWM channel 63
GETH_MDIO O MDIO Output
Data Sheet 15 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 2-1 Port 00 Functions (cont’d)

Type
M7 P00.1 I SLOW / General-purpose input
VEXT /
ES
CCU60_CC60INB T12 capture input 60
ASCLIN3_ARXE Receive input
EDSADC_DSCIN5A Modulator clock input
CAN10_RXDA CAN receive input node 0
PSI5_RX0A RXD inputs (receive data) channel 0
CCU61_CC60INA T12 capture input 60
SENT_SENT0B Receive input channel 0
EDSADC_DSCIN7B Modulator clock input
EVADC_G9CH11 AI Analog input channel 11, group 9
EDSADC_EDS5NA Negative analog input channel 5, pin A
— O3 Reserved
EDSADC_DSCOUT5 O4 Modulator clock output
SENT_SPC0 O6 Transmit output
CCU61_CC60 O7 T12 PWM channel 60
Data Sheet 16 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
N6 P00.2 I SLOW / General-purpose input
VEXT /
ES1
EDSADC_DSDIN7B Digital datastream input
EDSADC_DSDIN5A Digital datastream input
EDSADC_EDS5PA Positive analog input channel 5, pin A
PSI5_TX0 O4 TXD outputs (send data)
QSPI3_SLSO4 O6 Master slave select output
Data Sheet 17 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
EDSADC_ITR5F Trigger/Gate input
PSI5S_RXA RX data input
EDSADC_EDS5NB Negative analog input channel 5, pin B
ASCLIN3_ASLSO O2 Slave select signal output
— O3 Reserved
— O5 Reserved
Data Sheet 18 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
P6 P00.4 I SLOW / General-purpose input
VEXT /
ES1
SCU_E_REQ2_2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
EDSADC_SGNA Carrier sign signal input
ASCLIN10_ARXA Receive input
GTM_DTMA5_0 CDTM5_DTM4
GTM_DTMT3_0 CDTM3_DTM0
EDSADC_EDS5PB Positive analog input channel 5, pin B
PSI5S_TX O2 TX data output
EVADC_FC4BFLOUT O5 Boundary flag output, FC channel 4
Data Sheet 19 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
CAN11_RXDB CAN receive input node 1
EDSADC_CGPWMN O2 Negative carrier generator output
Data Sheet 20 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
EDSADC_CGPWMP O2 Positive carrier generator output
EVADC_EMUX10 O5 Control of external analog multiplexer interface 1
Data Sheet 21 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
R6 P00.7 I SLOW / General-purpose input
VEXT /
ES1
CCU61_CC60INC T12 capture input 60
GPT120_T2INA Trigger/gate input of timer T2
CCU61_CCPOS0A Hall capture input 0
CCU60_T12HRB External timer start 12
Data Sheet 22 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
GPT120_T2EUDA Count direction control input of timer T2
ASCLIN10_ARXB Receive input
— O4 Reserved
Data Sheet 23 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
CCU60_T13HRC External timer start 13
ASCLIN3_ARTS O3 Ready to send output
Data Sheet 24 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O3 Reserved
— O4 Reserved
— O5 Reserved
T6 P00.11 I SLOW / General-purpose input
VEXT /
ES1
EVADC_FC3CH0 Analog input FC channel 3
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 25 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
ASCLIN3_ACTSA Clear to send input
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
T2 P00.13 I FAST / General-purpose input
VEXT /
ES
— O2 Reserved
— O3 Reserved
CCU_EXTCLK1 O4 CCU external clock
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 26 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
U2 P00.14 I SLOW / General-purpose input
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
U1 P00.15 I FAST / General-purpose input
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 27 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
J2 P01.0 I SLOW / General-purpose input
VEXT /
ES
CAN21_RXDE CAN receive input node 1
EDSADC_ITR6E Trigger/Gate input
CAN03_RXDF CAN receive input node 3
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
K1 P01.1 I SLOW / General-purpose input
VEXT /
ES
ERAY1_RXDA1 Receive Channel A1
— O2 Reserved
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 28 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O7 Reserved
VEXT /
ES
QSPI3_SLSIB Slave select input
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 29 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
CAN01_RXDC CAN receive input node 1
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
QSPI3_MRSTC Master SPI data input
— O2 Reserved
— O3 Reserved
QSPI3_MRST O4 Slave SPI data output
— O5 Reserved
— O7 Reserved
Data Sheet 30 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
N9 P01.6 I FAST / General-purpose input
VEXT /
ES
QSPI3_MTSRC Save SPI data input
— O2 Reserved
QSPI3_MTSR O4 Master SPI data output
— O5 Reserved
— O6 Reserved
— O7 Reserved
P10 P01.7 I FAST / General-purpose input
VEXT /
ES
QSPI3_SCLKC Slave SPI clock inputs
— O2 Reserved
QSPI3_SCLK O4 Master SPI clock output
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 31 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
L1 P01.8 I SLOW / General-purpose input
VEXT /
ES
ERAY1_RXDB1 Receive Channel B1
ASCLIN0_ARXC Receive input
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
Data Sheet 32 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 33 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
ERAY1_TXDA O6 Transmit Channel A
— O7 Reserved
VEXT /
ES
— O3 Reserved
ERAY1_TXDB O6 Transmit Channel B
Data Sheet 34 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
ERAY1_TXENA O6 Transmit Enable Channel A
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 35 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
G6 P02.0 I FAST / General-purpose input
VEXT /
ES
ASCLIN2_ARXG Receive input
MSB)
Data Sheet 36 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
H7 P02.1 I SLOW / General-purpose input
VEXT /
ES
MSB)
— O5 Reserved
— O6 Reserved
Data Sheet 37 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
H6 P02.2 I FAST / General-purpose input
VEXT /
ES
Data Sheet 38 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSC1_SDI1 Upstream assynchronous input signal
PSI5_RX0B RXD inputs (receive data) channel 0
— O5 Reserved
— O6 Reserved
Data Sheet 39 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
J6 P02.4 I FAST / General-purpose input
VEXT /
ES
QSPI3_SLSIA Slave select input
I2C0_SDAA Serial Data Input
CAN0_ECTT1 External CAN time trigger input
PSI5S_CLK O4 PSISCLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA O5 Serial Data Output
Data Sheet 40 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
K7 P02.5 I FAST / General-purpose input
VEXT /
ES
I2C0_SCLA Serial Clock Input
PSI5S_RXB RX data input
QSPI3_MRSTA Master SPI data input
SENT_SENT3C Receive input channel 3
I2C0_SCL O5 Serial Clock Output
ERAY0_TXENB O6 Transmit Enable Channel B
Data Sheet 41 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
GPT120_T3INA Trigger/gate input of core timer T3
QSPI3_MTSRA Save SPI data input
RIF0_RAMP1B External RAMP B input
— O6 Reserved
Data Sheet 42 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
L7 P02.7 I FAST / General-purpose input
VEXT /
ES
GPT120_T3EUDA Count direction control input of core timer T3
QSPI3_SCLKA Slave SPI clock inputs
— O2 Reserved
Data Sheet 43 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
PMS_PMS_TESTGND AI Analog GND out for direct connection to GPIO
_PAD
GETH_MDC O6 MDIO clock
Data Sheet 44 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 45 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
F2 P02.12 I SLOW / General-purpose input
VEXT /
ES
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 46 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O6 Reserved
G2 P02.14 I SLOW / General-purpose input
VEXT /
ES
CAN20_RXDD CAN receive input node 0
CAN00_RXDH CAN receive input node 0
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 47 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O5 Reserved

Type
VEXT /
ES
GPT120_T6EUDB Count direction control input of core timer T6
GETH_RXERC Receive Error MII
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 48 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
GPT120_T5EUDB Count direction control input of timer T5
MSC0_EN1 O4 Chip Select
— O6 Reserved
— O7 Reserved
F10 P10.2 I FAST / General-purpose input
VEXT /
ES
GPT120_T6INB Trigger/gate input of core timer T6
MSB)
— O2 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 49 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
GPT120_T5INB Trigger/gate input of timer T5
— O2 Reserved
— O5 Reserved
— O7 Reserved
VEXT /
ES
CCU60_CCPOS0C Hall capture input 0
— O2 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 50 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
SCU_PD_HWCFG4 Hardware configuration pin 4
GPT120_T6OUT O5 External output for overflow/underflow detection of
core timer T6
Data Sheet 51 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
PSI5_RX3C RXD inputs (receive data) channel 3
ASCLIN2_ARXD Receive input
QSPI3_MTSRB Save SPI data input
core timer T3
Data Sheet 52 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
QSPI3_MRSTB Master SPI data input
MSB)
— O2 Reserved
— O4 Reserved
— O7 Reserved
Data Sheet 53 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
QSPI3_SCLKB Slave SPI clock inputs
MSB)
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
B8 P10.9 I SLOW / General-purpose input
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 54 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
A7 P10.11 I SLOW / General-purpose input
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 55 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 56 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
K15 P11.0 I RFAST / General-purpose input
VFLEX /
ES
— O3 Reserved
— O4 Reserved
GETH_TXD3 O6 Transmit Data
— O7 Reserved
K14 P11.1 I RFAST / General-purpose input
VFLEX /
ES
— O4 Reserved
— O7 Reserved
Data Sheet 57 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
F15 P11.2 I RFAST / General-purpose input
VFLEX /
ES
— O2 Reserved
G15 P11.3 I RFAST / General-purpose input
VFLEX /
ES
— O2 Reserved
— O5 Reserved
Data Sheet 58 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
J15 P11.4 I RFAST / General-purpose input
VFLEX /
ES
GETH_RXCLKB Receive Clock MII and RGMII (RGMII can use RXCLKA
only)
— O3 Reserved
— O4 Reserved
GETH_TXER O6 Transmit Error MII
GETH_TXCLK O7 Transmit Clock Output for RGMII
VFLEX /
ES
GETH_TXCLKA Transmit Clock Input for MII
GETH_GREFCLK Gigabit Reference Clock input for RGMII (125 MHz high
precission)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 59 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
J14 P11.6 I RFAST / General-purpose input
VFLEX /
ES
MSC0_FCLP O5 Shift-clock direct part of the differential signal
GETH_TXEN O6 Transmit Enable MII and RMII
GETH_TCTL Transmit Control for RGMII
VFLEX /
ES
GETH_RXD3A Receive Data 3 MII and RGMII (RGMII can use RXD3A
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 60 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VFLEX /
ES
GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
— O2 Reserved
— O4 Reserved
MSC0_SOP O5 Data output - direct part of the differential signal
— O6 Reserved
Data Sheet 61 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
MSB)
RXD0A only)
— O2 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 62 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII
GETH_RXDVA Receive Data Valid MII
GETH_CRSB Carrier Sense MII
GETH_RCTLA Receive Control for RGMII
— O2 Reserved
Data Sheet 63 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
GETH_REFCLKA Reference Clock input for RMII (50 MHz)
GETH_TXCLKB Transmit Clock Input for MII
GETH_RXCLKA Receive Clock MII and RGMII (RGMII can use RXCLKA
only)
GTM_CLK2 O3 CGM generated clock
VFLEX /
ES
GETH_RXERA Receive Error MII
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 64 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
GETH_CRSDVB Carrier Sense / Data Valid combi-signal for RMII
GETH_RXDVB Receive Data Valid MII
GETH_CRSA Carrier Sense MII
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VFLEX /
ES
GETH_COLA Collision MII
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 65 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
GETH_RXCLKC Receive Clock MII and RGMII (RGMII can use RXCLKA
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VFLEX /
ES
GETH_MDIOC MDIO Input
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 66 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
G17 P13.0 I LVDS_TX General-purpose input
GTM_TIM3_IN5_3 / FAST / Mux input channel 5 of TIM module 3
PU1 /
VEXT /
ASCLIN10_ARXC ES6 Receive input
QSPI2_SCLKN O3 Master SPI clock output (LVDS N line)
MSC0_FCLN O5 Shift-clock inverted part of the differential signal
— O6 Reserved
F17 P13.1 I LVDS_TX General-purpose input
PU1 /
VEXT /
I2C0_SCLB ES6 Serial Clock Input
— O2 Reserved
QSPI2_SCLKP O3 Master SPI clock output (LVDS P line)
— O4 Reserved
— O7 Reserved
Data Sheet 67 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
G16 P13.2 I LVDS_TX General-purpose input
PU1 /
VEXT /
GPT120_CAPINA ES6 Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB Serial Data Input
QSPI2_MTSRN O3 Master SPI data output (LVDS N line)
MSC0_SON O5 Data output - inverted part of the differential signal
— O7 Reserved
F16 P13.3 I LVDS_TX General-purpose input
PU1 /
VEXT /
P13.3 O0 ES6 General-purpose output
QSPI2_MTSRP O3 Master SPI data output (LVDS P line)
— O4 Reserved
— O6 Reserved
— O7 Reserved
B16 P13.4 I LVDS_TX General-purpose input
PU1 /
VEXT /
GTM_TIM3_IN3_8 ES6 Mux input channel 3 of TIM module 3
— O2 Reserved
— O3 Reserved
— O6 Reserved
Data Sheet 68 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
A16 P13.5 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 69 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
A14 P13.9 I FAST / General-purpose input
VEXT /
ES
I2C1_SCLB Serial Clock Input
— O4 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 70 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
ASCLIN3_ARXH Receive input
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 71 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 72 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES2
SENT_SENT17D Receive input channel 17
Data Sheet 73 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES2
MSB)
PMS_PINAWKP PINA ( P14.1) pin input
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 74 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
GETH_PPS O6 Pulse Per Second
— O7 Reserved
Data Sheet 75 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
VEXT /
ES
— O5 Reserved
Data Sheet 76 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 77 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
J17 P14.9 I LVDS_R General-purpose input
GTM_TIM3_IN3_3 X / FAST / Mux input channel 3 of TIM module 3
PU1 /
VEXT /
ASCLIN0_ACTSA ES Clear to send input
QSPI2_MRSTFN Master SPI data input (LVDS N line)
PU1 /
VEXT /
CAN23_RXDA ES CAN receive input node 3
QSPI2_MRSTFP Master SPI data input (LVDS P line)
Data Sheet 78 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 79 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O6 Reserved
— O7 Reserved
B18 P14.14 I FAST / General-purpose input
VEXT /
ES
— O7 Reserved
Data Sheet 80 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 81 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
SDMMC0_DAT7_IN read data in
— O4 Reserved
— O7 Reserved
SDMMC0_DAT7 O write data out
VEXT /
ES
MSB)
— O4 Reserved
— O5 Reserved
— O6 Reserved
SDMMC0_CLK O7 card clock
Data Sheet 82 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
QSPI2_MRSTE Master SPI data input
QSPI2_HSICINA Highspeed capture channel
— O4 Reserved
— O7 Reserved
VEXT /
ES
QSPI2_HSICINB Highspeed capture channel
SDMMC0_CMD_IN command in
— O4 Reserved
— O6 Reserved
— O7 Reserved
SDMMC0_CMD O command out
Data Sheet 83 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
I2C0_SCLC Serial Clock Input
MSB)
— O4 Reserved
— O5 Reserved
Data Sheet 84 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
I2C0_SDAC Serial Data Input
MSB)
— O4 Reserved
VEXT /
ES
Data Sheet 85 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
MSB)
— O2 Reserved
— O4 Reserved
— O5 Reserved
Data Sheet 86 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 87 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 88 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
CCU_PAD_SYSCLK Clock input pin for System PLL and Peripheral PLL
CBS_TGI0 Trigger input
MSB)
— O4 Reserved
HSCT0_SYSCLK_OUT O5 sys clock output
— O6 Reserved
— O7 Reserved
CBS_TGO0 O Trigger output
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 89 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
N24 P20.2 I S / PU / General-purpose input
VEXT This pin is latched at power on reset release to enter test
mode.
TESTMODE Testmode Enable Input
VEXT /
ES
— O7 Reserved
VEXT /
ES
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 90 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
ASCLIN9_ARXF Receive input
— O3 Reserved
— O4 Reserved
— O6 Reserved
VEXT /
ES
— O6 Reserved
Data Sheet 91 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O2 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
Data Sheet 92 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
IOM_PIN_13 GPIO pad input to FPC
— O2 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 93 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O6 Reserved
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 94 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
R22 P21.0 I LVDS_R General-purpose input
PU1 /
VEXT /
GTM_TIM2_IN4_6 ES Mux input channel 4 of TIM module 2
QSPI4_MRSTDN Master SPI data input (LVDS N line)
DMU_FDEST
HSCT1_RXDN Rx data
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
HSM_HSM1 O Pin Output Value
P22 P21.1 I LVDS_R General-purpose input
PU1 /
VEXT /
QSPI4_MRSTDP Master SPI data input (LVDS P line)
HSCT1_RXDP Rx data
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 95 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
R24 P21.2 I LVDS_R General-purpose input
PU1 /
VEXT /
QSPI2_MRSTCN Master SPI data input (LVDS N line)
SCU_EMGSTOP_POR Emergency stop Port Pin B input request
T_B
ASCLIN3_ARXGN Differential Receive input (low active)
HSCT0_RXDN Rx data
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
P24 P21.3 I LVDS_R General-purpose input
PU1 /
VEXT /
QSPI2_MRSTCP Master SPI data input (LVDS P line)
ASCLIN3_ARXGP Differential Receive input (high active)
GETH_MDIOD MDIO Input
HSCT0_RXDP Rx data
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 96 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
R25 P21.4 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
HSCT0_TXDN O Tx data
P25 P21.5 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
HSCT0_TXDP O Tx data
Data Sheet 97 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
N22 P21.6/TDI I FAST / General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3 PU. In Standby mode: HighZ.
TDI JTAG Module Data Input
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
core timer T3
DAP3 I/O DAP: DAP3 Data I/O
DAPE1 I/O DAPE: DAPE1 Data I/O
Data Sheet 98 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
N21 P21.7/TDO I FAST / General-purpose input
VEXT /
ES4
GETH_RXERB Receive Error MII
— O4 Reserved
— O5 Reserved
— O6 Reserved
core timer T6
TDO O JTAG Module Data Output
Data Sheet 99 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
W25 P22.0 I LVDS_TX General-purpose input
PU1 /
VEXT /
ASCLIN3_ATXN O2 Differential Transmit output (low active)
— O6 Reserved
W24 P22.1 I LVDS_TX General-purpose input
PU1 /
VEXT /
ASCLIN3_ATXP O2 Differential Transmit output (high active)
— O6 Reserved
Data Sheet 100 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
Y25 P22.2 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O6 Reserved
— O7 Reserved
Y24 P22.3 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O2 Reserved
— O6 Reserved
HSPDM_MUTE O7 Mute output to tx
Data Sheet 101 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
W21 P22.4 I FAST / General-purpose input
VEXT /
ES
— O3 Reserved
— O5 Reserved
HSPDM_BS0_OUT O7 Bit stream 0 output
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 102 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
V21 P22.6 I SLOW / General-purpose input
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 103 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 104 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 105 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AC25 P23.0 I SLOW / General-purpose input
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
AB24 P23.1 I FAST / General-purpose input
VEXT /
ES
Data Sheet 106 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AB25 P23.2 I SLOW / General-purpose input
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
AA24 P23.3 I SLOW / General-purpose input
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 107 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AA25 P23.4 I FAST / General-purpose input
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O7 Reserved
Y22 P23.6 I SLOW / General-purpose input
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 108 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved

Type
VEBU /
ES
EBU_A_IN11 Address Input
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
EBU_A11 O Address Output
Data Sheet 109 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 110 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
R29 P24.4 I FAST / General-purpose input
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 111 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
R30 P24.5 I FAST / General-purpose input
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 112 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 113 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 114 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 115 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 116 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved

Type
AG30 P25.0 I FAST / General-purpose input
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
EBU_BFCLKO O Burst Flash Clock Output
Data Sheet 117 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AF30 P25.1 I FAST / General-purpose input
VEBU /
ES
EBU_RD_FDBK Read Feedback
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
EBU_RD O Read Control
AF29 P25.2 I FAST / General-purpose input
VEBU /
ES
EBU_WR_FDBK Write Feedback
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
EBU_WR O Write Control
Data Sheet 118 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AE30 P25.3 I FAST / General-purpose input
VEBU /
ES
EBU_CS_FDBK2 Chip Select Feedback
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
EBU_BAA O7 Burst Address Advance
EBU_CS2 O Chip Select
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 119 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AD30 P25.5 I FAST / General-purpose input
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
EBU_WAIT Wait Input
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
EBU_ADV_FDBK ADV Control Signal Feedback
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
EBU_ADV O Address Valid Control Signal
Data Sheet 120 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AC29 P25.8 I FAST / General-purpose input
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
EBU_A23 O5 Address Output
— O6 Reserved
— O7 Reserved
EBU_BC0 O Byte Control
AC30 P25.9 I FAST / General-purpose input
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 121 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 122 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
Y29 P25.14 I FAST / General-purpose input
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 123 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AG29 P26.0 I SLOW / General-purpose input
VEBU /
ES
EBU_BFCLKI Burst Flash Clock Feedback
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved

Type
AJ21 P30.0 I FAST / General-purpose input
VEBU /
ES
EBU_AD_IN14 Data Bus Input
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
EBU_AD14 O Data Bus Output
Data Sheet 124 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AK21 P30.1 I FAST / General-purpose input
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 125 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 126 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 127 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 128 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 129 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 130 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 131 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 132 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 133 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 134 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 135 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 136 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 137 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 138 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 139 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEBU /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved

Type
AE22 P32.0/VGATE1N I SLOW / General-purpose input
PU1 / P32.0 / SMPS mode: analog output. External Pass Device
VEXT / gate control for EVRC
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 140 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AD22 P32.1/VGATE1P I SLOW / General-purpose input
PU1 / P32.1 / External Pass Device gate control for EVRC
GTM_TIM3_IN3_15 VEXT / Mux input channel 3 of TIM module 3
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
AE23 P32.2 I SLOW / General-purpose input
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
PMS_DCDCSYNCO O6 DCDC sync output
— O7 Reserved
Data Sheet 141 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O7 Reserved
VEXT /
ES
ASCLIN1_ACTSB Clear to send input
— O2 Reserved
— O3 Reserved
PMS_DCDCSYNCO O DCDC sync output
Data Sheet 142 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 143 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 144 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AD15 P33.0 I SLOW / General-purpose input
VEVRSB
/ ES5
IOM_GTM_0 GTM-provided inputs to EXOR combiner
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 145 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 146 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 147 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 148 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
CCU61_CTRAPC Trap input capture
Data Sheet 149 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
PSI5S_RXC RX data input
Data Sheet 150 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 151 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
MSB)
— O5 Reserved
— O7 Reserved
Data Sheet 152 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
GTM_TIM1_IN4_7 HighZ / Mux input channel 4 of TIM module 1
VEVRSB
SCU_EMGSTOP_POR Emergency stop Port Pin A input request
T_A
— O4 Reserved
— O6 Reserved
SMU_FSP0 O FSP[1..0] Output Signals - Generated by SMU_core
Data Sheet 153 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 154 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
the external PHY.
— O6 Reserved
VEVRSB
/ ES5
— O4 Reserved
— O5 Reserved
Data Sheet 155 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
PMS_PINBWKP PINB (P33.12) pin input
Data Sheet 156 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
EDSADC_SGNB Carrier sign signal input
— O6 Reserved
Data Sheet 157 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
QSPI2_SCLKD Slave SPI clock inputs
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEVRSB
/ ES5
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 158 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O3 Reserved
— O6 Reserved
VEVRSB
/ ES
CAN00_RXDG CAN receive input node 0
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 159 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
VEVRSB
/ ES
QSPI2_MRSTD Master SPI data input
— O3 Reserved
— O5 Reserved
Data Sheet 160 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES
QSPI2_MTSRD Save SPI data input
— O3 Reserved
— O5 Reserved
Table 2-22 Analog Inputs

Type
AA15 AN0 I D / HighZ Analog Input 0
EVADC_G0CH0 / VDDM Analog input channel 0, group 0
AB15 AN1 I D / HighZ Analog Input 1
AD14 AN2 I D / HighZ Analog Input 2
EVADC_G0CH4 Analog input channel 4, group 0
AE14 AN5 I D / HighZ Analog Input 5
Data Sheet 161 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 2-22 Analog Inputs (cont’d)

Type
EDSADC_EDS3NB Negative analog input channel 3, pin N
AB10 AN17/P40.10 I S / HighZ Analog Input 17
SENT_SENT10A / VDDM Receive input channel 10
Data Sheet 162 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AD9 AN18/P40.11 I S / HighZ Analog Input 18
Y10 AN23 I D / HighZ Analog Input 23
CCU60_CCPOS0D Hall capture input 0
CCU60_CCPOS1B Hall capture input 1
AC7 AN26/P40.2 I S / HighZ Analog Input 26
Data Sheet 163 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
W9 AN32/P40.4 I S / HighZ Analog Input 32
Y6 AN33/P40.5 I S / HighZ Analog Input 33
W10 AN34 I D / HighZ Analog Input 34
V9 AN36/P40.6 I S / HighZ Analog Input 36
Data Sheet 164 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
U10 AN40 I D / HighZ Analog Input 40
T10 AN42 I D / HighZ Analog Input 42
V6 AN44 I D / HighZ Analog Input 44
EDSADC_EDS1PC Positive analog input channel 1, pin C
EDSADC_EDS1NC Negative analog input channel 1, pin C
EDSADC_EDS1PD Positive analog input channel 1, pin D
Data Sheet 165 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
EDSADC_EDS1ND Negative analog input channel 1, pin D
AK7 AN48 I D / HighZ Analog Input 48
AJ7 AN49 I D / HighZ Analog Input 49
AJ4 AN54/P41.4 I S / HighZ Analog Input 54
AK4 AN55/P41.5 I S / HighZ Analog Input 55
AF1 AN56 I D / HighZ Analog Input 56
AF2 AN57 I D / HighZ Analog Input 57
Data Sheet 166 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
AA1 AN67/P40.15 I S / HighZ Analog Input 67
Data Sheet 167 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
EDSADC_EDS12PA Positive analog input channel 9, pin B
EDSADC_EDS12NA Negative analog input channel 9, pin B
EDSADC_EDS13PA / VDDM Positive analog input channel 13, pin A
EDSADC_EDS13NA / VDDM Negative analog input channel 13, pin A
Table 2-23 System I/O

Type
T12 AGBTCLKN (VSS) I LVDS_R AGBT Input;(TC3xx devices without AGBT: VSS)
X / VEXT
R12 AGBTCLKP (VSS) I LVDS_R AGBT Input;(TC3xx devices without AGBT: VSS)
X / VEXT
W15 AGBTTXN (VSS) O LVDS_TX AGBT Output;(TC3xx devices without AGBT: VSS)
/ VEXT
W16 AGBTTXP (VSS) O LVDS_TX AGBT Output;(TC3xx devices without AGBT: VSS)
/ VEXT
T19 AGBTERR (VSS) I FAST / AGBT Input;(TC3xx devices without AGBT: VSS)
PD /
VEXT
AD22 P32.1/VGATE1P O — DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
AE22 P32.0/VGATE1N O — DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
U25 XTAL1 I XTAL / XTAL1. Main Oscillator/PLL/Clock Generator Input.
VEXTOS
C
U24 XTAL2 O XTAL / XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
VEXTOS
C
Data Sheet 168 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 2-23 System I/O (cont’d)

Type
R19 DAPE0 I FAST / DAPE: DAPE0 Clock Input
PD2 / DAPE: DAPE0 clock input(PD Devices: NC)
VEXT
T24 TRST I FAST / JTAG Module Reset/Enable Input
DAPE0 I PU2 / DAPE: DAPE0 Clock Input
VEXT
R21 TMS I FAST / JTAG Module State Machine Control Input
DAP1 I/O PD2 / DAP: DAP1 Data I/O
VEXT
P21 TCK I FAST / JTAG Module Clock Input
DAP0 I PD2 / DAP: DAP0 Clock Input
VEXT
M16 DAPE1 I/O FAST / DAPE: DAPE1 Data I/O
PD2 / DAPE: DAPE1 Data I/O(PD Devices: VSS)
VEXT
M15 DAPE2 I/O FAST / DAPE: DAPE2 Data I/O
VEXT
M21 ESR1 I FAST / ESR1 Port Pin input - can be used to trigger a reset or
PU1 / an NMI
VEXT ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP I ESR1 pin input
L21 ESR0 I FAST / ESR0 Port Pin input - can be used to trigger a reset or
OD / an NMI
VEXT ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
M22 PORST I PORST / PORST pin input
PD / Power On Reset Input. Additional strong PD in case of
VEXT power fail.
Data Sheet 169 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 2-24 Supply

Type
N19, V19, VDD I — Digital Core Power Supply (1.25V)
M18, W18,
W13, V12,
J21, K20
AJ30, AH29, VEXT I — External Power Supply (5V / 3.3V)
AD25, AC24,
G8, F7, B3,
A2
J10 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V)
AE10, AJ9, VDDM I — ADC Analog Power Supply (5V / 3.3V)
AK9
A29, B28, VDDP3 I — Flash Power Supply (3.3V)
F24, G23
AK30, AJ29, VSS I — Digital Ground
AE25, AD24,
AB22, AA21,
K10, J9, G7,
B2, A30,
B30, B29,
F25, G24,
J22, K21
AE9, AJ8, VSSM I — Analog Ground for VDDM
AK8
P19, U19, VSS I — Digital Ground
P18, R18,
T18, U18,
M17, N17,
R17, T17,
V17, W17,
N16, P16,
R16, T16,
U16, V16,
N15, P15,
R15, T15,
U15, V15,
M14, N14,
R14, T14,
V14, W14,
P13, R13,
T13, U13,
P12, U12
T25 VSSOSC I — Oscillator Ground
AE11 VAREF1 I — Positive Analog Reference Voltage 1
AE12 VAGND1 I — Negative Analog Reference Voltage 1
Data Sheet 170 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 2-24 Supply (cont’d)

Type
AA6 VAREF2 I — Positive Analog Reference Voltage 2
AA7 VAGND2 I — Negative Analog Reference Voltage 2
C30, D30, NC I — Not connected. These pins are reserved for future
E30, F30, extensions and shall not be connected externally
G30, W30,
C29, D29,
E29, F29,
G29, A28,
A27, B27,
A26, B26,
A25, A21,
AJ20, B21,
B20, A17,
B17, A10,
B10, A9, B9,
A8, A4, B4,
A3, AJ3,
AK3, C2, D2,
E2, H2, R2,
AH2, AJ2,
AK2, B1, C1,
D1, E1, H1,
J1, R1, T1,
AH1, AJ1,
B6, B14, B25
AB9, F6, NC1 I — Not connected. These pins are not connected on
AE6, A1, package level and will not be used for future
AK1, V30, extensions
V29
H30, H29, VSS I — Digital Ground for EBU
AJ10, AK10
N12, M13 VDDSB (VDD) I — Devices with integrated EMEM: EMEM SRAM Standby
Power Supply, VDDSB (1.25V);Devices without
integrated EMEM: VDD (1.25V)
J29, J30, VEBU I — Digital Power Supply for EBU (5V / 3.3V)
AH30, AK29,
AK20, AJ11,
AK11
AA16 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby
SRAM
V24 VDDOSC I — Digital Power Supply for Oscillator (1.25V)
V25 VEXTOSC I — Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT)
AG1 VAREF3 I — Positive Analog Reference Voltage 3
AG2 VAGND3 I — Negative Analog Reference Voltage 3
Data Sheet 171 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
2.2 LFBGA-292 Package Variant Pin Configuration

Type
VEXT /
ES
— O4 Reserved
— O6 Reserved
Data Sheet 172 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
Data Sheet 173 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 174 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O3 Reserved
— O5 Reserved
Data Sheet 175 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
MSB)
Data Sheet 176 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 177 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 178 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 179 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O4 Reserved
Data Sheet 180 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 181 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O3 Reserved
— O4 Reserved
— O5 Reserved
VEXT /
ES1
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 182 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 183 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 184 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O5 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 185 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 186 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
Data Sheet 187 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
C2 P02.1 I SLOW / General-purpose input
VEXT /
ES
MSB)
— O5 Reserved
— O6 Reserved
Data Sheet 188 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
C1 P02.2 I FAST / General-purpose input
VEXT /
ES
Data Sheet 189 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
D2 P02.3 I SLOW / General-purpose input
VEXT /
ES
— O5 Reserved
— O6 Reserved
Data Sheet 190 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
D1 P02.4 I FAST / General-purpose input
VEXT /
ES
the external PHY.
Data Sheet 191 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
E2 P02.5 I FAST / General-purpose input
VEXT /
ES
Data Sheet 192 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O6 Reserved
Data Sheet 193 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
Data Sheet 194 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
_PAD
Data Sheet 195 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
E4 P02.9 I SLOW / General-purpose input
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 196 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved

Type
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 197 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O6 Reserved
— O7 Reserved
VEXT /
ES
MSB)
— O2 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 198 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O2 Reserved
— O5 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 199 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
core timer T6
Data Sheet 200 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
core timer T3
Data Sheet 201 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O2 Reserved
— O4 Reserved
— O7 Reserved
Data Sheet 202 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 203 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
E10 P11.0 I RFAST / General-purpose input
VFLEX /
ES
— O3 Reserved
— O4 Reserved
— O7 Reserved
VFLEX /
ES
— O4 Reserved
— O7 Reserved
Data Sheet 204 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
A10 P11.2 I RFAST / General-purpose input
VFLEX /
ES
— O2 Reserved
B10 P11.3 I RFAST / General-purpose input
VFLEX /
ES
— O2 Reserved
— O5 Reserved
Data Sheet 205 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
D10 P11.4 I RFAST / General-purpose input
VFLEX /
ES
only)
— O3 Reserved
— O4 Reserved
VFLEX /
ES
precission)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 206 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
VFLEX /
ES
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 207 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VFLEX /
ES
RXD1A only)
— O2 Reserved
— O4 Reserved
— O6 Reserved
Data Sheet 208 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
MSB)
RXD0A only)
— O2 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 209 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
— O2 Reserved
Data Sheet 210 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
only)
VFLEX /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 211 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VFLEX /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 212 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VFLEX /
ES
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 213 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
ASCLIN10_ARXC ES6 Receive input
— O6 Reserved
PU1 /
VEXT /
I2C0_SCLB ES6 Serial Clock Input
— O2 Reserved
— O4 Reserved
— O7 Reserved
Data Sheet 214 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
GPT120_CAPINA ES6 Trigger input to capture value of timer T5 into CAPREL
register
— O7 Reserved
PU1 /
VEXT /
P13.3 O0 ES6 General-purpose output
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 215 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES2
Data Sheet 216 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES2
MSB)
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 217 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 218 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
VEXT /
ES
— O5 Reserved
Data Sheet 219 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 220 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
D12 P14.9 I LVDS_R General-purpose input
PU1 /
VEXT /
PU1 /
VEXT /
Data Sheet 221 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O7 Reserved
VEXT /
ES
MSB)
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 222 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 223 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O4 Reserved
— O5 Reserved
Data Sheet 224 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O4 Reserved
VEXT /
ES
Data Sheet 225 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
MSB)
— O2 Reserved
— O4 Reserved
— O5 Reserved
Data Sheet 226 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 227 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
H19 P20.2 I S / PU / General-purpose input
mode.
VEXT /
ES
— O7 Reserved
VEXT /
ES
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 228 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O6 Reserved
VEXT /
ES
— O6 Reserved
Data Sheet 229 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O2 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
Data Sheet 230 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
— O2 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 231 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O6 Reserved
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 232 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
K17 P21.0 I LVDS_R General-purpose input
PU1 /
VEXT /
DMU_FDEST
HSCT1_RXDN Rx data
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
HSCT1_RXDP Rx data
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 233 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
T_B
HSCT0_RXDN Rx data
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
HSCT0_RXDP Rx data
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 234 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
K20 P21.4 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
J20 P21.5 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 235 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
H17 P21.6/TDI I FAST / General-purpose input
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
core timer T3
Data Sheet 236 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
H16 P21.7/TDO I FAST / General-purpose input
VEXT /
ES4
— O4 Reserved
— O5 Reserved
— O6 Reserved
core timer T6
Data Sheet 237 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
— O6 Reserved
PU1 /
VEXT /
— O6 Reserved
Data Sheet 238 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
— O2 Reserved
— O6 Reserved
Data Sheet 239 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O5 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 240 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 241 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 242 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 243 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
Data Sheet 244 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 245 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 246 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved

Type
Y17 P32.0/VGATE1N I SLOW / General-purpose input
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 247 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
W17 P32.1/VGATE1P I SLOW / General-purpose input
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 248 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
Data Sheet 249 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 250 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 251 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
W10 P33.0 I SLOW / General-purpose input
VEVRSB
/ ES5
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 252 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 253 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 254 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 255 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 256 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 257 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 258 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
MSB)
— O5 Reserved
— O7 Reserved
Data Sheet 259 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
T_A
— O4 Reserved
— O6 Reserved
Data Sheet 260 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 261 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
the external PHY.
— O6 Reserved
VEVRSB
/ ES5
— O4 Reserved
— O5 Reserved
Data Sheet 262 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 263 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O6 Reserved
Data Sheet 264 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEVRSB
/ ES5
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 265 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O3 Reserved
— O6 Reserved
VEVRSB
/ ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 266 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
VEVRSB
/ ES
— O3 Reserved
— O5 Reserved
Data Sheet 267 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES
— O3 Reserved
— O5 Reserved

Type
Data Sheet 268 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
U5 AN17/P40.10 I S / HighZ Analog Input 17
Data Sheet 269 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
R5 AN23 I D / HighZ Analog Input 23
Data Sheet 270 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
P4 AN32/P40.4 I S / HighZ Analog Input 32
R1 AN33/P40.5 I S / HighZ Analog Input 33
P5 AN34 I D / HighZ Analog Input 34
N4 AN36/P40.6 I S / HighZ Analog Input 36
Data Sheet 271 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
N5 AN38/P40.8 I S / HighZ Analog Input 38
M5 AN40 I D / HighZ Analog Input 40
L5 AN42 I D / HighZ Analog Input 42
L4 AN43 I D / HighZ Analog Input 43
N1 AN44 I D / HighZ Analog Input 44
N2 AN45 I D / HighZ Analog Input 45
Data Sheet 272 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type

Type
L7 AGBTCLKN (VSS) I LVDS_R AGBT Input;(TC3xx devices without AGBT: VSS)
X / VEXT
K7 AGBTCLKP (VSS) I LVDS_R AGBT Input;(TC3xx devices without AGBT: VSS)
X / VEXT
P10 AGBTTXN (VSS) O LVDS_TX AGBT Output;(TC3xx devices without AGBT: VSS)
/ VEXT
P11 AGBTTXP (VSS) O LVDS_TX AGBT Output;(TC3xx devices without AGBT: VSS)
/ VEXT
L14 AGBTERR (VSS) I FAST / AGBT Input;(TC3xx devices without AGBT: VSS)
PD /
VEXT
W17 P32.1/VGATE1P O — DCDC P ch. MOSFET gate driver output
Y17 P32.0/VGATE1N O — DCDC N ch. MOSFET gate driver output
M20 XTAL1 I XTAL / XTAL1. Main Oscillator/PLL/Clock Generator Input.
VEXTOS
C
M19 XTAL2 O XTAL / XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
VEXTOS
C
K14 DAPE0 I FAST / DAPE: DAPE0 Clock Input
VEXT
L19 TRST I FAST / JTAG Module Reset/Enable Input
VEXT
K16 TMS I FAST / JTAG Module State Machine Control Input
VEXT
J16 TCK I FAST / JTAG Module Clock Input
VEXT
Data Sheet 273 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
G11 DAPE1 I/O FAST / DAPE: DAPE1 Data I/O
VEXT
VEXT
G16 ESR1 I FAST / ESR1 Port Pin input - can be used to trigger a reset or
PU1 / an NMI
F16 ESR0 I FAST / ESR0 Port Pin input - can be used to trigger a reset or
OD / an NMI
G17 PORST I PORST / PORST pin input
VEXT power fail.
Table 2-43 Supply

Type
P8, P13, N7, VDD I — Digital Core Power Supply (1.25V)
N14, E15,
H14, D16,
G13
A2, B3, V19, VEXT I — External Power Supply (5V / 3.3V)
W20
D5 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V)
Y5 VDDM I — ADC Analog Power Supply (5V / 3.3V)
B18, A19 VDDP3 I — Flash Power Supply (3.3V)
Data Sheet 274 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
B2, D4, E5, VSS I — Digital Ground
T16, U17,
W19, Y20,
E16, D17,
B19, A20
Y4 VSSM I — Analog Ground for VDDM
P9, P12, N9, VSS I — Digital Ground
N10, N11,
N12, M7,
M8, M10,
M11, M13,
M14, L8, L9,
L10, L11,
L12, L13,
K8, K9, K10,
K11, K12,
K13, J7, J8,
J10, J11,
J13, J14, H9,
H10, H11,
H12, G9,
G12
L20 VSSOSC I — Oscillator Ground
Y6 VAREF1 I — Positive Analog Reference Voltage 1
Y7 VAGND1 I — Negative Analog Reference Voltage 1
T1 VAREF2 I — Positive Analog Reference Voltage 2
T2 VAGND2 I — Negative Analog Reference Voltage 2
A1, Y1, U4 NC1 I — Not connected. These pins are not connected on
package level and will not be used for future
extensions
G8, H7 VDDSB (VDD) I — Devices with integrated EMEM: EMEM SRAM Standby
Power Supply, VDDSB (1.25V);Devices without
integrated EMEM: VDD (1.25V)
T11 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby
SRAM
N19 VDDOSC I — Digital Power Supply for Oscillator (1.25V)
N20 VEXTOSC I — Digital Power Supply for Oscillator (shall be supplied
Data Sheet 275 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Pin Definition and Functions:LFBGA-292 ADAS Package Variant Pin
2.3 LFBGA-292 ADAS Package Variant Pin Configuration

Type
VEXT /
ES
— O4 Reserved
— O6 Reserved
Data Sheet 276 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
Data Sheet 277 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 278 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O3 Reserved
— O5 Reserved
Data Sheet 279 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
MSB)
Data Sheet 280 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 281 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 282 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 283 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O4 Reserved
Data Sheet 284 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
Data Sheet 285 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O3 Reserved
— O4 Reserved
— O5 Reserved
VEXT /
ES1
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 286 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES1
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 287 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
Data Sheet 288 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O5 Reserved
— O6 Reserved
Data Sheet 289 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
Data Sheet 290 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O5 Reserved
— O6 Reserved
Data Sheet 291 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
the external PHY.
Data Sheet 292 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
Data Sheet 293 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O6 Reserved
Data Sheet 294 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
Data Sheet 295 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
_PAD
Data Sheet 296 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O6 Reserved
— O7 Reserved
Data Sheet 297 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O2 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 298 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O2 Reserved
— O5 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 299 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
core timer T6
Data Sheet 300 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
core timer T3
Data Sheet 301 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O2 Reserved
— O4 Reserved
— O7 Reserved
Data Sheet 302 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 303 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
— O3 Reserved
— O4 Reserved
— O7 Reserved
VFLEX /
ES
— O4 Reserved
— O7 Reserved
Data Sheet 304 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
A12 P11.2 I RFAST / General-purpose input
VFLEX /
ES
— O2 Reserved
B12 P11.3 I RFAST / General-purpose input
VFLEX /
ES
— O2 Reserved
— O5 Reserved
Data Sheet 305 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
only)
— O3 Reserved
— O4 Reserved
VFLEX /
ES
precission)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 306 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
VFLEX /
ES
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 307 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VFLEX /
ES
RXD1A only)
— O2 Reserved
— O4 Reserved
— O6 Reserved
Data Sheet 308 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
MSB)
RXD0A only)
— O2 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 309 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
— O2 Reserved
Data Sheet 310 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
only)
VFLEX /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 311 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VFLEX /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 312 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VFLEX /
ES
only)
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VFLEX /
ES
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 313 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES2
Data Sheet 314 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES2
MSB)
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 315 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 316 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
VEXT /
ES
— O5 Reserved
Data Sheet 317 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 318 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
PU1 /
VEXT /
Data Sheet 319 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O7 Reserved
VEXT /
ES
MSB)
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 320 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 321 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O4 Reserved
— O5 Reserved
Data Sheet 322 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O4 Reserved
VEXT /
ES
Data Sheet 323 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
MSB)
— O2 Reserved
— O4 Reserved
— O5 Reserved
Data Sheet 324 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 325 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
H19 P20.2 I S / PU / General-purpose input
mode.
VEXT /
ES
— O7 Reserved
VEXT /
ES
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 326 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O6 Reserved
VEXT /
ES
— O6 Reserved
Data Sheet 327 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
MSB)
— O2 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
Data Sheet 328 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEXT /
ES
— O2 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 329 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O6 Reserved
VEXT /
ES
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 330 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
DMU_FDEST
HSCT1_RXDN Rx data
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
HSCT1_RXDP Rx data
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 331 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
T_B
HSCT0_RXDN Rx data
— O3 Reserved
— O4 Reserved
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
HSCT0_RXDP Rx data
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 332 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
K20 P21.4 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
J20 P21.5 I LVDS_TX General-purpose input
PU1 /
VEXT /
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 333 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
H17 P21.6/TDI I FAST / General-purpose input
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
core timer T3
Data Sheet 334 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
H16 P21.7/TDO I FAST / General-purpose input
VEXT /
ES4
— O4 Reserved
— O5 Reserved
— O6 Reserved
core timer T6
Data Sheet 335 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
— O6 Reserved
PU1 /
VEXT /
— O6 Reserved
Data Sheet 336 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
PU1 /
VEXT /
— O6 Reserved
— O7 Reserved
PU1 /
VEXT /
— O2 Reserved
— O6 Reserved
Data Sheet 337 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O5 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 338 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 339 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 340 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 341 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
Data Sheet 342 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 343 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O4 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O4 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 344 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved

Type
Y17 P32.0/VGATE1N I SLOW / General-purpose input
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 345 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
W17 P32.1/VGATE1P I SLOW / General-purpose input
ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 346 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
Data Sheet 347 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
VEXT /
ES
— O2 Reserved
— O3 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 348 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEXT /
ES
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
— O7 Reserved
Data Sheet 349 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O7 Reserved
Data Sheet 350 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 351 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 352 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O7 Reserved
Data Sheet 353 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 354 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 355 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 356 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
MSB)
— O5 Reserved
— O7 Reserved
Data Sheet 357 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
T_A
— O4 Reserved
— O6 Reserved
Data Sheet 358 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 359 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
the external PHY.
— O6 Reserved
VEVRSB
/ ES5
— O4 Reserved
— O5 Reserved
Data Sheet 360 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
Data Sheet 361 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O6 Reserved
Data Sheet 362 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
VEVRSB
/ ES5
— O2 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 363 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES5
— O3 Reserved
— O6 Reserved
VEVRSB
/ ES
— O2 Reserved
— O3 Reserved
— O4 Reserved
— O5 Reserved
— O6 Reserved
Data Sheet 364 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES
— O3 Reserved
— O5 Reserved
— O6 Reserved
VEVRSB
/ ES
— O3 Reserved
— O5 Reserved
Data Sheet 365 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
VEVRSB
/ ES
— O3 Reserved
— O5 Reserved

Type
C2 P50.0 I LVDS_R —
RIF0_D1N X / HighZ Radar data negative in 1
/ VEXT /
ES
C1 P50.1 I LVDS_R —
RIF0_D1P X / HighZ Radar data positive in 1
/ VEXT /
ES
D2 P50.2 I LVDS_R —
/ VEXT /
ES
D1 P50.3 I LVDS_R —
/ VEXT /
ES
E2 P50.4 I LVDS_R —
RIF0_CLKN X / HighZ Radar clock negative in
/ VEXT /
ES
Data Sheet 366 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
E1 P50.5 I LVDS_R —
RIF0_CLKP X / HighZ Radar clock positive in
/ VEXT /
ES
F2 P50.6 I LVDS_R —
RIF0_FRP X / HighZ Frame clock positive in
/ VEXT /
ES
F1 P50.7 I LVDS_R —
RIF0_FRN X / HighZ Frame clock negative in
/ VEXT /
ES
G2 P50.8 I LVDS_R —
/ VEXT /
ES
G1 P50.9 I LVDS_R —
/ VEXT /
ES
H2 P50.10 I LVDS_R —
/ VEXT /
ES
H1 P50.11 I LVDS_R —
/ VEXT /
ES

Type
B9 P51.0 I LVDS_R —
/ VEXT /
ES
A9 P51.1 I LVDS_R —
/ VEXT /
ES
/ VEXT /
ES
Data Sheet 367 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
/ VEXT /
ES
RIF1_CLKN X / HighZ Radar clock negative in
/ VEXT /
ES
RIF1_CLKP X / HighZ Radar clock positive in
/ VEXT /
ES
RIF1_FRP X / HighZ Frame clock positive in
/ VEXT /
ES
RIF1_FRN X / HighZ Frame clock negative in
/ VEXT /
ES
/ VEXT /
ES
/ VEXT /
ES
/ VEXT /
ES
/ VEXT /
ES

Type
Data Sheet 368 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
Data Sheet 369 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
Data Sheet 370 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
T4 AN24/P40.0 I S / HighZ Analog Input 24
R4 AN25/P40.1 I S / HighZ Analog Input 25
Data Sheet 371 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type

Type
L7 AGBTCLKN (VSS) I LVDS_R AGBT Input;(TC3xx devices without AGBT: VSS)
X / VEXT
K7 AGBTCLKP (VSS) I LVDS_R AGBT Input;(TC3xx devices without AGBT: VSS)
X / VEXT
P10 AGBTTXN (VSS) O LVDS_TX AGBT Output;(TC3xx devices without AGBT: VSS)
/ VEXT
P11 AGBTTXP (VSS) O LVDS_TX AGBT Output;(TC3xx devices without AGBT: VSS)
/ VEXT
L14 AGBTERR (VSS) I FAST / AGBT Input;(TC3xx devices without AGBT: VSS)
PD /
VEXT
W17 P32.1/VGATE1P O — DCDC P ch. MOSFET gate driver output
Y17 P32.0/VGATE1N O — DCDC N ch. MOSFET gate driver output
M20 XTAL1 I XTAL / XTAL1. Main Oscillator/PLL/Clock Generator Input.
VEXTOS
C
M19 XTAL2 O XTAL / XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
VEXTOS
C
K14 DAPE0 I FAST / DAPE: DAPE0 Clock Input
VEXT
L19 TRST I FAST / JTAG Module Reset/Enable Input
VEXT
K16 TMS I FAST / JTAG Module State Machine Control Input
VEXT
Data Sheet 372 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Type
J16 TCK I FAST / JTAG Module Clock Input
VEXT
VEXT
VEXT
G16 ESR1 I FAST / ESR1 Port Pin input - can be used to trigger a reset or
PU1 / an NMI
F16 ESR0 I FAST / ESR0 Port Pin input - can be used to trigger a reset or
OD / an NMI
G17 PORST I PORST / PORST pin input
VEXT power fail.
Table 2-62 Supply

Type
P8, P13, N7, VDD I — Digital Core Power Supply (1.25V)
N14, E15,
H14, D16,
G13, G8, H7
A2, B3, V19, VEXT I — External Power Supply (5V / 3.3V)
W20
D5 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V)
Y5 VDDM I — ADC Analog Power Supply (5V / 3.3V)
Data Sheet 373 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Pin Definition and Functions:Pin Position Definition

Type
B18, A19 VDDP3 I — Flash Power Supply (3.3V)
B2, D4, E5, VSS I — Digital Ground
T16, U17,
W19, Y20,
E16, D17,
B19, A20
Y4 VSSM I — Analog Ground for VDDM
P9, P12, N9, VSS I — Digital Ground
N10, N11,
N12, M7,
M8, M10,
M11, M13,
M14, L8, L9,
L10, L11,
L12, L13,
K8, K9, K10,
K11, K12,
K13, J7, J8,
J10, J11,
J13, J14, H9,
H10, H11,
H12, G9,
G12
L20 VSSOSC I — Oscillator Ground
Y6 VAREF1 I — Positive Analog Reference Voltage 1
Y7 VAGND1 I — Negative Analog Reference Voltage 1
T1 VAREF2 I — Positive Analog Reference Voltage 2
T2 VAGND2 I — Negative Analog Reference Voltage 2
A3, B1 NC I — Not connected. These pins are reserved for future
extensions and shall not be connected externally
A1, Y1, U4 NC1 I — Not connected. These pins are not connected on
package level and will not be used for future
extensions
T11 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby
SRAM
N19 VDDOSC I — Digital Power Supply for Oscillator (1.25V)
N20 VEXTOSC I — Digital Power Supply for Oscillator (shall be supplied
2.4 Pin Position Definition
Data Sheet 374 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 2-63 Pad List

Number Pad Name Pad Type X Y Comment
1 VEXT Vx 255699 175644 Supply Voltage
2 VSS Vx 356499 175644 Supply Voltage
3 P14.0 FAST / PU1 / 457299 175644 General-purpose I/O
VEXT / ES2
VEXT / ES
5 VDDP3 Vx 635499 322614 Supply Voltage
6 VDD Vx 714699 175644 Supply Voltage
7 P15.10 LVDS_TX / 826200 322614 General-purpose I/O
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
12 P14.4 SLOW / PU2 / 1348695 175644 General-purpose I/O
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES2
VEXT / ES
VEXT / ES
VEXT / ES
Data Sheet 375 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 2-63 Pad List (cont’d)

VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
VEXT / ES
FAST / PU1 /
VEXT / ES6
Data Sheet 376 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

FAST / PU1 /
VEXT / ES6
51 VDDP3 Vx 4334499 175644 Analog Input VDDP3
52 VDDP3 Vx 4388499 322614 Analog Input VDDP3
53 VDDP3 Vx 4469499 175644 Supply Voltage
VEXT / ES
VEXT / ES
VEXT / ES
58 P14.9 LVDS_RX / 4773024 175644 General-purpose I/O
FAST / PU1 /
VEXT / ES
FAST / PU1 /
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VFLEX / ES
VFLEX / ES
70 P11.0 RFAST / PU1 / 5703633 322614 General-purpose I/O
VFLEX / ES
Data Sheet 377 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

71 VFLEX Vx 5750631 175644 Supply Voltage
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
VFLEX / ES
Data Sheet 378 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VFLEX / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
112 VDDSB Vx 8279685 322614 Supply Voltage
VEXT / ES
VEXT / ES
VEXT / ES
Data Sheet 379 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEXT / ES
VEXT / ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
Data Sheet 380 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
HighZ / VEXT /
ES
VEXT / ES
VEXT / ES
Data Sheet 381 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
Data Sheet 382 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
206 RESERVED Vx 10265796 4734513 Must be bonded to VSS
VEXT / ES
VEXT / ES
Data Sheet 383 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES1
VEXT / ES1
VEXT / ES1
VEXT / ES1
VEXT / ES1
VEXT / ES1
VEXT / ES1
VEXT / ES1
VEXT / ES1
VEXT / ES1
VEXT / ES1
229 AN47 D / HighZ / 10265796 6156630 Analog Input 47
VDDM
230 VDDM Vx 10118826 6203628 Supply Voltage
231 VSSM Vx 10265796 6250626 Supply Voltage
VDDM
VDDM
Data Sheet 384 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VDDM
237 VAREF5 Vx 10265796 6532614 Supply Voltage
239 VAGND5 Vx 10265796 6656616 Supply Voltage
VDDM
VDDM
VDDM
VDDM
248 AN39/P40.9 S / HighZ / 10118826 7094601 Analog Input 39
VDDM
249 VDDM_EXT_ Vx 10265796 7141599 Supply Voltage
CONVPAD
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
Data Sheet 385 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
270 VDDM_EXT_ Vx 10118826 8173566 Supply Voltage
CONVIF
271 VSSM_CONVI Vx 10265796 8220564 Supply Voltage
F
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
Data Sheet 386 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
Data Sheet 387 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
Data Sheet 388 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VDDM
329 VEVRSB Vx 8176041 9042426 Supply Voltage
333 AGBTCLKN LVDS_RX / 7888959 9189441 AGBT Input;(TC3xx devices
(VSS) VEXT without AGBT: VSS)
334 AGBTCLKP LVDS_RX / 7807869 9189441 AGBT Input;(TC3xx devices
337 AGBTTXN LVDS_TX / 7538027 9189441 AGBT Output;(TC3xx
(VSS) VEXT devices without AGBT: VSS)
338 AGBTTXP LVDS_TX / 7456937 9189441 AGBT Output;(TC3xx
(VSS) VEXT devices without AGBT: VSS)
339 AGBTERR FAST / PD / 7266739 9189302 AGBT Input;(TC3xx devices
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB / ES
Data Sheet 389 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEVRSB /
ES5
VEVRSB / ES
VEVRSB /
ES5
VEVRSB /
ES5
358 P33.8 FAST / HighZ / 6276573 9042426 General-purpose I/O
VEVRSB
VEVRSB / ES
VEVRSB /
ES5
VEVRSB / ES
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB /
ES5
VEVRSB /
ES5
Data Sheet 390 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

371 P32.1/VGATE SLOW / PU1 / 5582385 9189396 General-purpose I/O
1P VEXT / ES
372 P32.1/VGATE Vx 5535387 9042426 DCDC P ch. MOSFET gate
1P driver output
374 P32.0/VGATE Vx 5441391 9042426 DCDC N ch. MOSFET gate
1N driver output
375 P32.0/VGATE SLOW / PU1 / 5394393 9189396 General-purpose I/O
1N VEXT / ES
381 RESERVED Vx 4747941 9189396 Must be bonded to VSS
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
Data Sheet 391 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
417 VEBU Vx 2183931 9189396 Supply Voltage
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
Data Sheet 392 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
Data Sheet 393 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
Data Sheet 394 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEBU / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
Data Sheet 395 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEXT / ES
505 VDDOSC Vx 348147 5664825 Supply Voltage
506 VSSOSC Vx 179145 5617827 Supply Voltage
507 XTAL1 XTAL / 179145 5458176 XTAL1. Main
VEXTOSC Oscillator/PLL/Clock
Generator Input.
508 XTAL2 XTAL / 179145 5364180 XTAL2. Main
VEXTOSC Oscillator/PLL/Clock
Generator OUTPUT
509 VSSOSC — 179145 5204529 Supply Voltage
510 VEXTOSC Vx 348147 5157531 Supply Voltage
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
Data Sheet 396 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEXT / ES
VEXT / ES
530 DAPE0 FAST / PD2 / 175644 3703041 DAPE: DAPE0 Clock Input
VEXT DAPE: DAPE0 clock
input(PD Devices: NC)
531 TRST FAST / PU2 / 322614 3656043 JTAG Module Reset/Enable
VEXT Input
FAST / PU1 /
VEXT / ES
FAST / PU1 /
VEXT / ES
FAST / PU1 /
VEXT / ES
FAST / PU1 /
VEXT / ES
FAST / PU1 /
VEXT / ES6
FAST / PU1 /
VEXT / ES6
541 TMS FAST / PD2 / 175644 2707551 JTAG Module State Machine
VEXT Control Input
VEXT / ES
543 TCK FAST / PD2 / 175644 2613555 JTAG Module Clock Input
VEXT
544 P20.2 S / PU / VEXT 322614 2566557 General-purpose I/O
This pin is latched at power
on reset release to enter test
mode.
Data Sheet 397 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEXT / ES
550 DAPE1 FAST / PD2 / 175644 2034729 DAPE: DAPE1 Data I/O
VEXT DAPE: DAPE1 Data I/O(PD
Devices: VSS)
551 P21.6/TDI FAST / PD / 322614 1987731 General-purpose I/O
PU2 / VEXT / PD during Reset and in
ES3 DAP/DAPE or JTAG mode.
After Reset release and when
not in DAP/DAPE or JTAG
mode: PU. In Standby mode:
HighZ.
552 DAPE2 FAST / PD2 / 175644 1940733 DAPE: DAPE2 Data I/O
VEXT DAPE: DAPE2 Data I/O(PD
Devices: VSS)
555 P21.7/TDO FAST / PU2 / 322614 1799739 General-purpose I/O
VEXT / ES4
556 ESR1 FAST / PU1 / 175644 1752741 ESR1 Port Pin input - can be
VEXT used to trigger a reset or an
NMI
ESR1: External System
Request Reset 1. Default NMI
function. See also SCU
chapter for details. Default
after power-on can be
different. See also SCU
chapter ´Reset Control Unit´
and SCU_IOCR register
description.
PMS_EVRWUP: EVR
Wakepup Pin
VEXT / ES
VEXT / ES
Data Sheet 398 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

561 ESR0 FAST / OD / 175644 1447209 ESR0 Port Pin input - can be
VEXT used to trigger a reset or an
NMI
ESR0: External System
Request Reset 0. Default
configuration during and after
reset is open-drain driver.
The driver drives low during
power-on reset. This is valid
additionally after deactivation
of PORST_N until the internal
reset phase has finished. See
also SCU chapter for details.
Default after power-on can be
different. See also SCU
chapter ´Reset Control Unit´
and SCU_IOCR register
description.
PMS_EVRWUP: EVR
Wakepup Pin
562 PORST PORST / PD / 322614 1400211 PORST pin input
VEXT Power On Reset Input.
Additional strong PD in case
of power fail.
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
Data Sheet 399 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
VEXT / ES
Whenever in table of section 3 ’Electrical Specification’ the term ‘neighbor pads’ is used, the detailed definition is
provided by Figure 2-63. This statement is also valid for next/nearest neighbor pads. This statement is also valid
for next/nearest neighbor pads.
In order to find out who is affecting operation on a target pad (interfering) a number of active close-neighbor pads
(ACNP) has to be defined.
Finding close-neighbor pads.
The Pad Ring has four edges: bottom, left, top, right. Each edge is limited, i.e. it has two ends.
Each pad has two direct (first) neighbors unless it is located at the end of the edge. In that case it only has one
neighbor. Similarly, each pad has two indirect (second) neighbors unless it or its first neighbor is located at the
end of the edge. These first and second neighbors we will collectively call Close-Neighbor pads. Therefore each
pad has 2 to 4 close-neighbor pads.
Finding close-neighbors can be done with the following sequence:
1.) Choose a target pad and lookup its “X” and “Y” coordinates in table Figure 2-63.
2.) Find first and second neighbors by calculating “X” and “Y” distance from the selected pad. Figure 2-63 is sorted
by “Y” coordinate, which might help locate the 4 close-neighbor candidates (if the pad is near the edge, it might
end up with less than 4 close-neighbors).
Defining active pads:
Pad is active if it is currently in use and if it doesn’t have “Vxx” in the name.
Figuring out number of active close-neighbor pads follow next rules:
- If the first neighbor is active, then we count it and also check if second neighbor (on the same side of selected
pad) is active.
- If the first neighbor is not active, then we do not check the second on the same side.
Data Sheet 400 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Pin Definition and Functions:Legend
2.5 Legend
The data in this chapter 2 match with the files TC39xed_IO_Spirit_v2.0.0.1.24.xml.
Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field Selection PCx = 0XXXB)
O = Output (for GPIO port lines the ´O´ represents in most cases the port HWOUT function)
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
Column “Buffer Type”:

RFAST = Pad class RFAST (5V/3.3V)
FAST = Pad class FAST (5V/3.3V)
SLOW = Pad class SLOW (5V/3.3V)
LVDS_TX = Pad class LVDS Transmit
LVDS_RX = Pad class LVDS Receive
S = Pad class S (Analog Input overlayed with General Purpose Input)
D = Pad class D (Analog Input)
Porst = Porst input Pad
XTAL1 = XTAL1 input Pad
XTAL2 = XTAL2 input Pad
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1)
PU2 = with pull-up device connected during startup and reset, HighZ in Standby mode
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1)
PD2 = with pull-down device connected during startup, reset, HighZ in Standby mode
OD = open drain during reset (PORST = 0)
ES = Supports Emergency Stop
ES1 = ES. ES can be overruled by VADC, control via P00_PCSR
ES2 = ES. ES can be overruled by DXCPL - DAP over CAN physical layer, No overruling for DXCM - Debug over
CAN message
ES3 = ES. ES can be overruled by JTAG mode if this pin is used as TDI
ES4 = ES. ES can be overruled by JTAG or Three Pin DAP mode
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG6 (P14.4). Pls. see also chapter
PMS, HWCFG[6].
Data Sheet 401 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Pin Definition and Functions:Legend
ES5 = ES. ES can be overruled by the Standby Controller - SCR - if implemented. Overruling can be disabled via
the control register P33_PCSR and P34_PCSR
ES6 = ES. On LVDS TX pads the ES affects the pads only in CMOS mode, not in LVDS mode. Thus, only when
LPCRx.TX_EN selects the CMOS Mode, the output is switched off in the ES event
Data Sheet 402 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationParameter Interpretation
3 Electrical Specification
3.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC39x and partly its requirements
on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with
an two-letter abbreviation in column “Symbol”:
• CC
Such parameters indicate Controller Characteristics which are a distinctive feature of the TC39x and must be
regarded for a system design.
• SR
Such parameters indicate System Requirements which must be provided by the microcontroller system in
which the TC39x designed in.
Data Sheet 403 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationAbsolute Maximum Ratings
3.2 Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 3-1 Absolute Maximum Ratings

Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Storage Temperature TST SR -65 - 150 °C upto 65h @ TJ = 150°C
Voltage at VDD power supply VDD SR - - 1.65 V upto 2.8h
pins with respect to VSS 1) 2) - - 1.45 V upto 72h
Voltage at VDDP3 power supply VDDP3 SR - - 4.43 V
pins with respect to VSS
Voltage at VDDM, VEXT, VFLEX VDDM SR - - 6.75 V upto 2.8h
and VEVRSB power supply pins - - 5.6 V upto 72h
with respect to VSS
Voltage on all analog and class VIN SR -0.7 - 6.75 V
S input pins with respect to VSS
3)
Voltage on all other input pins VIN SR -0.7 - 6.75 V

with respect to VSS 3)
Input current on any pin during IIN SR -10 - 10 mA
overload condition 4) 5)
Absolute maximum sum of all ΣIIN SR -100 - 100 mA
input circuit currents during
overload condition. 4)
1) Valid for cumulated for up to 2.8h and pulse forms followed a power supply switch on phase, where the rise
and fall times are related to the system capacities and coils.
2) Due to EVRC output voltage oscillation during switch off phase VDD can drop down to -0.72V. For VDD an input level down
to -0.72V during switch off phase will not cause any damage or reliability problem.
3) Voltages below VINmin have no Impact to the device reliabiltiy as Long as the times and currents defined in section Pin
Reliability in Overload for the affected pad(s) are not violated.
4) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may
damage the device.
5) The specified min. and max. values represent the current limits, which have to be maintained, in case of a short circuit
condition on the output of any Fast, RFast, Slow and Class S pad, not being used during operation.
This cover also output currents due to switching in operation for CL=200pF.
Data Sheet 404 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationPin Reliability in Overload
3.3 Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and
voltages that go beyond their own IO power supplies specification.
The following table defines overload conditions that will not cause any negative reliability impact if all the following
conditions are met:
• allowed time interval (defined in Note column) for overload condition is not exceeded. If no time limit is defined
the allowed time includes both ‘Operation Lifetime hours’ and ‘Inactive Lifetime hours’. The number of hours
in Table 3-77 and Table 3-78 are examples only and the applicable numbers are defined by the customer
profiles accepted by Infineon.
• Operating Conditions are met for
– pad supply levels
– temperature
If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters
functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still
possible in most cases but with relaxed parameters.
Table 3-2 Overload Parameters

Min. Typ. Max.
Input current on any digital pin IIN -5 - 5 mA except LVDS pins
during overload condition -15 1)
- 15 1)
mA except LVDS pins;
limited to max. 20
pulses with 1ms pulse
length
Input current on LVDS pin IINLVDS -3 - 3 mA
during overload condition
Input current on analog input IINANA -3 - 3 mA
pin during overload condition -5 - 5 mA limited to 60h over
lifetime
Absolute sum of all analog IINSA -20 - 20 mA
input currents for analog inputs
during overload conditon
Absolute maximum sum of all ΣIINS -100 - 100 mA
input circuit currents during
overload condition (digital and
analog combined)
Signal voltage over/undershoot VOUS VSS - 2 - VEXT/FLEX V limited to 60h over
at GPIOs +2 lifetime; Valid for non
LVDS and analoge
pads
Sum of all inactive device pin IIDS -100 - 100 mA
currents
Static pin output current IOUT CC - - 2.5 mA 100% duty cycle;
output driver = medium
- - 5 mA 100% duty cycle;
output driver = strong
Data Sheet 405 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-2 Overload Parameters (cont’d)

Min. Typ. Max.
Overload coupling factor for KOVDN CC - - 3*10-4 Overload injected on
digital inputs, negative GPIO non LVDS pad
and affecting neighbor
fast pads; -5mA < IIN <
0mA
- - 2*10-3 Overload injected on
GPIO non LVDS pad
slow pads VGASTE1N
and VGATE1P; -5mA
< IIN < 0mA
GPIO non LVDS pad
slow pads; -5mA < IIN <
0mA
- - 0.8 Overload injected on
LVDS RX pad and
affecting neighbor
LVDS pads
- - 0.5 Overload injected on
LVDS TX pad and
affecting neighbor
LVDS pads
Overload coupling factor for KOVDP CC - - 1.5*10-3 Overload injected on
digital inputs, positive GPIO non LVDS pad
GPIO non LVDS pads
- - 1 Overload injected on
LVDS RX pad and
affecting neighbor
LVDS pads
LVDS TX pad and
affecting neighbor
LVDS pads
Overload coupling factor for KOVAN CC - - 1*10-4 Analog inputs overlaid
analog inputs, negative 2) with slow pads or pull
down diagnostics; -
5mA < IIN < 0mA
- - 1*10-5 else; -5mA < IIN < 0mA
Data Sheet 406 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-2 Overload Parameters (cont’d)

Min. Typ. Max.
Overload coupling factor for KOVAP CC - - 2*10-4 Analoge inputs
analog inputs, positive 2) overlaid with slow pads
or pull down
diagnostics; 0mA < IIN
< 5mA
- - 2*10-5 else; 0mA < IIN < 5mA
1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters.
2) Overload coupling on analog inputs is caused by parasitic effects between pads, input multiplexers and surrounding
structures.
The given parameters have been verified for all permutations of channels. Also watch multiple connections of a pin to
several channels.
Data Sheet 407 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationOperating Conditions
3.4 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the
TC39x. All parameters specified in the following tables refer to these operating conditions, unless otherwise
noticed.
Digital supply voltages applied to the TC39x must be static regulated voltages.
All parameters specified in the following tables refer to these operating conditions (see table below), unless
otherwise noticed in the Note / Test Condition column.
Table 3-3 Operating Conditions

Min. Typ. Max.
SRI frequency fSRI SR - - 300 MHz
CPU Frequency (All CPUs) fCPUx SR - - 300 MHz
PLL0 output frequency fPLL0 SR 20 - 300 MHz
SPB frequency fSPB SR - - 100 MHz
FSI2 frequency fFSI2 SR - - 300 MHz
FSI frequency fFSI SR 20 - 100 MHz
GTM frequency fGTM SR - - 200 MHz
STM frequency fSTM SR - - 100 MHz
ERAY frequency fERAY SR - 80 - MHz
BBB frequency fBBB SR - - 150 MHz
VADC frequency fADC SR - - 160 MHz
ASCLIN Operating Frequency fASCLINx SR - - 200 MHz
CAN frequency fCAN SR - - 80 MHz
EBU operating frequency fEBU SR - - 160 MHz
I2C frequency fI2C SR - - 100 MHz
Operating MSC Frequency fMSC SR - - 200 MHz
PLL1 output frequency from fPLL1 SR 20 - 320 MHz
PER PLL
PLL2 output frequency from fPLL2 SR 20 - 200 MHz
PER PLL
QSPI Frequency fQSPI SR - - 200 MHz
ADAS clock frequency fADAS CC 200 - 300 MHz
MCANH frequency fMCANH CC - - 100 MHz
GETH frequency fGETH CC 150 - 200 MHz
Ambient Temperature TA SR -40 - 125 °C valid for all SAK
products
-40 - 150 °C valid for all SAL
products with package
Data Sheet 408 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-3 Operating Conditions (cont’d)

Min. Typ. Max.
Junction Temperature TJ SR -40 - 150 °C valid for all SAK
products
-40 - 170 °C valid for all SAL
products
Core Supply Voltage VDD SR 1.125 1) 1.25 1.375 2) V
ADC analog supply voltage VDDM SR 2.97 5.0 5.5 3) V
3)
Digital external supply voltage VEXT SR 4.5 5.0 5.5 V Nominal 5V Pad / Port
for pads and EVR Pin supply range. 5V
pad parameters are
valid.
2.97 3.3 3.63 V Nominal 3.3V Pad /
Port Pin supply range
with VDDP3 supplied
externally and EVR33
inactive. 3.3V pad
parameters are valid.
3.6 - 4.5 V Flash configured in
cranking mode; Flash
read operation with
reduced performance.
EVR33 active in low
voltage mode. 3.3V
pad parameters are
valid.
2.97 - 3.6 V Incase EVR33 is
active, Flash
configured in sleep
mode and execution
switched to RAM. 3.3V
pad parameters are
valid.
Digital supply voltage for EBU VEBU CC 2.97 3.3 3.63 V 3.3V pad parameters
are valid
4.5 5 5.5 V 5V pad parameters are
valid
Digital supply voltage for Flex VFLEX SR 2.97 - 4.0 V 3.3V pad parameters
port are valid
4.5 5.0 5.5 3) V 5V pad parameters are
valid
Digital supply voltage for Flash VDDP3 SR 2.97 3.3 3.63 4) V
2.6 - 3.63 V Flash configured in
cranking mode; Flash
read operation with
reduced performance.
Data Sheet 409 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-3 Operating Conditions (cont’d)

Min. Typ. Max.
Digital ground voltage VSS SR 0 - - V
Analog ground voltage for VDDM VSSM CC -0.1 0 0.1 V
5)
Digital external supply voltage VEVRSB SR 2.97 - 5.5 V
for EVR and during Standby
mode
Voltage to ensure defined pad VDDPPA CC 1.3 6) - - V
states
1) For VDD 1.08V ≤ VDD < 1.125V operation is still possible but with relaxed parameters.
2) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
5) VEVRSB supply voltage can drop down upto 2.6V during Standby mode. It is required to have a capictor of 100nF on VEVRSB
supply pin.
6) HWCFG[6] pin is latched and pull-up or tristate is activated at Port pins when VEXT has reached this level.
Limitation of Supply Voltage over Time

The maximum operation voltage for VEXT/FLEX/DDM supply rails is limited over the complete lifetime.
The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved
by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-4 Example Voltage Profile

VEXT/FLEX/DDM= Duration [h]
5.4 V < VEXT/FLEX/DDM ≤ 5.5 V ≤ 5% of lifetime
The maximum operation voltage for VDD supply rails is limited over the complete lifetime.
The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved
by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-5 Example Voltage Profile

VDD= Duration [h]
1.325 V < VDD ≤ 1.375 V ≤ 5% of lifetime
1.125 V < VDD ≤ 1.175V ≤ 5% of lifetime
Data Sheet 410 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical Specification5 V / 3.3 V switchable Pads
3.5 5 V / 3.3 V switchable Pads

Pad classes slow GPIO and fast GPIO support both Automotive Level (AL) or TTL level (TTL) operation.
Parameters are defined for AL operation and degrade in TTL operation.
Table 3-6 PORST Pad

Min. Typ. Max.
PORST pad Output current IPORST CC 13 - - mA VEXT = 2.97V; VPORST =
0.9V
Spike filter always blocked tSF1 CC - - 80 ns
pulse duration
Spike filter pass-through tSF2 CC 260 - - ns without additional
blocked pulse duration PORST Digtial Filter
active (PORSTDF =
0).
Input hysteresis 1) HYS CC 0.055 * - - V non of the neighbor
VEXT pads are used as
output;TTL (degraded,
used for CIF)
Pull-down current 2) IPDL CC - - |130| µA VIH; TTL (degraded,
used for CIF)
|15| - - µA VIL; TTL (degraded,
used for CIF)
Input leakage current IOZ CC -450 - 450 nA TJ≤150°C ; (0.1 * VEXT)
< VIN < (0.9 * VEXT)
-500 - 500 nA TJ≤150°C ;else
-900 - 900 nA TJ≤170°C ; (0.1 * VEXT)
< VIN < (0.9 * VEXT)
-950 - 950 nA TJ≤170°C ; else
Input high voltage level VIH SR 1.4 - - V TTL (degraded, used
for CIF); VEXT = 2.97V
2.0 - - V TTL; VEXT = 4.5V
Input low voltage level VIL SR - - 0.5 V TTL (degraded, used
for CIF); VEXT = 2.97V
- - 0.8 V TTL; VEXT = 4.5V
Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from
package to be added
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Data Sheet 411 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-7 Fast 5V GPIO

Min. Typ. Max.
On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL
= 2mA
31 55 80 Ohm strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2) tRF CC 1.6 - 3.2 ns CL = 25pF; driver =
strong sharp edge;
from 0.2 *
VEXT/FLEX/EVRSB to 0.8 *
VEXT/FLEX/EVRSB
4+0.55*C 4+0.75*C 12+1.0*C ns driver = medium;
L L L CL≤200pF
1.0+0.18* 2.5+0.27* 5.0+0.35* ns driver = strong edge =
CL CL CL medium; CL≤200pF
CL CL CL sharp ; CL≤200pF
Asymmetry of sending tTX_ASYM CC -1 - 1 ns CL; valid for all data
rates excluding clock
tolerance
Input frequency fIN CC - - 160 MHz
3)
Input hysteresis HYS CC 0.09 * - - V non of the neighbor
VEXT/FLEX/ pads are used as
EVRSB output; AL
0.075 * - - V non of the neighbor
EVRSB output; TTL
75 - - mV two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4) IPUH CC |30| - - µA VIH; AL or TTL
- - |130| µA VIL; AL or TTL
5)
Pull-down current IPDL CC - - |130| µA VIH; AL or TTL
|30| - - µA VIL; AL
|28| - - µA VIL; TTL
Data Sheet 412 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 3-7 Fast 5V GPIO (cont’d)

Min. Typ. Max.
Input leakage current IOZ CC -1100 - 1100 nA TJ ≤ 150°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB)
-2500 - 2500 nA TJ ≤ 150°C ; (0.1 *
VEXT/FLEX) < VIN < (0.9 *
VEXT/FLEX) ; LVDS_TX /
Fast pad type
-6000 - 6000 nA TJ ≤ 150°C ; LVDS_RX
/ Fast pad type ; else
-3200 - 3200 nA TJ ≤ 150°C ; LVDS_TX
-1500 - 1500 nA TJ ≤ 150°C ; else
-2000 - 2000 nA TJ ≤ 170°C ; (0.1 *
-4000 - 4000 nA TJ ≤ 170°C ; (0.1 *
Fast pad type
-13500 - 13500 nA TJ ≤ 170°C ; LVDS_RX
-5100 - 5100 nA TJ ≤ 170°C ; LVDS_TX
-2500 - 2500 nA TJ ≤ 170°C ; else
Input high voltage level VIH SR 0.7 * - - V AL
VEXT/FLEX/
EVRSB
2.0 - - V TTL
Input low voltage level VIL SR - - 0.44 * V AL
VEXT/FLEX/
EVRSB
- - 0.8 V TTL
Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms;
VEXT/FLEX/EVRSB =
constant; AL
package to be added
Pad set-up time to get an tSET CC - - 100 ns
software update of the
configuration active
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
Data Sheet 413 V 1.1 2019-09
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TC39x BC/BD-Step
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
Table 3-8 Fast 3.3V GPIO

Min. Typ. Max.
= 2mA
8mA
strong sharp edge;
from 0.2 *
VEXT/FLEX/EVRSB to 0.8 *
VEXT/FLEX/EVRSB
- - 5 ns CL = 25pF; driver =
strong sharp edge;
from 0.8V to 2.0V
(RMII)
2+0.57*C 5.5+0.75* 10+1.25* ns driver = medium;
L CL CL CL≤200pF
1.5+0.18* 1.5+0.28* 8+0.4*CL ns driver = strong edge =
CL CL medium; CL≤200pF
0.75+0.08 0.75+0.11 2.5+0.21* ns driver = strong edge =
*CL *CL CL sharp ; CL≤200pF
tolerance
3)
EVRSB output; AL
EVRSB output; TTL
EVRSB output;TTL (degraded,
used for CIF)
pads are used as
output with
driver=strong and
edge=sharp; AL
Data Sheet 414 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-8 Fast 3.3V GPIO (cont’d)

Min. Typ. Max.
4)
Pull-up current IPUH CC |17| - - µA VIH; AL and TTL
(degraded, used for
CIF)
|11| - - µA VIH; TTL
- - |80| µA VIL; AL and TTL and
TTL (degraded, used
for CIF)
Pull-down current 5) IPDL CC - - |105| µA VIH; AL and TTL
(degraded, used for
CIF)
- - |115| µA VIH; TTL
|19| - - µA VIL; AL and TTL
used for CIF)
-2500 - 2500 nA TJ ≤ 150°C ; (0.1 *
Fast pad type
-6000 - 6000 nA TJ ≤ 150°C ; LVDS_RX
-3200 - 3200 nA TJ ≤ 150°C ; LVDS_TX
-1500 - 1500 nA TJ ≤ 150°C ; else
-2000 - 2000 nA TJ ≤ 170°C ; (0.1 *
-4000 - 4000 nA TJ ≤ 170°C ; (0.1 *
Fast pad type
-13500 - 13500 nA TJ ≤ 170°C ; LVDS_RX
-5100 - 5100 nA TJ ≤ 170°C ; LVDS_TX
-2500 - 2500 nA TJ ≤ 170°C ; else
Data Sheet 415 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-8 Fast 3.3V GPIO (cont’d)

Min. Typ. Max.
VEXT/FLEX/
EVRSB
2.0 - - V TTL
1.4 - - V TTL (degraded, used
for CIF)
VEXT/FLEX/
EVRSB
- - 0.8 V TTL
- - 0.5 V TTL (degraded, used
for CIF)
Input low/high voltage level VILH SR 1.0 - 1.9 V RGMII; no hysteresis
available
VEXT/FLEX/EVRSB =
constant; AL
package to be added
Table 3-9 Slow 5V GPIO

Min. Typ. Max.
= 2mA
Rise / Fall time 1) 2) tRF CC 4+0.55*C 4+0.75*C 12+1*CL ns driver = medium edge
L L = medium ; CL≤200pF
1.5+0.25* 2.5+0.40* 7+0.55*C ns driver = medium edge
CL CL L = sharp ; CL≤200pF
tolerance
Data Sheet 416 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-9 Slow 5V GPIO (cont’d)

Min. Typ. Max.
3)
EVRSB output; AL
EVRSB output; TTL
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4) IPUH CC |30| - - µA VIH;AL or TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
- - |130| µA VIL; AL or TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
Pull-down current 5) IPDL CC - - |130| µA VIH; AL or TTL
|30| - - µA VIL; AL
Input leakage current IOZ CC -300 - 300 nA TJ ≤ 150°C; (0.1 *
-400 - 400 nA TJ ≤ 150°C; else
-600 - 600 nA TJ ≤ 170°C; (0.1 *
-750 - 750 nA TJ ≤ 170°C; else
-18000 - 18000 nA P32.0 and
P32.1;TJ≤150°C
-38000 - 38000 nA P32.0 and
P32.1;TJ≤170°C
VEXT/FLEX/
EVRSB
2.0 - - V TTL
VEXT/FLEX/
EVRSB
- - 0.8 V TTL
Data Sheet 417 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-9 Slow 5V GPIO (cont’d)

Min. Typ. Max.
VEXT/FLEX/EVRSB =
constant; AL
package to be added
Table 3-10 Slow 3.3V GPIO

Min. Typ. Max.
= 2mA
Rise / Fall time 1) 2) tRF CC 2+0.57*C 5.5+0.75* 10+1.25* ns driver = medium edge
L CL CL = medium ; CL≤200pF
2+0.30*C 3.5+0.50* 5+0.70*C ns driver = medium edge
L CL L = sharp ; CL≤200pF
tolerance
Input hysteresis 3) HYS CC 0.055 * - - V non of the neighbor
EVRSB output; AL
EVRSB output; TTL
EVRSB output;TTL (degraded,
used for CIF)
pads are used as
output with
driver=strong and
edge=sharp; AL
Data Sheet 418 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-10 Slow 3.3V GPIO (cont’d)

Min. Typ. Max.
4)
Pull-up current IPUH CC |17| - - µA VIH; AL and TTL
(degraded, used for
CIF); exept VGATE1P;
except VGATE1N and
TJ > 150°C
|11| - - µA VIH; TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
TTL (degraded, used
for CIF); exept
VGATE1P; except
VGATE1N and TJ >
150°C
(degraded, used for
CIF)
- - |115| µA VIH; TTL
used for CIF)
Input leakage current IOZ CC -300 - 300 nA TJ ≤ 150°C; (0.1 *
-400 - 400 nA TJ ≤ 150°C; else
-600 - 600 nA TJ ≤ 170°C; (0.1 *
-750 - 750 nA TJ ≤ 170°C; else
-18000 - 18000 nA P32.0 and
P32.1;TJ≤150°C
-38000 - 38000 nA P32.0 and
P32.1;TJ≤170°C
VEXT/FLEX/
EVRSB
2.0 - - V TTL
for CIF)
Data Sheet 419 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-10 Slow 3.3V GPIO (cont’d)

Min. Typ. Max.
VEXT/FLEX/
EVRSB
- - 0.8 V TTL
for CIF)
Input low/high voltage level VILH SR 1.0 - 1.9 V RGMII; no hysteresis
available
VEXT/FLEX/EVRSB =
constant; AL
package to be added
Table 3-11 RFast 5V GPIO

Min. Typ. Max.
= 2mA
8mA
strong sharp edge;
from 0.2 * VFLEX to 0.8
* VFLEX
4+0.55*C 4+0.75*C 12+1.0*C ns driver = medium;
L L L CL≤200pF
CL CL CL medium; CL≤200pF
CL CL CL sharp ; CL≤200pF
Asymmetry of sending tTX_ASYM CC -0.5 - 0.5 ns CL; valid for all data
tolerance
Data Sheet 420 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-11 RFast 5V GPIO (cont’d)

Min. Typ. Max.
3)
VFLEX pads are used as
output; AL
output; TTL
pads are used as
output with
driver=strong and
edge=sharp; AL
5)
|30| - - µA VIL; AL
VFLEX) < VIN < (0.9 *
VFLEX)
-2100 - 2100 nA TJ ≤ 150°C ; else
-3000 - 3000 nA TJ ≤ 170°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX)
-4000 - 4000 nA TJ ≤ 170°C ; else
VFLEX
2.0 - - V TTL
VFLEX
- - 0.8 V TTL
VFLEX = constant; AL
Pin capacitance CIO CC - 2 3.5 pF in addition 2.5pF from
package to be added
Data Sheet 421 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-12 RFast 3.3V pad

Min. Typ. Max.
On-Resistance of pad output RDSON CC 8 20 30 Ohm Driver = RGMII; IOH / OL
= 8mA
125 225 320 Ohm medium driver; IOH / OL
= 2mA
8mA
Input Duty Cycle fD SR 47.5 50 52.5
1) 2)
Rise / Fall time tRF CC 1.6 - 4.5 ns CL = 25pF; driver =
strong sharp edge;
from 0.2 * VFLEX to 0.8
* VFLEX
- - 5 ns CL = 25pF; driver =
strong sharp edge;
from 0.8V to 2.0V
(RMII)
- - 1 ns Driver = RGMII; from
20%V to 80%V;
CL=15pF
2+0.57*C 5.5+0.75* 10+1.25* ns driver = medium;
L CL CL CL≤200pF
1.5+0.18* 1.5+0.28* 8+0.4*CL ns driver = strong edge =
CL CL medium; CL≤200pF
0.75+0.08 0.75+0.11 2.5+0.21* ns driver = strong edge =
*CL *CL CL sharp ; CL≤200pF
Asymmetry of sending tTX_ASYM CC -0.4 - 0.4 ns CL; valid for all data
tolerance
Data Sheet 422 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-12 RFast 3.3V pad (cont’d)

Min. Typ. Max.
3)
output; AL
output; TTL
output;TTL (degraded,
used for CIF)
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4) IPUH CC |17| - - µA VIH; AL and TTL
(degraded, used for
CIF)
TTL (degraded, used
for CIF)
(degraded, used for
CIF)
- - |115| µA VIH; TTL
used for CIF)
VFLEX) < VIN < (0.9 *
VFLEX)
-2100 - 2100 nA TJ ≤ 150°C ; else
-3000 - 3000 nA TJ ≤ 170°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX)
-4000 - 4000 nA TJ ≤ 170°C ; else
VFLEX
2.0 - - V TTL
for CIF)
Data Sheet 423 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-12 RFast 3.3V pad (cont’d)

Min. Typ. Max.
VFLEX
- - 0.8 V TTL
for CIF)
VFLEX = constant; AL
Pin capacitance CIO CC - 2 3.5 pF in addition 2.5pF from
package to be added
Table 3-13 Class S 5V

Min. Typ. Max.
1)
VDDM pads are used as
output; AL
output; TTL
pads are used as
output with
driver=strong and
edge=sharp; AL
3)
|30| - - µA VIL; AL
Data Sheet 424 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-13 Class S 5V (cont’d)

Min. Typ. Max.
Input leakage current IOZ CC -150 - 150 nA TJ ≤ 150°C; else
-300 - 300 nA TJ ≤ 150°C; PDD
option available, or
AltRef option available
and EDSADC channel
connected, or two
EDSADC channels
connected
-300 - 300 nA TJ ≤ 170°C; else
-600 - 600 nA TJ ≤ 170°C; PDD
and EDSADC channel
connected, or two
EDSADC channels
connected
Input high voltage level VIH SR 0.7 * VDDM - - V AL
2.0 - - V TTL
VDDM
- - 0.8 V TTL
VDDM = constant; AL
package to be added
Table 3-14 Class S 3.3V

Min. Typ. Max.
Data Sheet 425 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-14 Class S 3.3V (cont’d)

Min. Typ. Max.
1)
output; AL
output; TTL
output; TTL (degraded
used for CIF)
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 2) IPUH CC |17| - - µA VIH; AL and TTL
(degraded, used for
CIF)
- - |80| µA VIL
3)
Pull-down current IPDL CC - - |105| µA VIH; AL and TTL
(degraded, used for
CIF)
- - |115| µA VIH; TTL
used for CIF)
-300 - 300 nA TJ ≤ 150°C; PDD
and EDSADC channel
connected
-300 - 300 nA TJ ≤ 170°C; else
-600 - 600 nA TJ ≤ 170°C; PDD
option available
Input high voltage level VIH SR 0.7 * VDDM - - V AL
2.0 - - V TTL
for CIF)
Data Sheet 426 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-14 Class S 3.3V (cont’d)

Min. Typ. Max.
VDDM
- - 0.8 V TTL
for CIF)
VDDM = constant; AL
package to be added
Table 3-15 Class D

Min. Typ. Max.
1) 1)
-300 - 300 nA TJ ≤ 150°C; PDD
and EDSADC channel
connected, or two
EDSADC channels
connected
-300 - 300 nA TJ ≤ 170°C; else
2) 2)
-600 - 600 nA TJ ≤ 170°C; PDD
and EDSADC channel
connected, or two
EDSADC channels
connected
package to be added
1) For AN11 100 nA need to be added.
2) For AN11 200 nA need to be added.
Data Sheet 427 V 1.1 2019-09
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TC39x BC/BD-Step
Data Sheet 428 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-16 ADC Reference Pads

Min. Typ. Max.
1)
Input leakage current for VAREF IOZ2 CC -2 - 2 1) µA TJ ≤ 150°C; VAREF <
VDDM; for EVADC; valid
for BGA292 and
BGA292 ADAS feature
set
-7 1) - 7 1) µA TJ ≤ 150°C; VAREF ≤
VDDM+50mV; for
EVADC; valid for
BGA292 and BGA292
ADAS feature set
-4 1) - 4 1) µA TJ ≤ 170°C; VAREF <
for BGA292 and
BGA292 ADAS feature
set
-14 1) - 14 1) µA TJ ≤ 170°C; VAREF ≤
VDDM+50mV; for
EVADC; valid for
BGA292 and BGA292
ADAS feature set
-1 2) - 1 2) µA TJ ≤ 150°C; VAREF <
for BGA516 and Bare
Die
-2 2) - 2 2) µA TJ ≤ 170°C; VAREF <
for BGA516 and Bare
Die
-3.5 2) - 3.5 2) µA TJ ≤ 150°C; VAREF ≤
VDDM+50mV; for
EVADC; valid for
BGA516 and Bare Die
-7 2) - 7 2) µA TJ ≤ 170°C; VAREF ≤
VDDM+50mV; for
EVADC; valid for
BGA516 and Bare Die
-2 3) - 2 3) µA TJ ≤ 150°C; VAREF <
VDDM; for EDSADC
-4 3) - 4 3) µA TJ ≤ 170°C; VAREF <
VDDM; for EDSADC
-6 3) - 6 3) µA TJ ≤ 150°C; VAREF ≤
VDDM+50mV; for
EDSADC
3) 3)
-12 - 12 µA TJ ≤ 170°C; VAREF ≤
VDDM+50mV; for
EDSADC
Data Sheet 429 V 1.1 2019-09
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TC39x BC/BD-Step
1) Limit is valid for VAREF2 pin.

2) Limit is valid for VAREF2 and VAREF3 pins each.
3) Limit is valid for VAREF1 pin.
Table 3-17 Driver Mode Selection for Slow Pads

PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting
X X 0 Speed grade 1 medium sharp edge (sm)
X X 1 Speed grade 2 medium medium edge (m)
Table 3-18 Driver Mode Selection for Fast Pads

X 0 0 Speed grade 1 Strong sharp edge (ss)
X 0 1 Speed grade 2 Strong medium edge (sm)
X 1 0 Speed grade 3 medium (m)
X 1 1 Speed grade 4 Reserved, do not use this combination
Table 3-19 Driver Mode Selection for RFast Pads

X 0 0 Speed grade 1 Strong sharp edge (ss)
X 0 1 Speed grade 2 Strong medium edge (sm)
X 1 0 Speed grade 3 medium (m)
X 1 1 Speed grade 4 RGMII function is active
Data Sheet 430 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationHigh performance LVDS Pads
3.6 High performance LVDS Pads

This LVDS pad type is used for the high speed chip to chip communication interface of the new TC39x. It compose
out of a LVDS pad and a fast pad.
CL = 2.5 pF for all LVDS parameters.
Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL)
Min. Typ. Max.
Output impedance R0 CC 40 - 140 Ohm Vcm = 1.0 V and 1.4 V
Rise time (20% - 80%) trise20 CC - - 0.75 1) ns ZL = 100 Ohm ±20%
@2pF external load
Fall time (20% - 80%) tfall20 CC - - 0.75 2) ns ZL = 100 Ohm ±20%
@2pF external load
Output differential voltage 3) VOD CC 240 - 330 mV RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=00
280 - 370 mV RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=01
320 - 410 mV RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=10
380 - 500 mV RT = 100 Ohm ± 1%;
LPCRx.VDIFFADJ=11
; Multi slave operation
Output voltage high VOH CC - - 1475 mV RT = 100 Ohm +/- 1%
VDIFFADJ=00 and 01
- - 1500 mV RT = 100 Ohm ± 1%
VDIFFADJ=10 and 11
Output voltage low VOL CC 925 - - mV RT = 100 Ohm ± 1%
VDIFFADJ=00 and 01
900 - - mV RT = 100 Ohm +/- 1%
VDIFFADJ=10 and 11
Output offset (Common mode) VOS CC 1125 - 1275 mV RT = 100 Ohm ± 1%
voltage
Input voltage range VI SR 0 - 1600 mV Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±10%
0 - 2400 mV Driver ground potential
RT = 100 Ohm ±20%
Input differential threshold Vidth SR -100 - 100 mV Driver ground potential
VDIFFADJ=10 and 11
-100 - 100 mV Driver ground potential
VDIFFADJ=00 and 01
Data Sheet 431 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL) (cont’d)
Min. Typ. Max.
Receiver differential input Rin CC 80 - 120 Ohm VI ≤ 2400 mV
impedance
Output differential voltage VODSM CC -5 - 20 mV RT = 100 Ohm ± 20%;
Sleep Mode 4) LPCRx.VDIFFADJ=xx
Delta output impedance dR0 SR - - 10 % Vcm = 1.0 V and 1.4 V
Change in VOS between 0 and dVOS CC - - 25 mV RT = 100 Ohm ±1%
1
Change in Vod between 0 and dVod CC - - 25 mV RT = 100 Ohm ±1%
1
Pad set-up time tSET_LVDS - 10 13 µs
CC
Duty cycle tduty CC 45 - 55 %
1) trise20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load.
2) tfall20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load.
3) Potencial violations of the IEEE Std 1596.3 are intended for the new multislave support feature. To be compliant to IEEE
Std 1596.3 LPCRx.VDIFFADJ has to be configure to 01.
4) Common Mode voltage of Tx is maintained.
Note: Driver ground potential difference is defined as driver-receiver potentital difference, that can result in a
voltage shift when comparing driver output voltage level and receiver input voltage level of a transmitted
signal.
Note: RT in table ‘LVDS - IEEE standard LVDS general purpose Link (GPL)’ is as termination resistor of the
receiver according to figure 3-5 in IEEE Std 1596.3-1996 and is represent in Figure 3-1 either by RIN or by
RT=100Ohm but not both.
default after start-up = CMOS function
Data Sheet 432 V 1.1 2019-09
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TC39x BC/BD-Step
Htotal=5nH
Cext=2pF Ctotal=3.5pF LVDS

Rin IN
RT=100Ohm
Htotal=5nH N
Ctotal=3.5pF
Cext=2pF
LVDS_Input_Pad_Model.vsd
Figure 3-1 LVDS pad Input model
Data Sheet 433 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationVADC Parameters
3.7 VADC Parameters

The accuracy of the converter results depends on the reference voltage range. The parameters in the table below
are valid for a reference voltage range of (VAREF - VAGND) >= 4.5 V. If the reference voltage range is below 4.5 V
by a factor of k (e.g. 3.3 V), the accuracy parameters increase by a factor of 1.1/k (e.g. 1.1 × 4.5 / 3.3 = 1.5).
Noise on supply voltage VDDM influences the conversion. The accuracy (error) parameters are defined for a supply
voltage ripple of below 20 mVpp up to 10 MHz (below 5 mVpp above 10 MHz).
Digital functions overlapping analog inputs influence accuracy.
The total unadjusted error (TUE) is defined without noise. The overall deviation depends on TUE and ENRMS
(depending on the noise distribution). Example: For a noise distribution of 4 sigma and ENRMS = 1.0 the additional
peak-peak noise error is ±(4 × 1.0) = 8 LSB12.
Fast compare operations are executed with 10-bit values.
The noise reduction feature improves the result by adding additional conversion steps. The conversion times,
therefore, increase accordingly (4 × tADCI + 3 × tADC for each of 1, 3, or 7 steps).
Table 3-21 VADC 5V

Min. Typ. Max.
EVADC IVR output voltage VDDK CC 1.15 - 1.35 V Measured at low
temperature.
Deviation of IVR output voltage dVDDK CC -2 - 2 % Based on device-
VDDK specific value
Analog reference voltage 1) VAREF SR 4.5 5.0 VDDM + V 4.5 V ≤ VDDM ≤ 5.5 V
0.05
2.97 3.3 VDDM + V 2.97 V ≤ VDDM < 4.5 V
0.05
Analog reference ground VAGND SR VSSM VSSM VSSM V VSSM and VAGND are
connected together
Analog input voltage range VAIN SR VAGND - VAREF V VAIN is limited by the
respective pad supply
voltage; see pin
configuration (buffer
type)
Converter reference clock fADCI SR 16 40 53.33 MHz 4.5 V ≤ VDDM ≤ 5.5 V
16 20 26.67 MHz 2.97 V ≤ VDDM < 4.5 V
2) 3)
Total Unadjusted Error TUE CC -4 - 4 LSB 12-bit resolution for
primary/secondary
groups, 10-bit
resolution for fast
compare channels
INL Error 2) EAINL CC -3 - 3 LSB
2)4)
DNL error EADNL CC -1 - 3 LSB
2)
Gain Error EAGAIN CC -3.5 - 3.5 LSB
2)3)
Offset Error EAOFF CC -4 - 4 LSB
RMS Noise 2)5) 6) ENRMS CC - 0.5 0.8 LSB Noise reduction level 3
- 0.5 1.0 LSB Standard conversion
Data Sheet 434 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-21 VADC 5V (cont’d)

Min. Typ. Max.
Reference input charge QCONV CC - - 20 pC VAIN = 0 V (worst
consumption per conversion case), precharging
(from VAREF) 7) 8) 9) disabled
- - 10 pC VAIN = 0 V (worst
case), precharging
enabled, VDDM - 5% <
VAREF < VDDM + 50 mV
Switched capacitance of an CAINS CC - 2.5 3.4 pF Input buffer disabled
analog input
Analog input charge QAINS CC - - 3.5 pC Primary groups and
consumption 10) fast compare
channels; VAIN = VAREF;
VDDM = 5.0 V; input
buffer enabled; TJ ≤
150°C
- - 3.8 pC Primary groups and
fast compare
channels; VAIN = VAREF;
VDDM = 5.0 V; input
buffer enabled; TJ >
150°C
- - 4.4 pC Secondary groups;
VAIN = VAREF; VDDM =
5.0 V; input buffer
enabled; TJ ≤ 150 °C
- - 4.8 pC Secondary groups;
VAIN = VAREF; VDDM =
5.0 V; input buffer
enabled; TJ > 150°C
Data Sheet 435 V 1.1 2019-09
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TC39x BC/BD-Step

Min. Typ. Max.
Sampling time tS SR 100 - - ns Primary group or fast
compare channel, 4.5
V ≤ VDDM ≤ 5.5 V; input
buffer disabled
300 - - ns Primary group or fast
buffer enabled
500 - - ns Secondary group, 4.5
buffer disabled
buffer enabled
200 - - ns Primary Group or fast
V ≤ VDDM < 4.5 V; input
buffer disabled
400 - - ns Primary group or fast
buffer enabled
buffer disabled
buffer enabled
Sampling time for calibration tSCAL SR 50 - - ns 4.5 V ≤ VDDM ≤ 5.5 V
100 - - ns 2.97 V ≤ VDDM < 4.5 V
Input buffer switch-on time tBUF CC - 0.4 1 µs
Wakeup time tWU CC - 0.1 0.2 µs Fast standby mode
- 1.6 3 µs Slow standby mode
Broken wire detection delay tBWR CC - 100 - cycles Result above 80% of
against VAREF full scale range, analog
input buffer disabled
Broken wire detection delay tBWG CC - 100 - cycles Result below 10% of
against VAGND full scale range, analog
input buffer disabled
Converter diagnostics unit RCSD CC 45 - 75 kOhm
resistance 11)
Converter diagnostics voltage dVCSD CC -10 - 10 % Percentage refers to
accuray VDDM
Data Sheet 436 V 1.1 2019-09
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TC39x BC/BD-Step

Min. Typ. Max.
Resistance of the multiplexer RMDU CC 30 - 42 kOhm 0 V ≤ VIN ≤ 0.9* VDDM,
diagnostics pull-up device Automotive Levels
56 - 78 kOhm 0 V ≤ VIN ≤ 0.9* VDDM,
TTL Levels
Resistance of the multiplexer RMDD CC 43 - 58 kOhm 0.1*VDDM ≤ VIN ≤ VDDM,
diagnostics pull-down device Automotive level
18 - 25 kOhm 0.1*VDDM ≤ VIN ≤ VDDM,
TTL level
Resistance of the pull-down RPDD CC - - 0.3 kOhm Measured at pad input
test device voltage VIN = VDDM / 2.
1) These limits apply to the standard reference input as well as to the alternate reference input.
2) Parameter depends on reference voltage range and supply ripple, see introduction.
Resulting worst case combined error is arithmetic combination of TUE and ENRMS.
Tests are done with postcalibration disabled, after completing the startup calibration.
3) Digital functions on analog inputs influence accuracy. The values for this parameter increase by 3 LSB12.
4) Monotonic characteristic, no missing codes when calibrated.
5) Parameter ENRMS refers to a 1 sigma distribution.
6) For analog inputs with overlaid digital GPIOs the RMS noise (ENRMS) can be up to 2 LSB 12 (soft switching for DC/DC
enabled).
7) For reduced reference voltages the consumed charge is reduced by factor k.
8) Maximum charge increases by 15 pC when BWD (Broken Wire Detection) is active.
9) Fast compare channels only consume 1/3 of the charge for a primary/secondary group.
10) For analog inputs with overlaid digital GPIOs or with PDD function this value increases by 1 pC.
11) Use a sample time of at least 1.1 µs to enable proper settling of the test voltage.
External Circuitry AD Converter

CHy (P)
(S)
RExt RAIN
...
CHx (P/S) (C)
CExt ZAIN CParasit CSWT CADC

VS VAIN VAREF
VAGND
CExt >> CParasit CParasit = CIO + CPackage CSWT + CADC = CAINS
ZAIN = (tS / Ceff) + RAIN Å Input impedance (P): Precharge sampling

RAIN = (tSmin / CAINS) / 10 Å Resistance of MUX (S): Sampling (direct)
CSWT = QAINS / VAREF Å Capacitance of switch tree (C): Conversion
Precharge enabled: Ceff = CSWT
Precharge disabled: Ceff = CAINS mc_evadc_equivpath.vsd
Figure 3-2 Equivalent Circuitry for Analog Inputs
Data Sheet 437 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationDSADC Parameters
3.8 DSADC Parameters

The DSADC parameters are valid only for voltage range 4.5 V <= VDDM <= 5.5 V.
These parameters describe the product properties and do not include external circuitry. The values are valid for
junction temperatures TJ <= 150°C if not defined explicitly.
Calibration is specified for gain factors 1 and 2, calibrated values refer to these settings.
The signal-noise ratio (SNR) is specified for differential inputs. For single ended operation the resulting signal-
noise ratio is reduced by 6 dB. For quasi-differential mode (i.e. using VCM) it is reduced by 6 dB for gain = 1 and
by 3 dB for gain= 2.
Table 3-22 DSADC 5V

Min. Typ. Max.
Common mode voltage bias RBIAS CC 105 130 155 kOhm On-chip variation ≤
resistance ±2.5%.
Positive reference voltage VAREF SR 4.5 - VDDM + V
0.05
Reference ground voltage VAGND SR VSSM - VSSM V VSSM and VAGND are
connected together
Reference load current IREF CC - 10 12 µA Per modulator
- - 14 µA Per modulator,
TJ>150°C
Common mode voltage dVCM CC -100 - 100 mV Deviation from
accuracy 1) selected voltage
Analog input voltage range VDSIN SR VSSM - 2 * VDDM V Differential;VDSxP -
VDSxN
VSSM - VDDM V Single ended
2)
Input current IRMS CC 7 10 15 µA Exact value (±1%)
available in UCB; valid
for gain = 1 and fMOD =
26.7 MHz
On-chip modulator clock fMOD SR 16 - 40 MHz
frequency
Gain error 3) 4) EDGAIN CC -0.2 5) ±0.15) 0.2 5) % TJ≤150°C; Target,
calibrated, VAREF
constant after
calibration; fMOD =
26.67 MHz
- ±0.25 - % TJ>150°C; VAREF
constant after
calibration; fMOD =
26.67 MHz
-1 - 1 % Calibrated once; fMOD
= 26.67 MHz
-2.5 - 2.5 % Uncalibrated; fMOD =
26.67 MHz
Data Sheet 438 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-22 DSADC 5V (cont’d)

Min. Typ. Max.
3) 5)
DC offset error EDOFF CC -5 - 5 5) mV Calibrated; fMOD =
26.67 MHz
-10 - 10 mV Calibrated once; fMOD
= 26.67 MHz
-30 - 30 mV Uncalibrated; fMOD =
26.67 MHz
Signal-Noise Ratio for SNR CC 80 - - dB TJ≤150°C; fPB = 30
differential input signals 2)6) 7) kHz; fMOD = 26.67 MHz
78 - - dB TJ≤150°C; fPB = 50
kHz; fMOD = 26.67 MHz
74 - - dB TJ≤150°C; fPB = 100
kHz; fMOD = 26.67 MHz
Signal-Noise Ratio degradation DSNR CC - - 3 dB TJ>150°C; Resulting
Signal-Noise Ratio
value is SNR - DSNR
Spurious-free dynamic range 3) SFDR CC 60 - - dB fMOD = 26.67 MHz
Output sampling rate fD CC 3.906 - 300 kHz 16 MHz / 4096, without
integrator
Pass band fPB CC 1.302 - 100 kHz Output data rate: fD =
fPB * 3; without
integrator
1.302 - 10 kHz Output data rate: fD =
fPB * 6; without
integrator
Pass band ripple dfPB CC -0.08 - 0.08 dB FIR filters enabled
Stop band attenuation SBA CC 40 - - dB 0.5 fD ... 1.0 fD
45 - - dB 1.0 fD ... 1.5 fD
50 - - dB 1.5 fD ... 2.0 fD
55 - - dB 2.0 fD ... 2.5 fD
60 - - dB 2.5 fD ... OSR/2 fD
DC compensation factor DCF CC -3 - - dB 10-5 fD, offset
compensation filter
enabled
(FCFGMx.OCEN =
001B)
Modulator settling time tMSET CC - - 20 µs After switching on,
voltage regulator
already running
1) On pins with overlaid GPIO function the max. limit increases by up to 25 mV due to leakage current for TJ > 150°C.
2) For detailed information, refer to the User Manual chapter.
3) This parameter is valid within the defined range of fMOD.
4) Gain mismatch error between the different EDSADC channels is within ±0.5%.
Data Sheet 439 V 1.1 2019-09
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TC39x BC/BD-Step
5) Recalibration needed in case of a temperature change >20ºC

6) These values are valid for an analog gain factor of 1. Subtract 3 dB for each higher gain factor.
7) For single ended input signals and gain1, the SNR is reduced by 6 dB.
Data Sheet 440 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationMHz Oscillator
3.9 MHz Oscillator

OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 16 MHz to 40 MHz crystals external
outside of the device. Support of ceramic resonators is also provided.
Table 3-23 OSC_XTAL

Min. Typ. Max.
Input current at XTAL1 IIX1 CC -70 - 70 µA VIN>0V ; VIN<VEXT
Oscillator frequency fOSC SR 4 - 40 MHz Direct Input Mode
selected, if shaper is
not bypassed
16 - 40 MHz External Crystal Mode
selected
Oscillator start-up time tOSCS CC - - 3 1) ms 20MHz ≤ fOSC and 8pF
load capacitance
Input voltage at XTAL1 2) VIX SR -0.7 - VEXT + 0.5 V If shaper is not
bypassed
Input amplitude (peak to peak) VPPX SR 0.3*VEXT - VEXT + 1.0 V If shaper is not
at XTAL1 bypassed; fOSC >
25MHz
0.35*VEXT - VEXT + 1.0 V If shaper is not
bypassed; fOSC ≤
25MHz
Internal load capacitor CL0 CC 1.30 1.40 1.55 pF enabled via bit
OSCCON.CAP0EN
OSCCON.CAP1EN
OSCCON.CAP2EN
OSCCON.CAP3EN
Internal load stray capacitor CXINTS CC 1.15 1.20 1.25 pF
between XTAL1 and XTAL2
Internal load stray capacitor CXTAL1 CC - 2.5 4 pF
between XTAL1 and ground
Duty cycle at XTAL1 3) DCX1 SR 35 - 65 % VXTAL1 = 0.5*VPPX
3)
Absolute RMS jitter at XTAL1 JABSX1 SR - - 28 ps 10 KHz to fOSC/2
3)
Slew rate at XTAL1 SRXTAL1 SR 0.3 - - V/ns Maximum 30%
difference between
rising and falling slew
rate
1) tOSCS is defined from the moment when the Oscillator Mode is set to External Crystal Mode until the oscillations reach an
amplitude at XTAL1 of 0.3 * VEXT.
This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease.
2) For supply (VEXT < 5.3V VIX) min could be down to -0.9V. For XTAL1 an input level down to -0.9V will not cause and damage
or riability problem operating with an external crystal.
Data Sheet 441 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationMHz Oscillator
3) Square wave input signal for XTAL1.
Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target
system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits
specified by the crystal or ceramic resonator supplier.
Data Sheet 442 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationBack-up Clock
3.10 Back-up Clock

The back-up clock provides an alternative clock source.
Table 3-24 Back-up Clock

Min. Typ. Max.
Back-up clock accuracy before fBACKUT CC 70 100 130 MHz VEXT≥2.97V
trimming
Back-up clock accuracy after fBACKT CC 98 100 102 MHz VEXT≥2.97V
trimming 1)
Standby clock fSB CC 25 70 110 kHz VEXT≥2.97V
1) A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms
for temperature and voltage drifts up to temperatures of 125 celcius
Data Sheet 443 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationTemperature Sensor
3.11 Temperature Sensor
Table 3-25 DTS PMS

Min. Typ. Max.
Measurement time for each tM CC - - 2.7 ms Measured from cold
conversion 1) power-on reset release
Calibration reference accuracy TCALACC CC -1 - 1 °C calibration points @
TJ=-40°C and
TJ=127°C
Accuracy over temperature TNL CC -2 - 2 °C TCALACC has to be
range added in addition
DTS temperature range TSR SR -40 - 170 °C
1) After warm reset tM is not restarted and is measured from last conversion.
Table 3-26 DTS Core

Min. Typ. Max.
Measurement time for each tM CC - - 2.7 ms Measured from cold
conversion 1) power-on reset release
Temperature difference ∆T CC -3 - 3 °C
between on chip temperature
sensors
Calibration reference accuracy TCALACC CC -2 - 2 °C calibration points @
TJ=-40°C and
TJ=127°C
Accuracy over temperature TNL CC -2 - 2 °C TCALACC has to be
range added in addition
DTS temperature range TSR SR -40 - 170 °C
1) After warm reset tM is not restarted and is measured from last conversion.
Data Sheet 444 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationPower Supply Current
3.12 Power Supply Current

The total power supply current defined below consists of leakage and switching component.
Application relevant values are typically lower than those given in the following table and depend on the customer's
system operating conditions (e.g. thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
The real (realistic) power pattern defines the following conditions:
• TJ = 150 °C
• fSRI = fCPUx = 300 MHz
• fGTM = 200 MHz
• fSPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx = 100 MHz
• VDD = 1.275 V
• VDDP3 / FLEX = 3.366 V
• VEXT / EVRSB / M = VDDM = 5.1 V
• all cores are active including four lockstep cores (IPC=0.6)
• the following modules are inactive: HSM, HSCT, GETH, Ethernet, PSI5, I2C, FCE, EBU, SPU, RIF, and MTU
The max power pattern defines the following conditions:
• TJ = 150 °C
• fGTM = 200 MHz
• VDD = 1.375 V
• VDDP3 / FLEX = 3.63 V
• VEXT / EVRSB / M = VDDM = 5.5 V
• all cores are active including four lockstep cores (IPC=1.2)
• the following modules are inactive: GETH, FCE, SPU, RIF, and MTU
The ADAS power pattern defines the following conditions:
• TJ = 125 °C
• fGTM = 100 MHz
• fSPU = 300 MHz; (FFT length =2048, complex windowing)
• VDD = 1.275 V
• VDDP3/EXT/FLEX/EVRSB = VDDM = 3.366 V
• CPU0 and CPU1 (IPC=1.2) and CPU2 (IPC=0.6) cores are active including three lockstep cores; CPU3
(IPC=0.6) is active without lockstep core
• Only EVADC0 and EVADC1 are active
• the following modules are inactive: CPU4, CPU5, HSM, HSCT, GETH, PSI5, I2C, FCE, EBU, MSC, DSADC,
and MTU
Data Sheet 445 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-27 Current Consumption

Min. Typ. Max.
∑ Sum of IDD core and IDDRAIL CC - - 1500 mA ADAS power pattern
peripheral supply currents (incl. - - 1640 mA max power pattern;
IDDPORST+ ∑ IDDCx0+ ∑ IDDCxx+ TJ=150°C
IDDGTM+IDDSB)
- - 1372 mA real power pattern;
TJ=150°C
TJ=160°C
IDD core current during active IDDPORST - - 300 mA VDD = 1.275V;
power-on reset (PORST pin CC TJ=125°C
held low). Leakage current of - - 575 mA VDD = 1.275V;
core domain. 1) TJ=150°C
- - 759 mA VDD = 1.275V;
TJ=160°C
- - 835 mA VDD = 1.275V;
TJ=165°C
∑ Sum of IDDP3 3.3 V supply IDDP3RAIL - - 50 2) mA ADAS power pattern
currents CC incl. Flash read current
and Dflash
programming current.
- - 60 2) mA max power pattern
incl. Flash read current
and Dflash
programming current.
- - 50 2) mA real power pattern incl.
Flash read current and
Dflash programming
current.
∑ Sum of external IEXT supply IEXTRAIL CC - - 60 mA max power pattern
currents (incl. - - 54 3)
mA real power pattern
IEXTFLEX+IEVRSB+IEXTLVDS)
IEXT and IFLEX supply current IEXTFLEX CC - - 22 1)4) 5) mA real power pattern with
port activity absent;
PORST output
inactive.
IEVRSB supply current 1) IEVRSB CC - - 8 mA real power pattern;
PMS/EVR module
current considered
without SCR and
Standby RAM during
RUN mode.
Data Sheet 446 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-27 Current Consumption (cont’d)

Min. Typ. Max.
∑ Sum of external IDDM supply IDDM CC - - 60 mA real power pattern;
currents (incl. sum of currents of
IDDMEVADC+IDDMEDSADC) EDSADC and EVADC
modules
∑ Sum of all currents (incl. IDDTOT CC - - 1536 mA real power pattern;
IEXTRAIL+IDDMRAIL+IDDx3RAIL+IDD) TJ=150°C
TJ=160°C
∑ Sum of all currents with DC- IDDTOTDC3 - - 980 mA real power pattern;
DC EVRC regulator active 6) CC EVRC reset settings
with 72% efficiency;
VEXT = 3.3V; TJ=160°C
∑ Sum of all currents with DC- IDDTOTDC5 - - 670 mA real power pattern;
DC EVRC regulator active 6) CC EVRC reset settings
with 72% efficiency;
VEXT = 5V; TJ=160°C
∑ Sum of all currents (SLEEP ISLEEP CC - - 38 mA All CPUs in idle, All
mode) 1) peripherals in sleep,
fSRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C
∑ Sum of all currents ISTANDBY CC - - 130 8) µA 32 kB Standby RAM
(STANDBY mode) drawn at block active. SCR
VEVRSB supply pin 7) inactive. Power to
remaining domains
switched off. TJ =
25°C; VEVRSB = 5V
Maximum power dissipation PD SR - - 2240 mW ADAS power pattern;
TJ=125°C
- - 3220 mW max power pattern;
TJ=150°C
- - 2500 mW real power pattern;
TJ=150°C
1) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22.
2) Realistic Pflash read pattern with 50% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common
decoupling capacitor of atleast 100nF for (VDDP3) is used. Continuous Dflash programming in burst mode with 3.3 V supply
and realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective
programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to x mA
for maximum x us which is handled by the decoupling and buffer capacitors. This parameter is relevant for external power
supply dimensioning and not for thermal considerations.
3) Limits are defined for real power pattern. For ADAS power pattern limit sum up to 40mA.
4) The current consumption includes only minimal port activity.
5) Limits are defined for real power pattern. For ADAS power pattern limit has to be multiplied by the factor 0.7.
6) The total current drawn from external regulator is estimated with 72% EVRC SMPS regulator efficiency. IDDTOTDCx is
calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents
and IDDM.
Data Sheet 447 V 1.1 2019-09
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TC39x BC/BD-Step
7) The same current limits apply also for the other power pattern.
8) ∑ Sum of all currents during RUN mode at VEVRSB supply pin is less than (IEVRSB + 4 mA Standby RAM current +
ISCRSB if SCR active). ∑ It is recommended to have atleast 100 nF decoupling capacitor at this pin. 32kB of Standby
SRAM contributes less than 10uA to ISTANDBY current.
Table 3-28 Module Current Consumption

Min. Typ. Max.
IDDP3 supply current for IDDP3PROG - - 25 mA Pflash 3.3V
programming of a Pflash or CC programming current
Dflash bank 1) adder when using
external 3.3V supply.
- - 9 2) mA Pflash 3.3V
programming current
adder when using
external 5V supply.
IEXT supply current added by IEXTLVDS CC - - 9 3) mA real power pattern; 6
1)
LVDS pads in LVDS mode pairs of LVDS pins
active with receive
function
- - 24 mA real power pattern; 6
pairs of LVDS pins
active with transmit
function
Data Sheet 448 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-28 Module Current Consumption (cont’d)

Min. Typ. Max.
∑ Sum of external IDDM supply IDDM CC - - 44 mA real power pattern;
currents (incl. current for EDSADC
IDDMEVADC+IDDMEDSADC) modules only and
EVADC modules are
inactive; 11 EDSADC
channels active
continuously.
- - 63 4) mA max power pattern;
current for EDSADC
modules only and
EVADC modules are
inactive; all EDSADC
channels active
continuously.
- - 16 5) mA real power pattern;
current for EVADC
modules only and
EDSADC modules are
inactive; 12 EVADC
modules active.
- - 20 6) mA max power pattern;
current for EVADC
modules only and
EDSADC modules are
inactive; all EVADC
modules active.
IDDP3 supply current for erasing IDDP3ERASE - - 25 mA Pflash 3.3V erasing
of a Pflash or Dflash bank CC current adder when
using external 3.3V
supply.
SCR 8-bit Standby Controller ISCRSB CC - - 7.5 7) mA SCR power pattern
current incl. PMS in STANDBY incl. PMS current
Mode drawn at VEVRSB supply consumption with
pin fback clock active;
fSYS_SCR = 20MHz;
TJ=150°C
- 0.150 - mA SCR power pattern
incl. PMS current
consumption with
fback inactive;
fSYS_SCR = 70kHz;
TJ=25°C
SCR 8-bit Standby Controller ISCRIDLE CC - - 3.5 mA real power pattern.
CPU in IDLE mode 8) CPU set into idle
mode.
Data Sheet 449 V 1.1 2019-09
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TC39x BC/BD-Step
1) The same current limits apply also for the other power pattern.
2) During Pflash programming at 5V, additional 3 mA is drawn at VEXT supply rail.
3) A single LVDS pair with receive function is limited to 1.5mA (tEXTLVDS).
4) A single DS channel instance consumes 4 mA.
5) EVADC current is limited to 3mA in "ADAS power pattern with 2 EVADC" at (IDDM).
6) A single VADC unit consumes 1.3 mA.
7) If SCR ADCOMP is activated, an additional 0.6 mA adder is to be considered.
8) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22.
Table 3-29 Module Core Current Consumption

Min. Typ. Max.
IDD core current of CPUx main IDDCx0 CC - - 70 mA max power pattern;
core with CPUx lockstep core IPC=1.2
inactive - - 45 mA real power pattern;
IPC=0.6
IDD core current of CPUx main IDDCxx CC - - IDDCx0 + mA max power pattern;
core with CPUx lockstep core 50 IPC=1.2
active - - IDDCx0 + mA real power pattern;
40 IPC=0.6
IDD core current added by GTM IDDGTM CC - - 160 mA max power pattern
TIMx, TOMx, ATOMx ,
MCSx active. 3
clusters at 200 MHz.
- - 60 mA TIMx, TOMx active at
100MHz. ATOMx ,
MCSx, DPLL inactive.
2 clusters at 100 MHz.
IDD core current added by HSM IDDHSM CC - - 20 1) mA max power pattern;
HSM running at
100MHz.
IDD core current added by SPU IDDSPU1 CC - - 360 2) mA CTRL.DIV = 00; SPU
@ 300 MHz; FFT
length 2048;
DATSRC=EMEM;
complex windowing
IDD core current added by SPU IDDSPU2 CC - - 310 2) mA CTRL.DIV = 00; SPU
@ 300 MHz; FFT
length 512;
DATSRC=EMEM;
complex windowing
IDD core dynamic current load IDDSPULJ1 - - 390 3) mA CTRL.DIV = 00; SPU
jump during IDDSPU1 pattern. CC @ 300 MHz; FFT
length 2048;
DATSRC=EMEM;
complex windowing
Data Sheet 450 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-29 Module Core Current Consumption (cont’d)

Min. Typ. Max.
IDD core dynamic current load IDDSPULJ2 - - 310 3) mA CTRL.DIV = 00; SPU
jump during IDDSPU2 pattern. CC @ 300 MHz; FFT
length 512;
DATSRC=EMEM;
complex windowing
IDD core dynamic current added IDDLBIST CC - - 150 4) mA LBIST Configuration A;
by LBIST 1.2V ≤ VDD
IDD core dynamic current added IDDMBIST CC - - 225 mA fMBIST = 300MHz;
by MBIST tMBIST < 6ms. MTU
Ganging procedure for
SRAM test and
initialization; VDD =
1.375V.
1) The current consumption includes basic HSM activity incl. AES module.
2) The current is estimated as the sum of the SPU base load current at clock activation and average current caused by SPU
dynamic activity as defined in the conditions. Secondary Voltage Monitor over-voltage threshold shall be set to VDD + 10%
and under-voltage threshold shall be set to VDD - 9% respectively.
During the SPU operational phase for IDDSPU1/2 usecase, the externally supplied VDD voltage has to be equal or greater than
1.225V (VDD nominal - 2%) for static accuracy part and the overall static and dynamic at the VDD supply pin shall be limited
to (VDD nominal -8%).
3) The dynamic current load jump during SPU activity as defined by the conditions observed at the VDD pin beyond a settling
time duration of 20 us.
4) LBIST is executed either during start-up phase or can be triggered by application software. Secondary voltage monitors
are inactive during the LBIST execution time (tLBIST).
During the start-up phase externally supplied VDD voltage has to be equal or greater than 1.2V (VDD nominal - 4%) for static
accuracy.
If VDD is supplied internally by EVRC, EVRC takes care not to violate the VDD 1.2V static under voltage limit.
3.12.1 Calculating the 1.25 V Current Consumption

The current consumption of the 1.25 V rail compose out of two parts:
• Static current consumption
• Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic current consumption
depends of the configured clocking frequencies and the software application executed. These two parts needs to
be added in order to get the rail current consumption.
(3.1)
I 0 = 5, 8871 --------- × e 0, 0246 × T J [ C ]

mA
C
(3.2)
I 0 = 16, 4863 --------- × e 0, 0232 × T J [ C ]

mA
C
Equation (3.1) defines the typical static current consumption and Equation (3.2) defines the maximum static
current consumption. Both functions are valid for VDD = 1.275 V.
Data Sheet 451 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationPower Supply Infrastructure and Supply Start-up
3.13 Power Supply Infrastructure and Supply Start-up
Data Sheet 452 V 1.1 2019-09
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TC39x BC/BD-Step
3.13.1 Supply Ramp-up and Ramp-down Behavior
3.13.1.1 Single Supply mode (a)
VEXT (externally supplied) 0 1 2 3 4 5

5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5 Primary cold PORST Reset Threshold
VLVDRST5 LVD Reset Threshold
VDDPPA HWCFG[6] latch
0V
PORST output deasserted when VDD,

VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)

PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDD (internally generated

by EVRC)
1.375 V
1.25 V
VRSTC Primary Reset Threshold
EVRC_tSTR
0V
VDDP3 (internally generated

by EVR33)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after EVR33_tSTR

VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
0V
tBP (incl. tEVRstartup)
T0 T1 T2 T3 T4 T5
Basic Supply & Clock EVRC & EVR33 Ramp-up User Code Execution
Firmware Execution Power Ramp-down phase
Infrastructure Phase fCPU0=100MHz default Startup_Diag_2 v
on firmware exit
Figure 3-3 Single Supply mode (a) - VEXT (5 V) single supply
Data Sheet 453 V 1.1 2019-09
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TC39x BC/BD-Step
VEXT = 5 V single supply mode. VDD and VDDP3 are generated internally by the EVRC and EVR33 internal
regulators.
• The rate at which current is drawn from the external regulator (dIEXT /dt) is limited during the basic
infrastructure and EVRx regulator start-up phase (T0 up to T2) to a maximum of 100 mA with 100 us settling
time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the
maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the
specification.
• Furthermore it is also ensured that the current drawn from the regulator (dIDD/dt) is limited during the Firmware
start-up phase (T3 up to T4) to a maximum of 100 mA with 100 us settling time.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
• PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA
(dIDD) is expected.
• The power sequence as shown in Figure 3-3 is enumerated below
– T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started .The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
– T2 refers to the point in time where consequently a soft start of EVRC and EVR33 regulators are initiated.
PORST (input) does not have any affect on EVR33 or EVRC output and regulators continue to generate
the respective voltages though PORST is asserted and the device is in reset state. The generated voltage
follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots.
– T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVRC and EVR33 regulators have ramped up.
PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU.
Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet
parameter).
– T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
– T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet 454 V 1.1 2019-09
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TC39x BC/BD-Step
3.13.1.2 Single Supply mode (e)
0 1 2 3 4 5
VEXT/VDDP3
(externally supplied)
LVD Reset release
HWCFG[1,2] latch
3.63 V
3.30 V
VRST5/
VRST33 Primary cold PORST Reset Threshold
VLVDRST5
LVD Reset Threshold
0V


VDD (internally generated

by EVRC)
1.375 V
1.25 V
tEVRstartup
(incl. tSTR)
EVRC is started with a delay after

VLVDRST5 level is reached at VEXT & EVRC_tSTR
0V
T0 T1 T2 T3 T4 T5
Basic Supply & Clock EVRC Ramp-up User Code Execution
Firmware Execution Power Ramp-down phase
Infrastructure Phase fC PU0=100MHz default Startup_Diag_4 v 0
on firmware exit
Figure 3-4 Single Supply mode (e) - (VEXT & VDDP3) 3.3 V single supply
VEXT = VDDP3 = 3.3 V single supply mode. VDD is generated internally by the EVRC regulator.
• The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet
parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual
waveform may not represent the specification.
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
Data Sheet 455 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
(dIDD) is expected.
available as the external supply ramps up. The bandgap and internal clock sources are started .The supply
– T2 refers to the point in time where consequently a soft start of EVRC regulator is initiated. PORST (input)
does not have any affect on EVRC output and regulators continue to generate the respective voltages
though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up
over the tSTR (datasheet parameter) time to avoid overshoots.
VRST33 and VRSTC supply voltage levels. EVRC regulator has ramped up. PORST (output) is de-
asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated.
The time between T1 and T3 is documented as tEVRstartup (datasheet parameter).
parameter).
thresholds.
Data Sheet 456 V 1.1 2019-09
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TC39x BC/BD-Step
3.13.1.3 External Supply mode (d)
VEXT (externally supplied) 0 1 2 3 4 5

5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
0V
VDD (externally supplied)

1.375 V
1.25 V
0V


VDDP3 (internally generated

by EVR33)
3.63 V
3.30 V
VRST33
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after EVR33_tSTR

VLVDRST5 level is reached at VEXT &
0V
T0 T1 T2 T3 T4 T5
Basic Supply & Clock EVR33 Ramp-up Phase Firmware Execution User Code Execution Power Ramp-down phase
Infrastructure fC PU0=100MHz default
on firmware exit Startup_Diag_1 v 0.3
Figure 3-5 External Supply mode (d) - VEXT and VDD externally supplied
VEXT = 5 V and VDD supplies are externally supplied. 3.3V is generated internally by the EVR33 regulator.
• External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is
defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDD rail. If VDD voltage
Data Sheet 457 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
rail is ramped up before VEXT; VDD supply overshoots during start-up shall be limited within the operational
voltage range.
• The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up
phase to a maximum of 100 mA with 100 us settling time.
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
(dIDD) is expected.
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
– T2 refers to the point in time where consequently a soft start of EVR33 regulator is initiated. PORST (input)
does not have any affect on EVR33 output and regulators continue to generate the respective voltages
though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up
over the tSTR (datasheet parameter) time to avoid overshoots.
VRST33 and VRSTC supply voltage levels. EVR33 regulators has ramped up. PORST (output) is de-
asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated.
The time between T1 and T3 is documented as tEVRstartup (datasheet parameter).
parameter).
thresholds.
Data Sheet 458 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
3.13.1.4 External Supply mode (h)
VEXT (externally supplied) 0 1 3 4 5

5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
0V
VDD (externally supplied)

1.375 V
1.25 V
0V
VDDP3 (externally supplied)
3.63 V
3.30 V
VRST33
0V PORST output deasserted when VDD,

tPOA time to ensure adequate time between reset releases
tBP
T0 T1 T3 T4 T5
Basic Supply & Clock Firmware Execution User Code Execution Power Ramp-down phase
Infrastructure fC PU0=100MHz default
on firmware exit Startup_Diag_3 v 0.4
Figure 3-6 External Supply mode (h) - VEXT, VDDP3 & VDD externally supplied
All supplies, namely VEXT, VDDP3 & VDD are externally supplied.
• External supplies VEXT, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards
to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The
slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDDP3 and VDD rails.
If smaller voltage rails are ramped up before VEXT; VDD and VDDP3 supply overshoots during start-up shall
be limited within the operational voltage ranges of the respective rails.
Data Sheet 459 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
• The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in
the Start-up phase to a maximum of 100 mA with 100 us settling time.
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
(dIDD) is expected.
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
VRST33 and VRSTC supply voltage levels. PORST (output) is de-asserted and HWCFG[3:5] pins are
latched on PORST rising edge by SCU. Firmware execution is initiated.
parameter).
– T5 refers to the point in time during the ramp-down phase when at least one of the externally provided
supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds.
Data Sheet 460 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationReset Timing
3.14 Reset Timing
Table 3-30 Reset

Min. Typ. Max.
Application Reset Boot Time tB CC - - 400 µs operating with max.
frequencies, with valid
BMI header
System Reset Boot Time tBS CC - - 1.1 ms RAM initialization and
HSM boot time are not
included, with valid
BMI header
Cold Power on Reset Boot tBP CC - - 3.1 ms dVEXT/dT=1V/ms.
Time 1) VEXT>VLVDRST5.
Boot time after Cold
PORST including EVR
ramp-up and Firmware
execution time; RAM
initialization and HSM
boot time are not
included.
- - 1.6 ms Firmware execution
time after PORST
release without EVR
ramp-up; RAM
initialization and HSM
boot time is not
included
Minimum cold PORST reset tEVRPOR CC 10 2) - - µs
hold time incase of power fail
event issued by EVR primary
monitors
PMS Infrastructure, EVRC and tEVRstartup - - 1 ms dV/dT=1V/ms. EVRC
EVR33 overall start-up time till CC and EVR33 active
cold PORST reset release
Minimum PORST active hold tPOA SR 1 3) - - ms
time externally after power
supplies are stable at operating
levels after start-up
Configurable PORST digital tPORSTDF CC 600 - 1200 ns
filter delay in addition to analog
pad filter delay
Warm Reset Sequencing Delay tWARMRSTSEQ - - 180 µs
CC
HWCFG pins hold time from tHDH CC 16 / fSPB - - ns
ESR0 rising edge
Data Sheet 461 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-30 Reset (cont’d)

Min. Typ. Max.
HWCFG pins setup time to tHDS CC 0 - - ns
ESR0 rising edge
Ports inactive after ESR0 reset tPI CC - - 8/fSPB ns
active
Ports inactive after PORST tPIP CC - - 150 ns
reset active
Hold time from PORST rising tPOH SR 150 - - ns
edge
Setup time to PORST rising tPOS SR 0 - - ns
edge
Warm PORST reset boot time tBWP CC - - 1.5 ms without RAM
initalization
LBIST execution time tLBIST CC - - 6 ms LBIST Configuration A;
extending the boot time 1.2V ≤ VDD
SCR reset boot time tSCR CC - - 5 µs User Mode 0
- - 16 µs User Mode 1
- 13.3 - µs WDT double bit ECC,
soft reset
Minimum external supplies tSUPHOLD CC - - 250 µs external supplies are
hold time after warm reset VEVRSB, VEXT, VFLEX,
assertion VEBU, VDDM, VDDP3 and
VDD
1) RAM initialization add 500µs in addition.
2) Cold PORST reset is driven by uC and maintained in an extended voltage range between VDDPPA limit and absolute
maximum rating voltage limits.
3) The reset release on supply ramp-up or supply restoration is delayed by a voltage hysteresis of 1.5% (default value) above
the undervoltage reset limit implemented on VEXT, VDDP3 and VDD rails. This mechanism helps to avoid multiple
consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released.
Data Sheet 462 V 1.1 2019-09
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TC39x BC/BD-Step
VDDP V D D PPA VD D PPA
V D D PR
VDD
tPOA
tPOA
PORST Cold Warm
ESR0
tP I t PI
tP IP
Pads Tristate Z / pullup H Programmed Z/ H Programmed Z /H Programmed

Pad- Pad-
state state
undefined undefined
t P OS t P OS
TRST t P OH tP OH
TESTMODE
t HDH t HDA t HDH t HDA t HDH
HWCFG power -on config config config
reset_beh_aurix
Figure 3-7 Power, Pad and Reset Timing
Data Sheet 463 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationEVR
3.15 EVR
Table 3-31 EVR33 LDO

Min. Typ. Max.
1)
Input voltage range VIN SR 3.60 - 5.50 V Normal RUN mode
2)
2.97 - 5.50 V Low voltage cranking
mode
Output voltage operational VOUT CC 2.97 3.3 3.63 V Normal RUN mode
range including load/line 2.60 3.3 3.63 V Low voltage cranking
regulation and aging 3) mode; IDDP3=50mA
Output VDDx3 static voltage VOUTT CC 3.225 3.3 3.375 V Normal RUN mode
accuracy after trimming and 2.78 3.3 3.375 V Low voltage cranking
aging without dynamic load/line mode; IDDP3=50mA
regulation.
Output buffer capacitance on COUT SR 1.45 2.2 3 µF
VOUT
Output buffer capacitor ESR COUTESR SR - - 100 4) mOhm f > 0.5MHz; f < 10MHz
Maximum output current of the IMAX CC 60 5) - - mA Normal RUN mode
regulator
Startup time tSTR CC - 500 1000 µs Normal RUN mode
6)
External VIN supply ramp dVin/dt SR - 1 - V/ms
Ripple on Output Voltage ∆VOUTTC - - 33 mV VEXT ≥ 2.97V ; VEXT ≤
CC 5.5V ; IOUTTC ≥ 10mA ;
IOUTTC ≤ 60mA;
∆VOUTTC = (peak to
peak ripple / 2)
Load step response 7) dVout/dIout -165 - - mV Normal RUN mode;
CC dI=10 to 60mA;
dt=20ns; Tsettle=20us
- - 165 mV Normal RUN mode;
dI=60 to 10mA;
-180 - - mV Low voltage cranking
mode; dI=10 to 50 mA;
- - 180 mV Low voltage cranking
mode; dI=50 to 10mA;
Data Sheet 464 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-31 EVR33 LDO (cont’d)

Min. Typ. Max.
Line step response dVout/dVin - - 40 mV dVin/dT=1V/ms; dV=
CC 3.6 to 5V; IMAX=60mA;
∆VOUTTC is included
-40 - - mV dVin/dT=1V/ms; dV= 5
to 3.6V; IMAX=60mA;
∆VOUTTC is included
- - 280 mV dVin/dT=50V/ms; dV=
3.6 to 5V; IMAX=60mA
-165 - - mV dVin/dT=50V/ms; dV=
5 to 3.6V; IMAX=60mA
1) A maximum pass device dropout voltage of 300mV is included in the minimum input voltage to ensure optimal pass device
performance during normal operation.
2) VEXT Input voltage drop up to 2.97V leading to VDDP3 output voltage drop upto 2.6V can be tolerated if Flash is switched
before to low performance mode.
3) No external inductive load permissible if EVR33 is used.
4) It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100
mOhm. An additional decoupling capacitor of 100nF shall be located close to the pin before Cout.
5) IMAX is limited to 40 mA incase of Low voltage mode (cranking case) with on chip pass devices. In case EVR33 is not
used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during
power sequencing 3.3V is supplied before 5V by external regulator.
6) EVR is robust against residual voltage ramp-up starting between 0 - 2.97 V. A VEXT voltage ramp range between 0.5V/min
upto 120V/ms is covered in robustness validation. The generated voltage itself follows a soft ramp-up over the tSTR time
to avoid overshoots.
7) Settling time is defined until output voltage is within +-1% of the mean(VOUTT) of the individual device.
Table 3-32 Supply Monitors

Min. Typ. Max.
Primary Undervoltage Reset VRST33 CC - - 3.00 V by reset release before
threshold for VDDP3 before EVR trimming on
trimming 1) supply ramp-up
Primary undervoltage reset VRSTC CC - - 1.138 V by reset release before
threshold for VDD before trimming on supply
trimming ramp-up including 2
LSB voltage
Hysteresis
VEXT primary undervoltage VEXTPRIUV 2.86 2.92 2.97 V VEXT = Undervoltage
monitor accuracy after CC cold PORST Primary
trimming 2) Monitor Threshold
VDDP3 primary undervoltage VDDP3PRIUV 2.86 3) 2.90 2.97 V VDDP3 =
monitor accuracy after CC Undervoltage cold
trimming 2) PORST Primary
Monitor Threshold
Data Sheet 465 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-32 Supply Monitors (cont’d)

Min. Typ. Max.
3)
VDD primary undervoltage VDDPRIUV 1.08 1.105 1.125 V VDD = Undervoltage
monitor accuracy after CC cold PORST Primary
trimming 2) Monitor Threshold
EVR primary monitor tPRIUV CC - - 300 ns The supply ramp / line
measurement latency for a new jump slope is limited to
supply value 50V/ms for VEXT, VDDP3
and VDD rails.
VEXT, VDDM & VEVRSB secondary VEXTMON CC 3.2 3.3 3.4 V SWDxxVAL,
supply monitor accuracy after VDDMxxVAL &
trimming 4) 5) SBxxVAL monitoring
threshold=3.3V=90h(
OV,UV).
EVRMONFILT.SWDFI
L=1.
4.5 4.6 4.7 V SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=4.6V=C8h(
UV)/C9h(OV).
EVRMONFILT.SWDFI
L=1
5.3 5.4 5.5 V SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5.4V=EAh(
UV)/ECh(OV).
EVRMONFILT.SWDFI
L=1
4.9 5.0 5.1 V SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5V=D9h(UV
)/DAh(OV).
EVRMONFILT.SWDFI
L=1
Data Sheet 466 V 1.1 2019-09
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TC39x BC/BD-Step

Min. Typ. Max.
VDDP3 secondary supply VDDP3MON 2.97 3.035 3.1 V EVR33xxVAL
monitor accuracy after CC monitoring
trimming 5) threshold=3.035V=CB
h(UV)/CCh(OV).
EVRMONFILT.EVR33
FIL = 3.
3.235 3.30 3.365 V EVR33xxVAL
monitoring
threshold=3.3V=DDh(
OV,UV).
EVRMONFILT.EVR33
FIL = 3.
3.5 3.565 3.63 V EVR33xxVAL
monitoring
threshold=3.565V=EE
h(UV)/EFh(OV).
EVRMONFILT.EVR33
FIL = 3.
VDD & VDDPD secondary supply VDDMON CC 1.125 1.15 1.175 V EVRCxxVAL &
monitor accuracy after PRExxVAL monitoring
trimming 5) threshold=1.15V=C7h(
UV)/C8h(OV).
EVRMONFILT.EVRC
FIL = 1.
1.225 1.25 1.275 V EVRCxxVAL &
PRExxVAL monitoring
threshold=1.25V=D9h(
OV,UV).
EVRMONFILT.EVRC
FIL = 1.
1.325 1.35 1.375 V EVRCxxVAL &
PRExxVAL monitoring
threshold=1.35V=EAh
(UV)/EBh(OV).
EVRMONFILT.EVRC
FIL = 1.
VEXT LVD Primary VLVDRST5 2.3 - 2.72 V Power-down
undervoltage reset Monitor CC 2.4 - 2.75 V Power-up
threshold
VEVRSB LVD Primary VLVDRSTSB 2.18 - 2.47 V Power-down
undervoltage reset Monitor CC 2.21 - 2.5 V Power-up
threshold
VEXT and VEVRSB PBIST primary VPBIST5 CC 5.63 - - V
overvoltage Monitor threshold
Data Sheet 467 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Min. Typ. Max.
Primary undervoltage reset VRST5 CC - - 3.0 V by last cold PORST
threshold for VEXT before release on supply
trimming ramp-up including
voltage hysteresis.
EVR secondary monitor tMON CC - - 3.2 µs HPOSC and SHPBG
measurement latency for all 6 bandgap trimmed.
supply rails Filter inactive.
1) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold
and by a voltage hysteresis of 1.5% above the undervoltage reset limit. These mechanisms serve as hysteresis to avoid
multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is
released. The reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply
is provided externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin.
2) The monitor tolerances constitute the inherent variation of the band gap and ADC over process, voltage and temperature
operational ranges. The VxxPRIUV parameters are device individually tested in production with +-1% tolerance about the
VxxPRIUV limits. All voltages are measured on pins.
3) VRSTxx parameters are relevant only for the first cold PORST release. Later the reset levels are trimmed by the Firmware
and reflected as VxxPRIUV parameters before device is used with full performance. The cold PORST is released with a
voltage hysteresis on all the primary monitors to avoid consecutive PORST toggling behavior.
4) In case the application is using 3.3V single supply (Single Supply mode (e), i.e. VEXT and VDDP3 are shorted together),
it is recommended to use secondary supply monitoring on channel VDDP3, because of the better accuracy of parameter
VDDP3MON.
5) To monitor voltage level not provided in conditions the values for OV and UV thresholds can be generated by a linear
interpolation or extrapolation based on the given points.
Table 3-33 Supply Ramp

Min. Typ. Max.
External VEXT & VEVRSB supply dVEXT/dt 8.3E-6 1 100 V/ms
ramp-up and ramp-down slope SR
1) 2) 3)
External VDDP3 supply ramp-up dVDDP3/dt 8.3E-6 1 100 V/ms

and ramp-down slope 1)3) SR
External VDD supply ramp-up dVDD/dt 8.3E-6 1 100 V/ms
External VDDM supply ramp-up dVDDM/dt 8.3E-6 1 100 V/ms
1) The device is robust against residual voltage ramp-up starting between 0 - 2.97 V for VEXT, VEVRSB, VDDP3 and VDDM
and 0-1 V for VDD. A voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation.
2) Also valid incase EVR33 or EVRC is used. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid
overshoots.
3) The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification.
Up to 1000000 power-cycles, matching the limits defined in the table’Supply Ramp’, are allowed for TC39x, without
any restriction to reliability.
Data Sheet 468 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-34 EVRC SMPS

Min. Typ. Max.
Input VEXT Voltage range VIN SR 2.97 - 5.5 V Start-up VEXT voltage
> 2.6 V
SMPS regulator output voltage VDDDC CC 1.125 - 1.375 V VEXT ≥ 2.97V ; VEXT ≤
range including load/line 5.5V ; IDDDC ≥ 1mA ;
regulation and aging IDDDC ≤ 1.5A ;
untrimmed
SMPS regulator static voltage VDDDCT CC 1.225 1.25 1.275 V VEXT ≥ 2.97V ; VEXT ≤
output accuracy after trimming 5.5V ; IDDDC ≥ 1mA ;
without dynamic load/line IDDDC ≤ 1.5A
regulation.
Programmable switching fDCDC SR 1.6 1.82 2.0 MHz Start-up frequency
frequency switches from 500 KHz
in open loop operation
to 1.82 MHz in closed
loop Operation.
- 0.8 - MHz Start-up frequency
switches from 500 KHz
in open loop operation
to 1.82 MHz in closed
loop Operation. 0.8
MHz to be set in SW.
Startup time tSTRDC CC - - 900 µs SMPS Start-up Mode.
It is is defined beween
VEXTPRIUV reset
threshold till PORST
release, on condition
that all other PORST
requirements were
released before. ISTART
< 700mA.
Switching frequency ∆fDCSPR CC - 1.8% - MHz
modulation spread
Maximum ripple at IMAX ∆VDDDC CC - - 16 mV VEXT ≥ 2.97V ; VEXT ≤
5.5V ; IDDDC ≥ 300mA ;
IDDDC ≤ 1.5A ; ∆VDDDC
= (Peak to Peak ripple
/ 2)
No load current consumption of IDCNL CC - 15 19 mA fDCDC=1.82MHz;
SMPS regulator IDDDC=ISLEEP; VEXT >
2.97 V; TJ=25°C
- 5 - mA LPM mode;
IDDDC=ISLEEP; VEXT >
2.97 V; TJ=25°C
Data Sheet 469 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-34 EVRC SMPS (cont’d)

Min. Typ. Max.
SMPS regulator load transient dVDDDCT / -50 - 87 mV dI < -450mA ;
response dlOUT CC IDDDC=500-1500mA;
tr=0.1us; tf=0.1us;
VDDDC=1.25V;
Tsettle=100 us
-100 - 145 mV dI < -700mA ;
IDDDC=750-1500mA;
tr=0.1us; tf=0.1us;
VDDDC=1.25V;
Tsettle=100 us
-26 - 26 mV dI < 100mA ;
IDDDC=50-1500mA;
tr=0.1us; tf=0.1us;
VDDDC=1.25V;
Tsettle=20us;
Maximum output current IMAX CC 100 - - mA LPM mode. Typical
current in LPM Mode =
ISLEEP
1.5 - - A limited by thermal
constraints and
component choice
SMPS regulator line transient dVDDDCT / -75 - 75 mV dV/dT=120V/ms; dV <
response dVIN CC 2.97 - 5.5V ; IDDDC=50-
1500mA;
-12.5 - 12.5 mV dV/dT=1V/ms; dV <
2.97 - 5.5V ; IDDDC=50-
1500mA;
SMPS regulator efficiency nDC CC - 80 - % VIN=3.3V;
IDDDC=1500mA;
fDCDC=1.82MHz
- 75 - % VIN=5V;
IDDDC=1500mA;
fDCDC=1.82MHz
Input Synchronisation fDCDCSYNC 1.6 1.82 2.0 MHz
frequency SR
Table 3-35 EVRC SMPS External components

Min. Typ. Max.
External output capacitor value COUT SR 20.8 32 43.2 µF IDDDC=1.5A; fDDDC =
1)
0.8MHz
15.4 22 29.7 µF IDDDC=1.5A; fDDDC =
1.82MHz
Data Sheet 470 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-35 EVRC SMPS External components (cont’d)

Min. Typ. Max.
External output capacitor ESR COUT_ESR - - 50 mOhm f≥0.5MHz ; f≤10MHz
SR - - 100 Ohm f=10Hz
1)
External input capacitor value CIN SR 6.5 10 13.5 µF IDDDC=1.5A
External input capacitor ESR CIN_ESR SR - - 50 mOhm f≥0.5MHz ; f≤10MHz
- - 100 Ohm f=100Hz
External inductor value LDC SR 3.29 4.7 6.11 fDCDC=0.8MHz
2.31 3.3 4.29 µH fDCDC=1.82MHz
External inductor DCR LDC_DCR SR - - 0.2 Ohm
P + N-channel MOSFET logic VLL SR - - 2.5 V
level
P + N-channel MOSFET drain |VBR_DS| SR +7 - - V NMOS - VGS = 0.
source breakdown voltage - - -7 V PMOS - VGS = 0.
P + N-channel MOSFET drain RON SR - - 150 mOhm IDDDC=1.5A;
source ON-state resistance |VGS|=2.5V ; TA=25°C
P + N-channel MOSFET Gate QG SR - - 8 nC IDDDC=1.5A; NMOS-
Charge |VGS|=5V; 1.5A pulsed
drain current
-8 - - nC IDDDC=1.5A; PMOS-
|VGS|=5V; 1.5A pulsed
drain current
External Inductor Saturation ∆ISAT SR 400 - - mA The saturation current
Current Margin of the coil must be
larger than IDDDC +
∆ISAT
P + N-channel MOSFET Gate VGSTH SR - 1 - V NMOS
threshold voltage - -1 - V PMOS
N-channel MOSFET reverse VRDN SR - 0.8 - V
diode forward voltage
1) Capacitor min-max range represent typical +-35% tolerance including DC bias effect. The trace resistance from the
capacitor to the supply or ground rail should be limited to 25 mOhm.
Data Sheet 471 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationSystem Phase Locked Loop (SYS_PLL)
3.16 System Phase Locked Loop (SYS_PLL)
Table 3-36 PLL System

Min. Typ. Max.
DCO Input frequency range fREF CC 10 - 40 MHz
Modulation Amplitude MA CC 0 - 2 %
Peak Period jitter DP CC -200 - 200 ps without modulation
(PLL output frequency)
Peak Accumulated Jitter DPP CC -5 - 5 ns without modulation
Total long term jitter JTOT CC - - 11.5 ns including modulation;
MA 1.25%; fREF 20MHz
System frequency deviation fSYSD CC - - 0.01 % with active modulation
DCO frequency range fDCO CC 400 - 800 MHz
PLL lock-in time tL CC 4 - 100 µs
Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet 472 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationPeripheral Phase Locked Loop (PER_PLL)
3.17 Peripheral Phase Locked Loop (PER_PLL)
Table 3-37 PLL Peripheral

Min. Typ. Max.
Peak Accumulated jitter at DPP CC -1000 - 1000 ps Peak only
SYSCLK pin
Peak accumulated jitter DPPI CC -700 - 700 ps Peak only
RMS Accumulated jitter DRMS CC -100 - 100 ps measured over 1 µs;
fREF = 20 MHz and fDCO
= 640 MHz or fREF = 25
MHz and fDCO = 800
MHz
Peak Period jitter DP CC -200 - 200 ps fDCO = 640 MHz or fDCO
= 800 MHz
Absolute RMS jitter (PLL out) JABS10 CC -125 - 125 ps fREF = 10 MHz; fDCO =
640 MHz
640 MHz
800 MHz
DCO frequency range fDCO CC 400 - 800 MHz
DCO input frequency range fREF CC 10 - 40 MHz
PLL lock-in time tL CC 4 - 100 µs
Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet 473 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationAC Specifications
3.18 AC Specifications
All AC parameters are specified for the complete operating range defined in Chapter 3.4 unless otherwise noted
in column Note / Test Condition.
Unless otherwise noted in the figures the timings are defined with the following guidelines:
VEXT/FL EX / VD D P3
90% 90%
10% 10%
VSS
tr tf
rise_fall
Figure 3-8 Definition of rise / fall times
VEXT/FL EX / VD D P3
VEXT/FL EX / VD D P3 Timing VEXT /FL EX / VD D P3

Reference
2 Points 2
VSS
timing_reference
Figure 3-9 Time Reference Point Definition
Data Sheet 474 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationJTAG Parameters
3.19 JTAG Parameters

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module
is fully compliant with IEEE1149.1-2000.
Table 3-38 JTAG

Min. Typ. Max.
TCK clock period t1 SR 50 - - ns
TCK high time t2 SR 10 - - ns
TCK low time t3 SR 10 - - ns
TCK clock rise time t4 SR - - 4 ns
TCK clock fall time t5 SR - - 4 ns
TDI/TMS setup to TCK rising t6 SR 6.0 - - ns
edge
TDI/TMS hold after TCK rising t7 SR 6.0 - - ns
edge
TDO valid after TCK falling t8 CC 3.0 - - ns CL≤20pF
edge (propagation delay) - - 25 ns CL≤50pF
TDO hold after TCK falling t18 CC 2 - - ns
edge
TDO high impedance to valid t9 CC - - 25 ns CL≤50pF
from TCK falling edge
TDO valid output to high t10 CC - - 25 ns CL≤50pF
impedance from TCK falling
edge
t1
0.9 VEXT
0.5 VEXT
0.1 VEXT
t5 t4
t2 t3
MC_ JTAG_ TCK

Figure 3-10 Test Clock Timing (TCK)
Data Sheet 475 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationJTAG Parameters
TCK
t6 t7
TMS
t6 t7
TDI
t9 t8 t1 0
TDO
t18
MC_JTAG
Figure 3-11 JTAG Timing
Data Sheet 476 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationDAP Parameters
3.20 DAP Parameters

The following parameters are applicable for communication through the DAP debug interface.
Table 3-39 DAP

Min. Typ. Max.
DAP0 clock rise time t14 SR - - 1 ns f=160MHz
- - 4 ns f=40MHz
- - 2 ns f=80MHz
DAP0 clock fall time t15 SR - - 1 ns f=160MHz
- - 4 ns f=40MHz
- - 2 ns f=80MHz
DAP1 setup to DAP0 rising t16 SR 4 - - ns
edge 5 - - ns f=40MHz
DAP1 hold after DAP0 rising t17 SR 2 - - ns
edge
DAP1 valid per DAP0 clock t19 CC 4 - - ns CL=20pF ; f=160MHz
period 8 - - ns CL=20pF ; f=80MHz
10 - - ns CL=50pF ; f=40MHz
DAP0 high time t12 SR 2 - - ns
DAP0 low time t13 SR 2 - - ns
DAP0 clock period t11 SR 6.25 - - ns
Table 3-40 SCR DAP

Min. Typ. Max.
DAP0 clock rise time t14 SR - - 8 ns f=20MHz
DAP0 clock fall time t15 SR - - 8 ns f=20MHz
DAP1 setup to DAP0 rising t16 SR 10 - - ns
edge
DAP1 hold after DAP0 rising t17 SR 10 - - ns
edge
DAP1 valid per DAP0 clock t19 CC 30 - - ns CL=20pF ; f=20MHz
period
DAP0 high time t12 SR 15 - - ns
DAP0 low time t13 SR 15 - - ns
DAP0 clock period t11 SR 50 - - ns
Data Sheet 477 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationDAP Parameters
t 11
t15 t14
t12 t13
0.9 VEXT
DAP0 0.5 VEXT
0.1 VEXT
t16 t17
DAP1
(Host to Device)
t11
DAP11),2)
(Device to Host)
t19
1) The DAP1 and DAP2 device to host timing is individual for both pins.
There is no guaranteed max. signal skew.
2) No explicite setup and hold times are given for DAP1 for the direction Device to Host.
Only t11 and t19 are guaranteed and the tool may set the sample point freely.
Figure 3-12 DAP Timing

Note: The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.
Data Sheet 478 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationASCLIN SPI Master Timing
3.21 ASCLIN SPI Master Timing

This section defines the timings for the ASCLIN in the TC39x.
Note: Pad asymmetry is already included in the following timings.
Table 3-41 Master Mode strong sharp (ss) output pads

Min. Typ. Max.
ASCLKO clock period t50 CC 20 - - ns CL=25pF
Deviation from ideal duty cycle t500 CC -2 - 2 ns CL=25pF
MTSR delay from ASCLKO t51 CC -3.5 - 3.5 ns CL=25pF
shifting edge
ASLSOn delay from the first t510 CC -3 - 3.5 ns CL=25pF
ASCLKO edge
MRST setup to ASCLKO t52 SR 25 - - ns CL=25pF
latching edge
MRST hold from ASCLKO t53 SR -2 - - ns CL=25pF
latching edge
Table 3-42 Master Mode strong medium (sm) output pads

Min. Typ. Max.
MTSR delay from ASCLKO t51 CC -7 - 7 ns CL=50pF
shifting edge
ASLSOn delay from the first t510 CC -7 - 7 ns CL=50pF
ASCLKO edge
latching edge
latching edge
Table 3-43 Master Mode medium (m) output pads

Min. Typ. Max.
MTSR delay from ASCLKO t51 CC -20 - 20 ns CL=50pF
shifting edge
ASLSOn delay from the first t510 CC -20 - 20 ns CL=50pF
ASCLKO edge
Data Sheet 479 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-43 Master Mode medium (m) output pads (cont’d)

Min. Typ. Max.
latching edge
latching edge
t50
ASCLKO
t51 t500 t51
MTSR
t52
t53
MRST Data valid Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-13 ASCLIN SPI Master Timing
Data Sheet 480 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
3.22 QSPI Timings, Master and Slave Mode

This section defines the timings for the QSPI in the TC39x.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
Table 3-44 Master Mode Timing, LVDS output pads for data and clock
Min. Typ. Max.
1)
SCLKO clock period t50 CC 20 - - ns CL=25pF
Deviation from the ideal duty t500 CC -1 1) - 1 1) ns CL=25pF
cycle
MTSR delay from SCLKO t51 CC -3 1) - 4 1) ns CL=25pF
shifting edge
SLSOn deviation from the ideal t510 CC -4 1) - 5.5 1) ns CL=25pF, driver
programmed position strength ss
1) 1)
-10 - 10 ns CL=25pF, driver
strength sm
1) 1)
strength m
1)
MRST setup to SCLK latching t52 SR 18 - - ns CL=25pF; valid for
edge LVDS Input pads of
QSPI2 only
19.5 1) - - ns CL=25pF; valid for
LVDS Input pads of
QSPI4 only
MRST hold from SCLK latching t53 SR -1 1) - - ns CL=25pF; valid for
edge LVDS Input pads only
1) The load (CL=25pF) defined in the condition list is a load definition for the single end signal SLSO and does not intend to
add an additional load inside the differential signal lines. For single end signals the load definition defines the max length
of the signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply.
Table 3-45 Master Mode Strong Sharp (ss) output pads

Min. Typ. Max.
Deviation from the ideal duty t500 CC -2 - 2 ns CL=25pF
cycle
MTSR delay from SCLKO t51 CC -4 - 5 ns CL=25pF
shifting edge
SLSOn deviation from the ideal t510 CC -4 - 5 ns CL=25pF
programmed position
MRST setup to SCLK latching t52 SR 25 1) 2) - - ns CL=25pF
edge
MRST hold from SCLK latching t53 SR -2 1)2) - - ns CL=25pF
edge
Data Sheet 481 V 1.1 2019-09
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TC39x BC/BD-Step
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-46 Master Mode Strong Medium (sm) output pads

Min. Typ. Max.
cycle
shifting edge
programmed position
edge
edge
Table 3-47 Master Mode Medium (m) output pads

Min. Typ. Max.
cycle
shifting edge
programmed position
edge
edge -13 1)2)
- - ns CL=50pF; SCR SSC
Table 3-48 Slave mode timing

Min. Typ. Max.
SCLK clock period t54 SR 4 x TMAX - - ns
SCLK duty cycle t55/t54 SR 40 - 60 %
Data Sheet 482 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-48 Slave mode timing (cont’d)

Min. Typ. Max.
MTSR setup to SCLK latching t56 SR 6 - - ns Input Level AL
edge 6 - - ns Input Level TTL
MTSR hold from SCLK latching t57 SR 4 - - ns Input Level AL
SLSI setup to first SCLK shift t58 SR 4 - - ns Input Level AL
SLSI hold from last SCLK t59 SR 3 - - ns Input Level AL
latching edge 6 - - ns Input Level TTL
MRST delay from SCLK shift t60 CC 5 - 35 ns driver = strong edge =
edge medium ; CL=50pF
2 - 24 ns driver = strong edge =
sharp ; CL=50pF
15 - 80 ns medium driver ;
CL=50pF
14 - - ns medium driver ;
CL=50pF; SCR SSC
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
t51 SAMPLING POINT
MTSR1) 0.5 VEXT/FLEX
t52
t53
MRST 1) Data valid Data valid
t510
2) 0.5 VEXT/FLEX
SLSOn
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-14 Master Mode Timing
Data Sheet 483 V 1.1 2019-09
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TC39x BC/BD-Step
t54 Last latching

SCLK edge
1) First shift First latching
SCLKI SCLK edge SCLK edge 0.5 VEXT/FLEX
t55 t55
t56 t56
t57 t57
MTSR 1) Data Data
valid valid
t60 t60
1)
MRST 0.5 VEXT/FLEX
t58
t61 t59
SLSI
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. QSPI_TmgSM.vsd
Figure 3-15 Slave Mode Timing
Data Sheet 484 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationMSC Timing 5 V Operation
3.23 MSC Timing 5 V Operation
The following section defines the timings.

Note: Load for LVDS pads are defined as differential loads in the following timings.
Table 3-49 LVDS clock/data (LVDS pads in LVDS mode) valid for 5V
Min. Typ. Max.
1) 2)
FCLPx clock period t40 CC 2 * TA - - ns LVDS; CL=50pF
3)
Deviation from ideal duty cycle t400 CC -1 3) - 1 3) ns LVDS; 0 < CL < 50pF
3) 3)
SOPx output delay t44 CC -3 - 3 ns CL=50pF
ENx output delay t45 CC -4 3) - 5 3) ns ss; CL=50pF; ABRA
block bypassed
-4 3) - 4 3) ns ss; CL=50pF; ABRA
block used
-2 3) - 10 3) ns sm; CL=50pF
3) 3)
-30 - 30 ns m; CL=50pF
1) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
3) The load (CL=50pF) defined in the condition list is a load definition for the single end signal EN and does not intend to add
an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the
signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply.
Table 3-50 Strong sharp (ss) driver for clock/data valid for 5V
Min. Typ. Max.
FCLPx clock period t40 CC 2 * TA - - ns CL=50pF
SOPx output delay t44 CC -4 - 3.5 ns CL=50pF
ENx output delay t45 CC -4 - 3.5 ns CL=50pF
Table 3-51 Strong medium (sm) driver for clock/data valid for 5V
Min. Typ. Max.
ENx output delay t45 CC -7 - 7 ns CL=50pF
Data Sheet 485 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationMSC Timing 5 V Operation
Table 3-52 Medium (m) driver for clock/data valid for 5V

Min. Typ. Max.
ENx output delay t45 CC -20 - 20 ns CL=50pF
Table 3-53 Upstream Interface

Min. Typ. Max.
SDI bit time t46 SR 8 * tMSC - - ns
SDI rise time t48 SR - - 200 ns
SDI fall time t49 SR - - 200 ns
t40
t400
FCLP
t44 t44
SOP
t45 t45
EN 0.5 VEXT/FLEX
t48 t49
0.9 VEXT/FLEX
SDI 0.1 VEXT/FLEX
t46 t46 MSC_Timing_A.vsd
Figure 3-16 MSC Interface Timing

Note: The SOP data signal is sampled with the falling edge of FCLP in the target device.
Data Sheet 486 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.24 Ethernet Interface (ETH) Characteristics
3.24.1 ETH Measurement Reference Points
ETH Clock 1.4 V 1.4 V
2.0 V 2.0 V
ETH I/O
0.8 V 0.8 V
tR tF
ETH_Testpoints.vsd
Figure 3-17 ETH Measurement Reference Points
Data Sheet 487 V 1.1 2019-09
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TC39x BC/BD-Step
3.24.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 3-54 ETH Management Signal Parameters valid for 3.3V

Min. Typ. Max.
ETH_MDC period t1 CC 400 - - ns CL=25pF
ETH_MDC high time t2 CC 160 - - ns CL=25pF
ETH_MDC low time t3 CC 160 - - ns CL=25pF
ETH_MDIO setup time (output) t4 CC 10 - - ns CL=25pF
ETH_MDIO hold time (output) t5 CC 10 - - ns CL=25pF
ETH_MDIO data valid (input) t6 SR 0 - 300 ns CL=25pF
t1
t3 t2
ETH_MDC
ETH_MDIO
sourced by controller :
ETH_MDC
t4 t5
ETH_MDIO
(output ) Valid Data
ETH_MDIO sourced by PHY:
ETH_MDC
t6
ETH_MDIO
(input ) Valid Data
ETH_Timing-Mgmt.vsd
Figure 3-18 ETH Management Signal Timing
Data Sheet 488 V 1.1 2019-09
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TC39x BC/BD-Step
3.24.3 ETH MII Parameters

In the following, the parameters of the MII (Media Independent Interface) are described.
Table 3-55 ETH MII Signal Timing Parameters

Min. Typ. Max.
Clock period t7 SR 40 - - ns CL=25pF ;
baudrate=100Mbps
400 - - ns CL=25pF ;
baudrate=10Mbps
Clock high time t8 SR 14 - 26 ns CL=25pF ;
baudrate=100Mbps
140 1) - 260 2) ns CL=25pF ;
baudrate=10Mbps
Clock low time t9 SR 14 - 26 ns CL=25pF ;
baudrate=100Mbps
140 1) - 260 2) ns CL=25pF ;
baudrate=10Mbps
Input setup time t10 SR 10 - - ns CL=25pF
Input hold time t11 SR 10 - - ns CL=25pF
Output valid time t12 CC 0 - 25 ns CL=25pF
1) Defined by 35% of clock period.
t7
t9 t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t1 0 t1 1
ETH_MII_RXD[3:0]
ETH_MII_RX_DV Valid Data
ETH_MII_RX_ER
(sourced by PHY )
ETH_MII_TX_CLK
t1 2
ETH_MII_TXD[3:0]
Valid Data
ETH_MII_TXEN
(sourced by controller )
ETH_Timing-MII.vsd
Figure 3-19 ETH MII Signal Timing
Data Sheet 489 V 1.1 2019-09
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TC39x BC/BD-Step
3.24.4 ETH RMII Parameters

In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.
Table 3-56 ETH RMII Signal Timing Parameters valid for 3.3V
Min. Typ. Max.
ETH_RMII_REF_CL clock t13 CC 20 - - ns 50ppm ; CL=25pF
period
ETH_RMII_REF_CL clock high t14 CC 7 1) - 13 2) ns CL=25pF
time
ETH_RMII_REF_CL clock low t15 CC 7 1) - 13 2) ns CL=25pF
time
ETHTXEN, ETHTXD[1:0], t16 CC 4 - - ns CL=25pF
ETHRXD[1:0], ETHCRSDV;
setup time
ETHTXEN, ETHTXD[1:0], t17 CC 2 - - ns CL=25pF
ETHRXD[1:0], ETHCRSDV;
hold time
t1 3
t1 5 t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t1 6 t17
ETHTXEN,
ETHTXD[1:0],
ETHRXD[1:0], Valid Data
ETHCRSDV,
ETH_Timing-RMII .vsd
ETHRXER
Figure 3-20 ETH RMII Signal Timing
Data Sheet 490 V 1.1 2019-09
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TC39x BC/BD-Step
3.24.5 ETH RGMII Parameters

In the following, the parameters of the RGMII are described.
Table 3-57 ETH RGMII Signal Timing Parameters valid for 3.3V
Min. Typ. Max.
TX Clock period t19 CC 36 40 44 ns 100Mbps
360 400 440 ns 10Mbps
7.2 8 8.8 ns Gigabit
Data to Clock Output skew t20 CC -500 0 500 ps
Data to Clock input skew (at t21 SR 1 1.8 2.6 ns SKEWCTL.RXCFG =
receiver) 0; SKEWCTL.TXCFG
=0
Clock duty cycle tduty CC 40 50 60 % 10/100Mbps
45 50 55 % Gigabit
GREFCLK duty cycle tduty_in SR 45 - 55 %
GREFCLK Input accuracy ACC SR -0.005 - 0.005 %
Figure 3-21 ETH RGMII TX Signal Timing (Delay on Destination (DoD))
Figure 3-22 ETH RGMII RX Signal Timing (Delay on Source (DoS))
Data Sheet 491 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationE-Ray Parameters
3.25 E-Ray Parameters

The timings of this section are valid for the strong driver and sharp edge settings of the output drivers with CL =
25 pF.
Table 3-58 Transmit Parameters

Min. Typ. Max.
Rise time of TxEN tdCCTxENRise2 - - 9 ns CL=25pF
5 CC
Fall time of TxEN tdCCTxENFall25 - - 9 ns CL=25pF
CC
Sum of rise and fall time tdCCTxRise25+ - - 9 ns 20% - 80% ; CL=25pF
dCCTxFall25
CC
Sum of delay between TP1_FF tdCCTxEN01 - - 25 ns
and TP1_CC and delays CC
derived from TP1_FFi, rising
edge of TxEN
Sum of delay between TP1_FF tdCCTxEN10 - - 25 ns
derived from TP1_FFi, falling
edge of TxEN
Asymmetry of sending ttx_asym CC -2.45 - 2.45 ns CL=25pF
Sum of delay between TP1_FF tdCCTxD01 - - 25 ns
edge of TxD
Sum of delay between TP1_FF tdCCTxD10 - - 25 ns
edge of TxD
TxD signal sum of rise and fall ttxd_sum CC - - 9 ns
time at TP1_BD
Table 3-59 Receive Parameters

Min. Typ. Max.
Acceptance of asymmetry at tdCCTxAsymAcc -30.5 - 43.0 ns CL=25pF
receiving part ept25 SR
Acceptance of asymmetry at tdCCTxAsymAcc -31.5 - 44.0 ns CL=15pF
receiving part ept15 SR
Threshold for detecting logical TuCCLogic1 35 - 70 %

high SR
Threshold for detecting logical TuCCLogic0 30 - 65 %
low SR
Data Sheet 492 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationE-Ray Parameters
Table 3-59 Receive Parameters (cont’d)

Min. Typ. Max.
Sum of delay between TP4_CC tdCCRxD01 - - 10 ns
and TP4_FF and delays CC
edge of RxD
Sum of delay between TP4_CC tdCCRxD10 - - 10 ns
and TP4_FF and delays CC
edge of RxD
Data Sheet 493 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationHSCT Parameters
3.26 HSCT Parameters
Table 3-60 HSCT - Rx parasitics and loads

Min. Typ. Max.
Capacitance total budget Ctotal CC - 3.5 5 pF Total Budget for
complete receiver
including silicon,
package, pins and
bond wire
Parasitic inductance budget Htotal CC - 5 - nH
Table 3-61 HSCT - Rx/Tx setup timing

Min. Typ. Max.
RX o/p duty cycle DCrx CC 40 - 60 %
Disable time of the LVDS pad tLVDSDIS CC - - 20 ns
Enable time of the LVDS pad tLVDSEN CC - - 400 ns
Wakeup time from Sleep Mode tSWU CC - - 250 ns
Maximum length of a wake-up tWUP CC - - 0.2 ns
glitch that does not wake-up
the receiver
Bias startup time tbias CC - 5 10 µs Bias distributor waking
up from power down
and provide stable
Bias.
RX startup time trxi CC - - 600 ns Wake-up RX from
power down.
TX startup time ttx CC - - 280 ns Wake-up TX from
power down.
Table 3-62 HSCT

Min. Typ. Max.
Bit Error Rate based on 20 MHz BER20 CC - - 10EXP- Bit Error Rate based
reference clock at Slave PLL 12 on 20 MHz reference
side clock at Slave PLL side
Transistion time from Rx tDISLS CC - - 700 ns Transition time from
Disable to Rx Low Speed Mode Rx Disable to Rx Low
Speed Mode
Data Sheet 494 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationHSCT Parameters
Table 3-62 HSCT (cont’d)

Min. Typ. Max.
Transistion time from Rx tHLSMS CC - - 500 ns Transition time from
High/Low Speed Mode to Rx Rx High/Low Speed
Medium Speed Mode Mode to Rx Medium
Speed Mode
Transistion time from Rx tHMSLS CC - - 600 ns Transition time from
High/Medium Speed Mode to Rx High/Medium
Rx Low Speed Mode Speed Mode to Rx
Low Speed Mode
Transistion time from Tx High tHSLS CC - - 600 ns Transition time from Tx
Speed Mode to Tx Low Speed High Speed Mode to
Mode Tx Low Speed Mode
Transistion time from Tx Low tLSHS CC - - 400 ns Transition time from Tx
Speed Mode to Tx High Speed Low Speed Mode to Tx
Mode High Speed Mode
Transistion time from Rx tMLSHS CC - - 400 ns Transition time from
Medium/Low Speed Mode to Rx Medium/Low
Rx High Speed Mode Speed Mode to Rx
High Speed Mode
HSCT physical layer power-on tPON CC - - 600 ns HSCT physical layer
power-on
Data Sheet 495 V 1.1 2019-09
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TC39x BC/BD-Step
Electrical SpecificationInter-IC (I2C) Interface Timing
3.27 Inter-IC (I2C) Interface Timing

All I2C timing parameter are SR for Master Mode and CC for Slave Mode.
Table 3-63 I2C Standard Mode Timing

Min. Typ. Max.
Fall time of both SDA and SCL t1 - - 300 ns Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Capacitive load for each bus Cb SR - - 400 pF
line
Bus free time between a STOP t10 4.7 - - µs Measured with a pull-
and ATART condition up resistor of 4.7
SCL and SDA line
Rise time of both SDA and SCL t2 - - 1000 ns Measured with a pull-
up resistor of 4.7
SCL and SDA line
Data hold time t3 0 - - µs Measured with a pull-
up resistor of 4.7
SCL and SDA line
Data set-up time t4 250 - - ns Measured with a pull-
up resistor of 4.7
SCL and SDA line
Low period of SCL clock t5 4.7 - - µs Measured with a pull-
up resistor of 4.7
SCL and SDA line
High period of SCL clock t6 4 - - µs Measured with a pull-
up resistor of 4.7
SCL and SDA line
Hold time for the (repeated) t7 4 - - µs Measured with a pull-
START condition up resistor of 4.7
SCL and SDA line
Data Sheet 496 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-63 I2C Standard Mode Timing (cont’d)

Min. Typ. Max.
Set-up time for (repeated) t8 4.7 - - µs Measured with a pull-
SCL and SDA line
Set-up time for STOP condition t9 4 - - µs Measured with a pull-
up resistor of 4.7
SCL and SDA line
Table 3-64 I2C Fast Mode Timing

Min. Typ. Max.
Fall time of both SDA and SCL t1 20+0.1*C - 300 ns Measured with a pull-
b up resistor of 4.7
SCL and SDA line
line
Bus free time between a STOP t10 1.3 - - µs Measured with a pull-
and ATART condition up resistor of 4.7
SCL and SDA line
Rise time of both SDA and SCL t2 20+0.1*C - 300 ns Measured with a pull-
b up resistor of 4.7
SCL and SDA line
Data hold time t3 0 - - µs Measured with a pull-
up resistor of 4.7
SCL and SDA line
Data set-up time t4 100 - - ns Measured with a pull-
up resistor of 4.7
SCL and SDA line
Low period of SCL clock t5 1.3 - - µs Measured with a pull-
up resistor of 4.7
SCL and SDA line
High period of SCL clock t6 0.6 - - µs Measured with a pull-
up resistor of 4.7
SCL and SDA line
Data Sheet 497 V 1.1 2019-09
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TC39x BC/BD-Step
Table 3-64 I2C Fast Mode Timing (cont’d)

Min. Typ. Max.
Hold time for the (repeated) t7 0.6 - - µs Measured with a pull-
SCL and SDA line
Set-up time for (repeated) t8 0.6 - - µs Measured with a pull-
SCL and SDA line
Set-up time for STOP condition t9 0.6 - - µs Measured with a pull-
up resistor of 4.7
SCL and SDA line
Table 3-65 I2C High Speed Mode Timing

Min. Typ. Max.
line
Fall time of SCL t11 10 1) - 40 1) ns bus line load of 100pF
1) 1)
Fall time of SDA t12 10 - 80 ns bus line load of 100pF
1) 1)
Rise time of SCL t13 10 - 40 ns bus line load of 100pF
Rise time of SDA t14 10 1) - 80 1) ns bus line load of 100pF
1) 1)
Data hold time t3 0 - 70 ns bus line load of 100pF
1)
Data set-up time t4 10 - - ns bus line load of 100pF
1)
Low period of SCL clock t5 160 - - ns bus line load of 100pF
1)
High period of SCL clock t6 60 - - ns bus line load of 100pF
1)
Hold time for the (repeated) t7 160 - - ns bus line load of 100pF
START condition
Set-up time for (repeated) t8 160 1) - - ns bus line load of 100pF
START condition
Set-up time for STOP condition t9 160 1) - - ns bus line load of 100pF
1) Values are defined for Cb = 100pF, for the Timing of Cb = 400pF see the I2C Standard.
Data Sheet 498 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
t1 t2 t4
70%
SDA 30%
t1 t3 t2 t6
SCL
th
9
t7 t5 clock
S t 10
SDA
t8 t7 t9
SCL
th
9
Sr P S
clock
Figure 3-23 I2C Standard and Fast Mode Timing
Data Sheet 499 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationSDMMC Interface Timing
3.28 SDMMC Interface Timing
Table 3-66 SDMMC

Min. Typ. Max.
Clock period Data Transfer t1 CC 20 - - ns push-pull, CL ≤ 30pF,
Mode VEXT = 3.3V
Clock period Indentification t2 CC - - 2500 ns open-drain, CL ≤ 30pF,
Mode VEXT = 3.3V
Clock low time t3 CC 6,5 - - ns CL ≤ 30pF, VEXT = 3.3V
Clock high time t4 CC 6,5 - - ns CL ≤ 30pF, VEXT = 3.3V
Data output valid time before t5 CC 3 - - ns CL ≤ 30pF, VEXT = 3.3V
rising clock edge
Data output valid time after t6 CC 3 - - ns CL ≤ 30pF, VEXT = 3.3V
rising clock edge
Data input hold time t7 SR 2,5 - - ns CL ≤ 30pF, VEXT =
3.3V, TTL levels
Data Input delay time t8 SR - - 13,7 ns CL ≤ 30pF, VEXT =
3.3V, TTL levels
Data Input setup time t9 SR 5,2 - - ns CL ≤ 30pF, VEXT =
3.3V, TTL levels
t1
t3
t4
CLK
t6
t5
Output DATA DATA
t8 t9
t7
Input DATA DATA
Figure 3-24 SDMMC Timing
Data Sheet 500 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationFSP Parameter
3.29 FSP Parameter
Table 3-67 Safety

Min. Typ. Max.
Skew between FSP0 and FSP1 tFSPSKEW -8 - 9 ns CL=50pF, driver
CC strength m
strength sm
strength ss
Data Sheet 501 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationRadar Interface Timing
3.30 Radar Interface Timing

This section defines the timings for RIF in the TC39x.
Table 3-68 Skew Calibration Related

Min. Typ. Max.
Bit time t80 CC 2.5 - - ns
Clock skew form the ideal t81 SR -0.6 - 0.6 ns Baud Rates from 200
position in the middle of the to 400MBaud
data bit
Set-up time t82 SR 1.5 - - ns Baud rates less than
200MBaud
Hold time t83 SR 1.5 - - ns Baud rates less than
200MBaud
RAMP1 set-up time relative to t88 SR 30 - - ns
the FRAME rising edge
RAMP1 hold time relative to the t89 SR 30 - - ns
FRAME rising edge
Data Sheet 502 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationEBU Timings
3.31 EBU Timings
3.31.1 BFCLKO Output Clock Timing

VSS = 0 V;VDD = 1.3 V ± 5%; 3.3 V ± 5%,
Table 3-69 BFCLK0 Output Clock Timing Parameters1)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Conditi
on
BFCLKO clock period tBFCLKO CC 13.332) – – ns –
BFCLKO high time t5 CC 3 – – ns –
BFCLKO low time t6 CC 3 – – ns –
BFCLKO rise time t7 CC – – 3 ns –
BFCLKO fall time t8 CC – – 3 ns –
3)
BFCLKO duty cycle t5/(t5 + t6) DC 35 50 55 % –
1) Not subject to production test, verified by design/characterization.
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K divider has to be regarded.
tBFCLKO
0.9 VDD
BFCLKO 0.5 VDDP05
0.1 VDD
t8 t7
t5 t6
MCT04883_mod
Figure 3-25 BFCLKO Output Clock Timing
3.31.2 EBU Asynchronous Timings

For each timing, the accumulated PLL jitter of the programed duration in number of clock periods must be added
separately.
Table 3-70 Common Asynchronous Timings valid for 3.3V

Min. Typ. Max.
AD(31:0) output delay to ADV# t13 CC -5.5 - 2.5 ns CL=35pF
rising edge, multiplexed read /
write
AD(31:0) output delay to ADV# t14 CC -5.5 - 2.5 ns CL=35pF
rising edge, multiplexed read /
write
Address valid to CS falling t15 CC -2 - 2.5 ns CL=35pF
edge (deviation from
programmed value)
Data Sheet 503 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 3-70 Common Asynchronous Timings valid for 3.3V (cont’d)

Min. Typ. Max.
Address valid to ADV falling t16 CC -2 - 2.5 ns CL=35pF
programmed value)
ADV falling edge -> CS falling t17 CC -2 - 2.5 ns CL=35pF
programmed value)
Pulse wdih deviation from the ta CC -0.8 - 0.8 ns edge=medium;
ideal programmed width due to CL=35pF
B pad asymmetry, rise delay - -0.8 - 0.8 ns edge=sharp; CL=35pF
fall delay
Table 3-71 Asynchronous Read Timings valid for 3.3V

Min. Typ. Max.
A(23:0) output delay to RD t0 CC -2.5 - 2.5 ns CL=35pF
rising edge, deviation from the
ideal programmed value
Data input Hold from CS rising t18 CC -6 - - ns CL=35pF
edge
Data input Setup to CS rising t19 CC 19 - - ns CL=35pF
edge
A(23:0) output delay to RD t1 CC -2.5 - 2.5 ns CL=35pF
CS rising edge to RD rising t2 CC -2 - 2.5 ns CL=35pF
edge, deviation from the ideal
programmed value
ADV rising edge to RD rising t3 CC -2 - 4.5 ns CL=35pF
programmed value
BC rising edge to RD rising t4 CC -2.5 - 2.5 ns CL=35pF
programmed value
WAIT input setup to RD rising t5 SR 19 - - ns CL=35pF
programmed value
WAIT input hold to RD rising t6 SR -4 - - ns CL=35pF
programmed value
Data input setup to RD rising t7 SR 19 - - ns CL=35pF
programmed value
Data Sheet 504 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 3-71 Asynchronous Read Timings valid for 3.3V (cont’d)

Min. Typ. Max.
Data input hold to RD rising t8 SR -4 - - ns CL=35pF
programmed value
MR / W output delay to RD# t9 CC -2.5 - 1.5 ns CL=35pF
EBU Address Address Hold Command Data Recovery New Addr.

STATE Phase Phase (opt.) Phase Hold Phase Phase (opt.) Phase
Control Bitfield: ADDRC AHOLDC RDWAIT DATAC RDRECOVC ADDRC
Duration Limits in 1...15 0...15 1...31 0...15 0...15 1...15

EBU_CLK Cycles
A[23:0] Valid Address Next

Addr.
pv + t30
pv + t31
pv + ta
CS[3:0] pv + t32
CSCOMB
pv + ta pv + t33
ADV
pv + ta
RD/WR
pv + ta
pv + ta
BC[3:0] t34
t35
WAIT
t36
t14 t37
pv + t13 pv + t38
AD[31:0] Address Out Data Out
MR/W pv + t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values) new_MuxWR_Async_10.vsd
Figure 3-26 Multiplexed Read Access
Data Sheet 505 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
EBU Address Address Hold Command Data Recovery New Addr.

STATE Phase Phase (opt.) Phase Hold Phase Phase (opt.) Phase
Control Bitfield: ADDRC AHOLDC RDWAIT DATAC RDRECOVC ADDRC
Duration Limits in 1...15 0...15 1...31 0...15 0...15 1...15

EBU_CLK Cycles
A[23:0] Valid Address Next

Addr.
pv + t30
pv + t31
pv + ta
CS[3:0] pv + t32
CSCOMB
pv + ta pv + t33
ADV
pv + ta
RD/WR
pv + ta
pv + ta
BC[3:0] t34
t35
WAIT
t36
t37 pv + t38
AD[31:0] Data Out
pv + t39
MR/W
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values) new_DemuxWR_Async_10.vsd
Figure 3-27 Demultiplexed Read Access
Table 3-72 Asynchnronous Write Timings valid for 3.3V

Min. Typ. Max.
A(23:0) output delay to WR t30 CC -2.5 - 2.5 ns CL=35pF
A(23:0) output delay to WR t31 CC -2.5 - 2.5 ns CL=35pF
CS rising edge to WR rising t32 CC -2 - 2.5 ns CL=35pF
programmed value
Data Sheet 506 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 3-72 Asynchnronous Write Timings valid for 3.3V (cont’d)

Min. Typ. Max.
ADV rising edge to WR rising t33 CC -2.5 - 2 ns CL=35pF
programmed value
BC rising edge to WR rising t34 CC -2.5 - 2 ns CL=35pF
programmed value
WAIT input setup to WR rising t35 SR 19 - - ns CL=35pF
programmed value
WAIT input hold to WR rising t36 SR 0 - - ns CL=35pF
programmed value
Data output delay to WR rising t37 CC -5.5 - 2.5 ns CL=35pF
programmed value
Data output delay to WR rising t38 CC -5.5 - 2.5 ns CL=35pF
programmed value
MR / W output delay to WR t39 CC -2.5 - 1.5 ns CL=35pF
3.31.3 EBU Burst Mode Access Timing

VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 3.3 V ± 5%;
Table 3-73 Burst Read Timings valid for 3.3V

Min. Typ. Max.
Output delay from BFCLKO t10 CC -2 - 2.5 ns CL=35pF
rising edge
RD and RD/WR active/inactive t12 CC -2 - 2 ns CL=35pF
after BFCLKO active edge
CSx output delay from t21 CC -2.5 - 2.0 ns CL=35pF
BFCLKO active edge
ADV active/inactive after t22 CC -2 - 2 ns CL=35pF
BFCLKO active edge
BAA active/inactive after t22a CC -2.5 - 2.0 ns CL=35pF
BFCLKO active edge
Data setup to BFCLKI rising t23 SR 5 - - ns CL=35pF
edge
Data hold from BFCLKI rising t24 SR 0 - - ns CL=35pF
edge
Data Sheet 507 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 3-73 Burst Read Timings valid for 3.3V (cont’d)

Min. Typ. Max.
WAIT setup (low or high) to t25 SR 5 - - ns CL=35pF
BFCLKI rising edge
WAIT hold (low or high) from t26 SR 0 - - ns CL=35pF
BFCLKI rising edge
Address Command Burst Burst Recovery Next Addr.

Phase(s) Phase(s) Phase(s) Phase(s) Phase(s) Phase(s)
BFCLKI 1)
BFCLKO
t10 t10
A[23:0] Burst Start Address Next
Addr.
t22 t22 t22

ADV
t21 t21 t21

CS[3:0]
CSCOMB
t12 t12
RD
RD/WR
t22a t22a
BAA
t24 t24
t23 t23
D[31:0]
Data (Addr+0) Data (Addr+4)
(32-Bit)
D[15:0]
Data (Addr+0) Data (Addr+2)
(16-Bit)
t26
t25
WAIT
1) Output delays are always referenced to BCLKO. The reference clock for input
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
feedback enabled). BurstRDWR_4.vsd
Figure 3-28 EBU Burst Mode Read / Write Access Timing
Data Sheet 508 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
3.31.4 EBU Arbitration Signal Timing

VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 3.3 V ± 5% ;
Table 3-74 EBU Arbitration Timings valid for 3.3V

Min. Typ. Max.
Output delay from BFCLKO t27 CC - - 3 ns CL=35pF
rising edge
Data setup to BFCLKO falling t28 SR 16 - - ns CL=35pF
edge
Data hold from BFCLKO falling t29 SR 2 - - ns CL=35pF
edge
BFCLKO
t27 t27
HLDA Output
t27 t27
BREQ Output
BFCLKO
t28
t28
t29 t29
HOLD Input
HLDA Input
EBUArb_1
Figure 3-29 EBU Arbitration Signal Timing
Data Sheet 509 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationFlash Target Parameters
3.32 Flash Target Parameters
Table 3-75 Flash

Min. Typ. Max.
Program Flash Erase Time per tERP CC - - 0.5 s cycle count < 1000
logical sector 1)
Program Flash Erase Time per tMERP CC - - 0.5 s For consecutive logical
Multi-Sector Command 1) sectors in a physical
sector with total range
≤ 512 kByte; cycle
count < 1000
Program Flash program time tPRP5 CC - - 80 µs 32 Byte
per page in 5 V mode 1)
Program Flash program time tPRP3 CC - - 115 µs 32 Byte
per page in 3.3 V mode 1)
Program Flash program time tPRPB5 CC - - 220 µs 256 Byte
per burst in 5 V mode 1)
Program Flash program time tPRPB3 CC - - 530 µs 256 Byte
per burst in 3.3 V mode 1)
Program Flash program time tPRPB3_1MB - - 2.2 s Derived value for
for 1 MByte with burst CC documentation
programming in 3.3 V mode purpose
excluding communication 1)
Program Flash program time tPRPB5_1MB - - 1 s Derived value for
for 1 MByte with burst CC documentation
programming in 5 V mode purpose
Program Flash program time tPRPB5_PF - - 16 s Derived value for
for complete PFlash with burst CC documentation
programming in 5 V mode purpose
Write Page Once adder 1) tADD CC - - 20 µs Adder to Program
Time when using Write
Page Once
Program Flash suspend to read tSPNDP CC - - 120 µs For Write Burst, Verify
latency 1) Erased and for multi-
(logical) sector erase
commands
Data Flash Erase Disturb Limit NDFD CC - - 50 cycles
(single ended sensing mode)
Data Flash Erase Disturb Limit NDFDC CC - - 500 cycles
(complement sensing mode)
UCB Erase Disturb Limit NUCBD CC - - 500 cycles
Data Sheet 510 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Table 3-75 Flash (cont’d)

Min. Typ. Max.
Program time data flash per tPRD CC - - 75 µs 8 Byte
page 1)2)
Complete Device Flash Erase tER_Dev CC - 10.4 18.5 s Valid for less than
Time PFlash and DFlash 1)3) 4) 1000 cycles, w/o UCB.
5)
Derived value for
documentation
purpose.
Data Flash program time per tPRDB CC - - 140 µs 32 Byte
burst 1)2)
Data Flash suspend to read tSPNDD CC - - 120 µs
latency 1)
Wait time after margin change tFL_MarginDel - - 2 µs
CC
Program Flash Endurance per NE_P CC - - 1000 cycles Replace logical sector
Logical Sector command shall be
used if a sector fails
during erase or
program
Number of erase operations NERP CC - - 16000 cycles
per physical sector in program
flash
Program Flash Retention Time, tRET CC 20 - - years Max. 1000
Sector erase/program cycles
UCB Retention Time tRTU CC 20 - - years Max. 100
erase/program cycles
per UCB, max 500
erase/program cycles
for all UCBs together
Data Flash access delay tDF CC - - 100 ns see RFLASH of DMU
register HF_DWAIT
Data Flash ECC Delay tDFECC CC - - 20 ns see RECC of DMU
register HF_DWAIT
Program Flash access delay tPF CC - - 30 ns see RFLASH of DMU
register HF_PWAIT
Program Flash ECC delay tPFECC CC - - 10 ns see RECC and CECC
of DMU register
HF_PWAIT
Number of erase operations on NERD0C CC - - 4000000 cycles
DF0 over lifetime (complement
sensing mode) 6)
Number of erase operations on NERD0S CC - - 750000 cycles
DF0 over lifetime (single ended
sensing mode) 7)
Data Sheet 511 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Min. Typ. Max.
Number of erase operations on NERD1C CC - - 2000000 cycles
DF1 over lifetime (complement
sensing mode) 6)
Number of erase operations on NERD1S CC - - 500000 cycles
DF1 over lifetime (single ended
sensing mode) 7)
Data Flash Endurance per NE_EEP10C - - 500000 cycles Max. data retention
EEPROMx sector (complement CC time 10 years
sensing mode) 8)
DataFlash Endurance per NE_EEP10S - - 125000 cycles Retention time and Tj
EEPROMx sector (single CC according below
ended sensing mode) 8) example temperature
profile
- - 125000 cycles max data retention
time 20y, Tj=110°C
time 8.2y, Tj=125°C
Data Flash Endurance per NE_HSMC CC - - 250000 cycles Max. data retention
HSMx sector (complement time 10 years
sensing mode) 8)
Data Flash Endurance per NE_HSMS CC - - 125000 cycles Retention time and Tj
HSMx sector (single ended according below
sensing mode) 8) example temperature
profile
time 20y, Tj=110°C
time 8.2y, Tj=125°C
Junction temperature limit for TJPFlash SR - - 150 °C
PFlash program/erase
operations
Data Flash Erase Time per tERD1 CC - - 0.5 s Max. 1000
Sector 1)3)5) erase/program cycles
Data Flash Erase Time per tERDM CC - - 1.5 s Max allowed cycles,
Sector 1)3)5) see NE_EEP10 and
NE_HSM parameters
DataFlash Adder on Erase tER_ADDC32C - - 50 ms Adder per 32 kByte on
Time per 32kByte erase size CC erase time; applicable
when using complement only when using
sensing mode 1) complement mode
Data Sheet 512 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

Min. Typ. Max.
Data Flash Erase Time per tMERD1 CC - - 0.5 s Max 1000
Multi-Sector Command 1)3)5) erase/program cycles;
For consecutive logical
sectors ≤ 256KBytes
Data Flash Erase Time per tMERDM CC - - 1.5 s Max allowed cycles,
Multi-Sector Command 1)3)5) see NE_EEP10x and
NE_HSMx
Parameters; For
consecutive logical
sectors ≤ 256 kByte
Program Flash Access Delay at tPF_low_VDDP3 - - 60 ns see register
reduced VDDP3 voltage supply CC DMU_HF_PWAIT.CFL
during cranking ASH
Data Flash Erase Verify time tVER_PAGE_D - - 10 µs Time per 8 Byte page
per page (Complement C CC for Verify Erased Page
Sensing) 2) command
Data Flash Erase Verify time tVER_PAGE_D - - 10 µs Time per 8 Byte page
per page (Single Ended S CC for Verify Erased Page
Sensing) 1) command
Program Flash Erase Verify tVER_PAGE_P - - 10 µs Time per 32 Byte page
time per page 1) CC for Verify Erased Page
command
Data Flash Erase Verify time tVER_SEC_DC - - 200 µs Time per 2 KB sector
per sector (Complement CC for Verify Erased
Sensing) 1) Logical Sector Range
command
Data Flash Erase Verify time tVER_SEC_DS - - 360 µs Time per 4 KB sector
per sector (Single Ended CC for Verify Erased
Sensing) 1) Logical Sector Range
command
Program Flash Erase Verify tVER_SEC_P - - 360 µs Time per 16KB sector
time per sector 1) CC for Verify Erased
Logical Sector Range
command
Data Flash Erase Verify time tVER_WL_DC - - 30 µs
per wordline (Complement CC
Sensing) 1)
Data Flash Erase Verify time tVER_WL_DS - - 50 µs
per wordline (Single Ended CC
Sensing) 1)
Program Flash Erase Verify tVER_WL_P - - 30 µs
time per wordline 1) CC
1) Only vaild for fFSI = 100MHz.
2) Time is not dependent on program mode (5V or 3.3V).
Data Sheet 513 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
3) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase
processes may be increased by up to 50%.
4) Using 512 kByte / 256 kByte erase commands (PFlash / DFlash).
5) If the DataFlash is operated in Complement Sensing Mode the erase time is increased by erase_size / 32kByte x
tER_ADDC32C
6) Allows segmentation of addressable memory into 8 logical sectors; round robin cycling must still be done to consider erase
disturb limit NDFD.
7) Allows segmentation of addressable memory into 6 logical sectors; round robin cycling must still be done to consider erase
disturb limit NDFD.
8) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.
Data Sheet 514 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationQuality Declarations
3.33 Quality Declarations
Table 3-76 Quality Parameters

Min. Typ. Max.
Moisture Sensitivity Level MSL CC - - 3 Conforming to Jedec
J-STD--020C for 240C
ESD susceptibility according to VCDM SR - - 500 1) V for all other balls/pins;
Charged Device Model (CDM) conforming to
JESD22-C101-C
- - 750 V for corner balls/pins;
conforming to
JESD22-C101-C
ESD susceptibility according to VHBM SR - - 2000 2) V Conforming to
Human Body Model (HBM) JESD22-A114-B
ESD susceptibility of the LVDS VHBM1 SR - - 2000 V
pins according to Human Body
Model (HBM)
Operation Lifetime tOP CC - - 24500 hour see below temperature
profile as an example
1) Pads of the AGBT interface are limited to a maximum value of 250V.
2) Pads of the AGBT interface are limited to a maximum value of 1000V.
Example Temperature Profile

The following temperature profile is an example. Application specific temperature profiles need to be aligned and
approved by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-77 Example Temperature Profile

TJ= Duration [h] Comment
≤ 170°C ≤ 30
≤ 160°C ≤ 120
≤ 150°C ≤ 220
≤ 140°C ≤ 350
≤ 130°C ≤ 780
≤ 120°C ≤ 1600
≤ 110°C ≤ 3000
≤ 100°C ≤ 7000
≤ 90°C ≤ 8000
≤ 80°C ≤ 2400
≤ 70°C ≤ 1000
≤ 24500 total time
Data Sheet 515 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationQuality Declarations
Table 3-78 Example Inactive Lifetime Temperature Profile

TJ= Duration [h] Comment
≤ 55°C ≤ 150700
Data Sheet 516 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationPackage Outline
3.34 Package Outline
Figure 3-30 Package Outlines LFBGA-516
29 2x
0.5 ±0.05
0.15 M C A B
17 ±0.1 1.7 MAX 0.08 M C
B A
20
19
0.1 C 18
17
16
15 19 x 0.8 = 15.2
14
13
17 ±0.1
CODE 12
11
10
9
8
7
29 2x 6
0.8
0.15 5
4
COPLA NARITY 3
SEATING PL ANE
2
1
Y W V U T R P N ML K J HG F E DC B A
INDEX
INDEX MAR KIN G MARKIN G
0.8
(LASER ED) 19 x 0.8 = 15.2
C 0.33 MIN
STAND OFF
Figure 3-31 Package Outlines LFBGA-292

You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
Data Sheet 517 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Electrical SpecificationPackage Outline
3.34.1 Package Parameters
Table 3-79 Package Parameters

Min. Typ. Max.
Thermal resistance (junction to RTH_JA - - 14 K/W LFBGA292
ambient) 1) CC - - 12.2 K/W LFBGA516
Thermal resistance (junction to RTH_JCB - - 4 K/W LFBGA292
case bottom) 1) CC - - 3 K/W LFBGA516
Thermal resistance (junction to RTH_JCT - - 5 K/W LFBGA292
case top) 1) CC - - 5 K/W LFBGA516
1) The top and bottom thermal resistances between the case and the ambient (RTH_CTA, RTH_CBA) are to be combined
with the thermal resistances between the junction and the case given above (RTH_JCT, RTH_JCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTH_JA). The thermal resistances between the case
and the ambient (RTH_CTA, RTH_CBA) depend on the external system (PCB, case) characteristics and are under user
responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTH_JA * PD, where the RTH_JA is
the total thermal resistance between the junction and the ambient.
Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1).
Data Sheet 518 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
HistoryChanges from Version 0.4 to Version 0.6
4 History
Version 0.4 is the first version of this document.
4.1 Changes from Version 0.4 to Version 0.6
• Update table Platform Feature Overview

• Changes in Pin Definition and Functions
– Add pad type RFAST to Legend
– Corrected ball assigmant to NC and NC1
– P32.0 replace name from EVR13 to EVRC
– P32.1 replace name from EVR13 to EVRC
– Add Function description for GTM_TIM_INxx Symbols
– Change numbering for GTM_TIM_INxx Symbols
– Update Function description for CAN signals
– Add missing Function description for EVADC
– Add missing Function description for EDSADC
– Add Function description for GTM_DTMxx Symbols
– Update Function description for SCU_E_REQ signals
– Change Symbol for SCU_E_REQ signals
– Update Function description for SCU_PD_HWCFGx signals
– Add QSPI5_SCLK to P14.10
– Remove SDMMC_DS from P15.2
– Remove PLL_WRAPPER_ANA_0_PAD_SYSCLK
– Switch CBS_TGyz from inverted to non inverted
– Change Symbol from HSCTPHY_1_RXDx to HSCT1_RXDx
– Change Symbol from SCU_EMGSTOP_B_RIQ to SCU_EMGSTOP_PORT_B
– Add CCUEXTCLK0
– Add EDSADC_EDS9NB to AN70
– Add PMS_DCDCSYNCO to P32.4
– Add DAP3 to P21.6
– Remove SDMMC_DS from P15.2
– ADD TDI to P21.6
– Add DAPE1 to P21.6
– Add DAP2 to P21.7
– ADD TDO to P21.7
– Remove DAP Function description from P21.7 Input
– Change Symbol HSDPM_HSDPM_xxx to HSDPM_xxx
– Switch EBU_x from inverted to non inverted
– Add HSDPM_MUTE to P22.3
Data Sheet 519 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Add HSDPM_BS0 to P22.4

– Change P22.4 from SLOW to FAST
– Add HSDPM_BS1 to P22.5
– Change P22.5 from SLOW to FAST
– Change Symbol from SCU_EMGSTOP_A_RIQ to SCU_EMGSTOP_PORT_A
– Add EVADC_G5CH2 to AN50
– Add EDSADC_EDS9PB to AN70
– Add Buffer Type to ABGT Symbols
• Changes in table 'Overload Parameters' of Overload
– Change max value of KOVDN from 6*10-4 to 1*10-4
– Change note of KOVDN from 'Overload injected on GPIO non LVDS pad and affecting neighbor slow pads;
-2mA < IIN < 0mA' to 'Overload injected on GPIO non LVDS pad and affecting neighbor slow pads; -5mA
< IIN < 0mA'
– Change note of KOVDN from '1.7*10-3' to '3*10-4'
– Change max value of KOVDN from 0.3 to 0.5
– Change note of KOVDN from 'Overload injected on LVDS pad and affecting neighbor LVDS pads' to
'Overload injected on LVDS TX pad and affecting neighbor LVDS pads'
– Change max value of KOVDP from 5*10-4 to 5*10-3
– Change note of KOVDP from 'Overload injected on LVDS pad and affecting neighbor LVDS pads' to
'Overload injected on LVDS TX pad and affecting neighbor LVDS pads'
– Change note of KOVDP from '1*10-5' to '1.5*10-3'
– Change max value of KOVAN from 1*10-4 to 1*10-5
– Change note of KOVAN from ''Analog Inputs overlaid with class slow pads or pull down diagnostics; -1mA <
IIN < 0mA'' to ''Analog Inputs overlaid with class slow pads or pull down diagnostics; -5mA < IIN < 0mA''
– Change note of KOVAN from '1*10-3' to '1*10-4'
– Change note of KOVAP from '1*10-5' to '2*10-5'
– Change note of KOVAP from '1*10-4' to '2*10-4'
– Add parameter IOUT
• Operating Conditions
– Change note of VDDM from 'Upper voltage range' to ''
– Change note of VDDM from 'Lower voltage range' to ''
– Change note of VEVRSB from 'VEVRSB is bonded together with VEXT supply pin in smaller LQFP packages.' to ''
• Changes in table 'PORST Pad' of Standard Pads
– Change note of HYS from 'non of the neighbor pads are used as output; TTL' to 'non of the neighbor pads
are used as output;TTL (degraded, used for CIF)'
– Change min value of HYS from 0.1 * VEXT/FLEX V to 0.055 * VEXT/FLEX V
– Change min value of IPDL from |18| µA to |15| µA
– Change note of HYS from 'two of the neighbor pads are used as output with driver=strong and edge=sharp;
TTL' to 'two of the neighbor pads are used as output with driver=strong and edge=sharp; TTL (degraded,
used for CIF)'
• Changes in table 'Fast 5V GPIO' of Standard Pads
– Change note of HYS from '0.1 * VEXT/FLEX V' to '0.09 * VEXT/FLEX V'
Data Sheet 520 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

– Change min value of RDSON from 140 Ohm to 125 Ohm
– Change typ value of RDSON from 200 Ohm to 225 Ohm
– Change max value of RDSON from 260 Ohm to 320 Ohm
– Change note of RDSON from '35 Ohm' to '31 Ohm'
– Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX'
– Change max value of tRF from 2.8 ns to 3.2 ns
– Change min value of tRF from 0.5+0.075*CL ns to 0.5+0.08*CL ns
– Change note of tRF from '0.5+0.15*CL ns' to '1.0+0.17*CL ns'
– Change max value of tRF from 4+0.95*CL ns to 12+1.0*CL ns
– Change note of IOZ from '-3900 nA' to '-5000 nA'
– Change note of IOZ from '3900 nA' to '5000 nA'
– Change max value of IOZ from 3600 nA to 5000 nA
– Change note of fIND from '' to 'AL and TTL'
– Change note of fOUTD from '' to 'medium driver'
– Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'
• Changes in table 'Fast 3.3V GPIO' of Standard Pads
– Change min value of tRF from 2 ns to 1.6 ns
– Change min value of tRF from 4+0.57*CL ns to 2+0.57*CL ns
– Change note of tRF from '1.5+0.38*CL ns' to '8+0.4*CL ns'
Data Sheet 521 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Change note of tRF from '7+1.1*CL ns' to '10+1.25*CL ns'

– Change note of IPUH from '|19| µA' to '|17| µA'
– Change min value of IPUH from |9| µA to |11| µA
– Change min value of IPDL from |18| µA to |15| µA
– Change min value of IOZ from -4100 nA to -5000 nA
– Change max value of IOZ from 3600 nA to 5000 nA
• Changes in table 'Slow 5V GPIO' of Standard Pads
– Change max value of tRF from 3.5+0.55*CL ns to 7+0.55*CL ns
– Change note of tRF from '4+0.95*CL ns' to '12+1*CL ns'
– Change note of IPUH from 'VIH; AL or TTL' to 'VIH; AL or TTL; exept VGATE1P and TJ > 150°C'
– Change note of IPUH from 'VIL; AL or TTL' to 'VIL; AL or TTL; exept VGATE1P and TJ > 150°C'
• Changes in table 'Slow 3.3V GPIO' of Standard Pads
– Change max value of tRF from 7+1.1*CL ns to 10+1.25*CL ns
– Change note of IPUH from 'VIH; AL and TTL (degraded, used for CIF)' to 'VIH; AL and TTL (degraded, used
for CIF); exept VGATE1P and TJ > 150°C'
– Change note of IPUH from 'VIH; TTL' to 'VIH; TTL; exept VGATE1P and TJ > 150°C'
– Change note of IPDL from '|18| µA' to '|15| µA'
– Change note of IPUH from 'VIL; AL and TTL and TTL (degraded, used for CIF)' to 'VIL; AL and TTL and TTL
(degraded, used for CIF); exept VGATE1P and TJ > 150°C'
Data Sheet 522 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
• Changes in table 'Class S 5V' of Standard Pads

– Change note of IOZ from 'TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC
channel connected or AN70 or AN71' to 'TJ ≤ 150°C; PDD option available, or AltRef option available and
EDSADC channel connected, or two EDSADC channels connected'
• Changes in table 'RFast 3.3V pad' of Standard Pads
– Change min value of tRF from 2 ns to 1.6 ns
– Change min value of tRF from 4+0.57*CL ns to 2+0.57*CL ns
– Change max value of tRF from 1.5+0.38*CL ns to 8+0.4*CL ns
– Change note of IPUH from '|9| µA' to '|11| µA'
– Change note of IPDL from '|18| µA' to '|15| µA'
• Changes in table 'RFast 5V GPIO' of Standard Pads
– Change min value of tRF from 2.5+0.18*CL ns to 1.0+0.18*CL ns
– Change note of tRF from ''CL = 25pF; driver = strong sharp edge'' to ''CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX''
Data Sheet 523 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Change note of tRF from '2.8 ns' to '3.2 ns'

– Change max value of tRF from 0.5+0.15*CL ns to 1.0+0.17*CL ns
– Change max value of tRF from 2.5+0.35*CL ns to 5.0+0.35*CL ns
– Change note of fIND from '' to 'AL and TTL'
• Changes in table 'Class D' of Standard Pads
– Update footnote of Standard Pads to 'For AN11 200 nA need to be added.'
– Change note of IOZ from 'TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC
channel connected' to 'TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel
connected, or two EDSADC channels connected'
• Changes in table 'LVDS - IEEE standard LVDS general purpose link (GPL)' of LVDS Pads
– Change max value of trise20 from 0.5 ns to 0.75 ns
– Change max value of tfall20 from 0.5 ns to 0.75 ns
– Change max value of VOD from 450 mV to 500 mV
– Change min value of VOD from 360 mV to 380 mV
• VADC 5V
– Change max value of dVCSD from 20 % to 10 %
– Change note of dVCSD from '-20 %' to '-10 %'
– Change note of fADCI from 'Upper voltage range' to '4.5V ≤ VDDM ≤ 5.5V'
– Change note of tSCAL from 'Upper voltage range' to '4.5V ≤ VDDM ≤ 5.5V'
– Change note of fADCI from 'Lower voltage range' to '2.97V ≤ VDDM < 4.5V'
– Change note of tS from 'Primary group or fast compare channel, upper voltage range; input buffer disabled'
to 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer disabled'
– Change note of tSCAL from 'Lower voltage range' to '2.97V ≤ VDDM < 4.5V'
– Change note of tS from 'Primary group or fast compare channel, upper voltage range; input buffer enabled'
to 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer enabled'
– Change note of tS from 'Secondary group, upper voltage range; input buffer disabled' to 'Secondary group,
4.5V ≤ VDDM ≤ 5.5V; input buffer disabled'
– Change note of tS from 'Secondary group, upper voltage range; input buffer enabled' to 'Secondary group,
4.5V ≤ VDDM ≤ 5.5V; input buffer enabled'
– Change note of tS from 'Primary Group or fast compare channel, lower voltage range; input buffer disabled'
to 'Primary Group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer disabled'
– Change note of tS from 'Primary group or fast compare channel, lower voltage range; input buffer enabled'
to 'Primary group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer enabled'
– Change note of tS from 'Secondary group, lower voltage range; input buffer disabled' to 'Secondary group,
2.97V ≤ VDDM < 4.5V; input buffer disabled'
– Change note of tS from 'Secondary group, lower voltage range; input buffer enabled' to 'Secondary group,
2.97V ≤ VDDM < 4.5V; input buffer enabled'
• DSADC 5V
Data Sheet 524 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Update wording in front of table DSADC 5V

– Change note of DCF from '10-5 fD, offset compensation filter enabled (FCFGMx.OEN = 001B)' to '10-5 fD,
offset compensation filter enabled (FCFGMx.OCEN = 001B)'
• OSC_XTAL
– Change note of CL1 from '2.35 pF' to '3.35 pF'
– Add parameter CXTAL1
• Changes in table 'DTS PMS' of DTS
– Change max value of tM from 2.6 ms to 2.7 ms
• Add table 'DTS Core'
• Current Consumption
– Change max value of IDDRAIL from 1370 mA to 1372 mA
– Change TJ in real power pattern definition from 150°C to 160°C
• Changes in table 'Module Core Current Consumption' of Current Consumption
– Change name of Module Core Current Consumption from Module Core Current Concumption to Module
Core Current Consumption
– Change note of IDDCx0 from 'real power pattern' to 'real power pattern; IPC=0.6'
– Change max value of IDDCx0 from 40 mA to 45 mA
– Change note of IDDCx0 from ''max power pattern'' to ''max power pattern; IPC=1.2''
– Change note of IDDCx0 from '60 mA' to '70 mA'
– Change note of IDDCxx from ''max power pattern'' to ''max power pattern; IPC=1.2''
– Change note of IDDCxx from 'IDDCx0 + 60 mA' to 'IDDCx0 + 50 mA'
– Change note of IDDGTM from 'real power pattern; TIMx, TOMx, ATOMx , MCSx active. 5 clusters at 200
MHz.' to 'real power pattern; TIMx, TOMx, ATOMx , MCSx active. 3 clusters at 200 MHz.'
– Change max value of IDDGTM from 60 mA to 130 mA
– Change note of IDDGTM from '88 mA' to '160 mA'
– Change note of IDDSPU from ''CTRL.DIV = 01 ; FFT clocked at half SPU Clock'' to ''CTRL.DIV = 01 ; FFT
clocked at half SPU Clock; Both SPU modules are active.''
– Change note of IDDSPU from '60 mA' to '70 mA'
– Change note of IDDCIF from '20 mA' to '30 mA'
– Change note of IDDMBIST from '100 mA' to '200 mA'
– Change note of IDDCxx from 'real power pattern' to 'real power pattern; IPC=0.6'
– Change note of IDDGTM from 'TIMx, TOMx active at 100MHz. ATOMx , MCSx, DPLL inactive.' to 'TIMx,
TOMx active at 100MHz. ATOMx , MCSx, DPLL inactive. 2 clusters at 100 MHz.'
– Change max value of IDDGTM from 20 mA to 60 mA
– Change note of IEXTRAIL from '58 mA' to '54 mA'
– Change max value of IEXTRAIL from t.b.d mA to 60 mA
– Change max value of IEXTFLEX from 30 mA to 22 mA
• Changes in table 'Module Current Consumption' of Current Consumption
– Change max value of IEXTLVDS from t.b.d mA to 20 mA
– Change max value of ISCRSB from 4 mA to 6.5 mA
– Change description of ISCRSB from 'SCR 8-bit Standby Controller in STANDBY Mode drawn at VEVRSB
supply pin' to 'SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply
pin'
Data Sheet 525 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Change note of ISCRSB from 'SCR power pattern; fSYS_SCR = 20MHz; TJ=150°C' to 'SCR power pattern incl.
PMS current consumption with fback clock active; fSYS_SCR = 20MHz; TJ=150°C'
– Change note of ISCRSB from 'real power pattern; fSYS_SCR = 70kHz; TJ=25°C' to 'SCR power pattern incl.
PMS current consumption with fback inactive; fSYS_SCR = 70kHz; TJ=25°C'
– Change typ value of ISCRSB from 0.025 mA to 0.190 mA
– Change description of ISCRSB from 'SCR 8-bit Standby Controller in STANDBY Mode drawn at VEVRSB
supply pin' to 'SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply
pin'
– Change note of IDDM from ''real power pattern ; current for EDSADC module only; 11 EDSADC channels
active.'' to ''real power pattern; current for EDSADC modules only and EVADC modules are inactive; 11
EDSADC channels active continuously.''
– Change note of IDDM from '66 mA' to '44 mA'
– Change note of IDDM from 'max power pattern; All EDSADC channels active 100% time.' to 'max power
pattern; current for EDSADC modules only and EVADC modules are inactive; all EDSADC channels active
continuously.'
– Change max value of IDDM from 84 mA to 63 mA
– Change note of IDDM from 'real pattern;12 EVADC modules active' to 'real power pattern; current for EVADC
modules only and EDSADC modules are inactive; 12 EVADC modules active.'
– Change note of IDDM from 'max power pattern; All EVADC modules are active 100% time' to 'max power
pattern; current for EVADC modules only and EDSADC modules are inactive; all EVADC modules active.'
– Change max value of IDDTOT from 1506 mA to 1536 mA
– Change note of IDDTOTDC3 from 'real power pattern; VEXT = 3.3V; TJ=160°C' to 'real power pattern; EVRC
reset settings with 72% efficiency; VEXT = 3.3V; TJ=160°C'
– Change max value of IDDTOTDC3 from 830 mA to 980 mA
– Change description of IDDTOTDC3 from '∑ Sum of all currents with DC-DC EVR13 regulator active' to '∑ Sum
of all currents with DC-DC EVRC regulator active'
– Change note of IDDTOTDC5 from 'real power pattern; VEXT = 5V; TJ=160°C' to 'real power pattern; EVRC reset
settings with 72% efficiency; VEXT = 5V; TJ=160°C'
– Change max value of IDDTOTDC5 from 600 mA to 670 mA
– Change description of IDDTOTDC5 from '∑ Sum of all currents with DC-DC EVR13 regulator active' to '∑ Sum
of all currents with DC-DC EVRC regulator active'
– Change note of ISLEEP from '10 mA' to '25 mA'
– Change note of PD from 't.b.d. mW' to '3220 mW'
– Change max value of PD from 2560 mW to 2500 mW
– Change max value of IEVRSB from 4 mA to 8 mA
– Change note of IEVRSB from 'real power pattern; PMS/EVR module current considered without SCR and
Standby RAM' to 'real power pattern; PMS/EVR module current considered without SCR and Standby RAM
during RUN mode.'
– Change max value of IDDTOT from 1690 mA to 1720 mA
• Reset
– Change min value of tPOH from 100 ns to 150 ns
– Change note of tBP from 'dV/dT=1V/ms. including EVR ramp-up and Firmware execution time; RAM
initialization and HSM boot time is not included' to 'dVEXT/dT=1V/ms. VEXT>VLVDRST5. Boot time after
Data Sheet 526 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
Cold PORST including EVR ramp-up and Firmware execution time; RAM initialization and HSM boot time
are not included.'
– Change note of tB from 'operating with max. frequencies' to 'operating with max. frequencies, with valid BMI
header'
– Change note of tBS from '' to 'RAM initialization and HSM boot time are not included, with valid BMI header'
– Change note of tBP from 'Firmware execution time; without EVR ramp-up; RAM initialization and HSM boot
time is not included' to 'Firmware execution time after warm PORST without EVR ramp-up; RAM
initialization and HSM boot time is not included'
– Change type of tPOA from CC to SR
– Change description of tPOA from 'Minimum PORST active hold time externally after power supplies are
stable at operating levels' to 'Minimum PORST active hold time externally after power supplies are stable
at operating levels after start-up'
• PMS/EVR33 LDO
– Change note of dVout/dIout from 'Normal RUN mode; dI=10 to 60 to 100mA; dt=20ns; Tsettle=20us' to
'Normal RUN mode; dI=10 to 60mA; dt=20ns; Tsettle=20us'
– Change note of dVout/dIout from 'Normal RUN mode; dI=100 to 60 to 10mA; dt=20ns; Tsettle=20us' to
'Normal RUN mode; dI=60 to 10mA; dt=20ns; Tsettle=20us'
– Change note of dVout/dVin from 'dVin/dT=1V/ms; dV= 5 to 3.6V' to 'dVin/dT=1V/ms; dV= 5 to 3.6V;
IMAX=60mA'
– Change note of dVout/dVin from 'dVin/dT=1V/ms; dV= 3.6 to 5V' to 'dVin/dT=1V/ms; dV= 3.6 to 5V;
IMAX=60mA'
– Change typ value of COUT from 1 µF to 2.2 µF
– Change note of COUT from '1.35 µF' to '3 µF'
– Change min value of COUT from 0.65 µF to 1.45 µF
– Change min value of dVout/dIout from -100 mV to -180 mV
– Change max value of dVout/dIout from 100 mV to 180 mV
– Change note of IMAX from '100 mA' to '60 mA'
– Change note of dVout/dVin from 'dVin/dT=50V/ms; dV= 5 to 3.6V' to 'dVin/dT=50V/ms; dV= 5 to 3.6V;
IMAX=60mA'
– Change note of dVout/dVin from 'dVin/dT=50V/ms; dV= 3.6 to 5V' to 'dVin/dT=50V/ms; dV= 3.6 to 5V;
IMAX=60mA'
• PMS/Supply Monitors
– Change max value of VLVDRST5 from 2.7 V to 2.75 V
– Change note of VLVDRST5 from '2.67 V' to '2.72 V'
– Change note of VRST33 from 'by reset release before EVR trimming on supply ramp-up.' to 'by last cold
PORST release on supply ramp-up including voltage hysteresis.'
– Change note of VRSTC from 'by reset release before trimming on supply ramp-up including 2 LSB voltage
Hysteresis' to 'by last cold PORST release on supply ramp-up including voltage hysteresis.'
– Change note of VRST5 from 'by reset release before trimming on supply ramp-up including 2 LSB voltage
hysteresis' to 'by last cold PORST release on supply ramp-up including voltage hysteresis.'
• PMS/Supply Ramp
– Change description of SR_V_EXT from 'External VEXT & VEVRSB supply ramp' to 'External VEXT & VEVRSB
supply ramp-up and ramp-down slope'
– Change description of SR_V_DDP3 from 'External VDDP3 supply ramp' to 'External VDDP3 supply ramp-up
and ramp-down slope'
Data Sheet 527 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Change description of SR_V_DD from 'External VDD supply ramp' to 'External VDD supply ramp-up and
ramp-down slope'
– Change description of SR_V_DDM from 'External VDDM supply ramp' to 'External VDDM supply ramp-up and
ramp-down slope'
• Changes in table 'EVRC SMPS' of PMS/EVRC SMPS
– Change name of EVRC SMPS from EVR13 SMPS to EVRC SMPS
• Changes in table 'EVRC SMPS External components' of PMS/EVRC SMPS
– Change name of EVRC SMPS External components from EVR13 SMPS External components to EVRC
SMPS External components
• Changes in section JTAG Parameters
– Update figure Test Clock Timing (TCK)
• Changes in section DAP Parameters
– Combine figures Test Clock Timing (DAP0), DAP Timing Host to Device, and DAP Timing Device to Host
(DAP1 and DAP2 pins) into single figure DAP Timing
– Add t14 for condition F=40MHz
• Changes in table 'Master Mode strong sharp (ss) output pads' of ASCLIN
– Change min value of t51 from -3 ns to -3.5 ns
– Change note of t51 from '3 ns' to '3.5 ns'
– Change max value of t510 from 3 ns to 3.5 ns
• Changes in table 'Master Mode Timing, LVDS output pads for data and clock' of QSPI
– Change max value of t51 from 3 ns to 4 ns
– Change min value of t52 from 17 ns to 18 ns
• Changes in table 'Strong sharp (ss) driver for clock/data valid for 5V' of MSC
– Change note of t45 from '-3 ns' to '-4 ns'
– Change min value of t44 from -3 ns to -4 ns
• Changes in table 'ETH RGMII Signal Timing Parameters valid for 3.3V' of Ethernet
– Add parameter t21
• Changes in table 'ETH RMII Signal Timing Parameters valid for 3.3V' of Ethernet
– Change description of t16 from 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; setup
time' to 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; setup time'
– Change description of t17 from 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; hold
time' to 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; hold time'
• Changes in table 'HSCT - Rx/Tx setup timing' of LVDS Pads
– Change max value of ttx from 250 ns to 280 ns
• Removed section CIF
• SDMMC
– Change note of t5 from 'CL ≤ 30pF' to 'CL ≤ 30pF, VEXT = 3.3V'
– Change min value of t5 from -3 ns to 3 ns
– Change description of t5 from 'Data output delay time' to 'Data output valid time before rising clock edge'
– Change note of t6 from ''CL ≤ 30pF'' to ''CL ≤ 30pF, VEXT = 3.3V''
– Change note of t6 from 'max' to 'min'
Data Sheet 528 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Change note of t6 from '13,7 ns' to '3 ns'

– Change description of t6 from 'Data input delay time' to 'Data output valid time after rising clock edge'
– Change description of t8 from 'Output hold time' to 'Data Input delay time'
– Add parameter t9
– Change note of t1 from 'push-pull, CL ≤ 30pF, tolerance ± 100kHz' to 'push-pull, CL ≤ 30pF, VEXT = 3.3V'
– Change predicate of t1 from max to min
– Change note of t2 from 'open-drain, CL ≤ 30pF, tolerance ± 20kHz' to 'open-drain, CL ≤ 30pF, VEXT = 3.3V'
– Change note of t7 from 'CL ≤ 30pF' to 'CL ≤ 30pF, VEXT = 3.3V, TTL levels'
• Flash
– Change note of tER_Dev from '' to 'Valid for less than 1000 cycles, w/o UCB. Derived value for documentation
purpose.'
– Change note of tER_Dev from 'Derived value for documentation purpose' to 'Valid for less than 1000 cycles,
w/o UCB. Derived value for documentation purpose.'
• ED Current Consumption
– Change max value of IDDSB from 8 mA to 15 mA
– Change note of IDDSB from '27 mA' to '34 mA'
• Package Parameters
– Update table Thermal Characteristics of the Package
– Change package type from PG-LFBGA-516-9 to PG-LFBGA-516-10
– Change package type from PG-LFBGA-292-9 to PG-LFBGA-292-10
• Added preamble to AGBT stating that AGBT is lab-only interface without full test coverage
• Changes in table "Absolute Maximum Ratings"
– Change value of Parameter "VDDM"
– Change value of Parameter "VIN"
– Change value of Parameter "VIN"
• Changes in table "Master Mode strong sharp (ss) output pads"
– Change value of Parameter "t51"
• Changes in table "Current Consumption"
– Change condition of Parameter "IDDPORST"
– Change value of Parameter "IDDRAIL"
– Change value of Parameter "IEVRSB"
– Change value of Parameter "IEXTFLEX"
– Change value of Parameter "ISLEEP"
– Change condition of Parameter "ISTANDBY"
– Change value of Parameter "ISTANDBY"
– Change of Parameter "IDDRAIL" description
Data Sheet 529 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Footnote added to Parameter "IDDP3RAIL"

– Footnote added to Parameter "IEXTFLEX"
– Footnote added to Parameter "IEVRSB"
– Footnote added to Parameter "ISLEEP"
• Changes in table "Module Core Current Consumption"
– Change condition of Parameter "IDDLBIST"
– Change value of Parameter "IDDLBIST"
– Footnote added to Parameter "IDDLBIST"
– Change condition of Parameter "IDDMBIST"
– Change value of Parameter "IDDMBIST"
– Change condition of Parameter "IDDSPU1"
– Change value of Parameter "IDDSPU1"
– Change value of Parameter "IDDSPULJ1"
– Parameter "IDDCIF" deleted
– New Parameter "IDDSPU2" added
– New Parameter "IDDSPULJ1" added
– New Parameter "IDDSPULJ2" added
• Changes in table "Module Current Consumption"
– Change value of Parameter "IDDP3PROG"
– Change value of Parameter "ISCRIDLE"
– Change condition of Parameter "ISCRSB"
– Change value of Parameter "ISCRSB"
– Footnote added to Parameter "IEXTLVDS"
– New Parameter "IDDP3ERASE" added
• Changes in table "DSADC 5V"
– Change preamble
– Change value of Parameter "EDGAIN"
– Change value of Parameter "EDOFF"
– Change value of Parameter "IREF"
– Change value of Parameter "IRMS"
– Change of Parameter "IREF" description
– Footnote added to Parameter "IRMS"
– Footnote added to Parameter "EDGAIN"
– Footnote added to Parameter "EDOFF"
– Footnote added to Parameter "SNR"
– Footnote added to Parameter "SFDR"
• Changes in table "DTS PMS"
– Change value of Parameter "tM"
• Changes in table "ED Current Consumption"
– Change value of Parameter "IEXTAGBT"
– Parameter "VDDAGBT" deleted
– Footnote changed of Parameter "VDDEEC"
Data Sheet 530 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
• Changes in table "Transmit Parameters"

– Change of Parameter "tdCCxEN10" description
• Changes in table "EVR33 LDO"
– Change value of Parameter "IMAX"
– Change condition of Parameter "VinVoutRatio"
– Change value of Parameter "VinVoutRatio"
– Change condition of Parameter "VoutIOutRatio"
– Change value of Parameter "VoutIOutRatio"
– Change condition of Parameter "tSTR"
– New Parameter "dVOUTTC" added
• Changes in table "EVRC SMPS"
– Change value of Parameter "dVDDDC"
– Change condition of Parameter "fDCDC"
• Changes in table "Flash"
– Change condition of Parameter "NE_EEP10S"
– Change condition of Parameter "NE_HSMS"
• Changes in table "HSCT - Rx/Tx setup timing"
– Change value of Parameter "ttx"
• Changes in table "LVDS - IEEE standard LVDS general purpose link (GPL)"
– Change condition of Parameter "Rin"
– Change value of Parameter "VOD"
– Change value of Parameter "tfall20"
– Change value of Parameter "trise20"
– New Parameter "tSET" added
– Corrected “LVDSH” to “LVDS”
• Changes in table "LVDS clock/data (LVDS pads in LVDS mode) valid for 5V"
– Change condition of Parameter "t40"
• Changes in table "Strong sharp (ss) driver for clock/data valid for 5V"
• Changes in table "Operating Conditions"
– Change condition of Parameter "TA"
• Changes in table "OSC_XTAL"
– New Parameter "IHBX" added
– Change value of Parameter "CXTAL1"
– Remove Parameter VILBX
• Changes in table "Overload"
– Change condition of Parameter "IINANA"
– Parameter "IID" deleted
• Changes in table "Package Parameters"
– Change value of Parameter "RTH_JA"
Data Sheet 531 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Change value of Parameter "RTH_JCB"

– Change value of Parameter "RTH_JCT"
• Changes in table "PLL Peripheral"
– Change condition of Parameter "DP"
– Change condition of Parameter "DRMS"
– Change value of Parameter "DPP"
– Change Parameter description of "DPP"
– New Parameter "JABS25" added
– New Parameter "DPPI" added
• Changes in table "Master Mode Timing, LVDS output pads for data and clock"
• Changes in table "Quality"
– Change of Parameter "VHBM1" description
– Footnote added to Parameter "VCCM"
– Footnote added to Parameter "VHBM"
• Changes in table "Reset"
– Change condition of Parameter "tB"
– Change value of Parameter "tB"
– Change condition of Parameter "tBP"
– Change value of Parameter "tBS"
– Change value of Parameter "tBWP"
– Change condition of Parameter "tLBIST"
– Footnote added to Parameter "tBP"
– Change of Parameter "tBP" description
– Change of Parameter "tLBIST" description
• Changes in table "SDMMC"
• Changes in table "PORST pad"
– Change condition of Parameter "IOZ"
– Change value of Parameter "HYS"
• Changes in table "Class D"
– Change value of Parameter "IOZ"
Data Sheet 532 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
• Changes in table "Fast 3.3V GPIO"

– Footnote changed of parameter “tRF”
– Change value of Parameter "VIH"
– Change value of Parameter "VIL"
– Change condition of Parameter "tRF"
– Footnote added to Parameter "tRF"
– Change of Parameter "tSET" description
– Change condition of Parameter "VILD"
• Changes in table "Fast 5V GPIO"
• Changes in table "RFast 3.3V pad"
• Changes in table "RFast 5V pad"
• Changes in table "Slow 3.3V GPIO"
Data Sheet 533 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step

– Change condition of Parameter "IPUH"
• Changes in table "Slow 5V GPIO"
– Change condition of Parameter "IPUH"
• Changes in table "Class S 5V"
• Changes in table "ADC Reference Pads"
– Change condition of Parameter "IOZ2"
– Change value of Parameter "IOZ2"
– Footnote added to Parameter “IOZ2”
• Changes in table "Supply Monitors"
– Change condition of Parameter "VDDMON"
– Change condition of Parameter "VDDP3MON"
– Change condition of Parameter "VEXTMON"
– Change condition of Parameter "VRST33"
– Change condition of Parameter "VRST5"
– Change condition of Parameter "VRSTC"
– Change value of Parameter "VRSTC"
– Change condition of Parameter "tMON"
– Footnote added to Parameter "VEXTMON"
Data Sheet 534 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
• Changes in table "Back-up Clock"

– Footnote change in Parameter "fBACKT"
• Changes in table "DTS Core"
– New Parameter "dT" added
• Changes in table "VADC 5V"
– Changed preamble
– Change condition of Parameter "RPDD"
– Change condition of Parameter "VDDK"
– Change condition of Parameter "fADCI"
– Change condition of Parameter "tS"
– Change condition of Parameter "tSCAL"
– New Parameter "VDDK" added
– New Parameter "dVDDK" added
– Footnote added to Parameter "QCONV"
• Changes in table “Platform Feature Overview”

– Removed feature for “ASIL”
• Changes in chapter “Pin Definition and Functions”
– Changed naming from “BGA516” to “LFBGA-516”
– Changed figure for “LFBGA-516”
– Changed naming from “BGA292” to “LFBGA-292”
– Changed figure for “LFBGA-292”
– Changed naming from “BGA292 ADAS feature set” to “LFBGA-292 ADAS feature set”
– Changed figure for “LFBGA-292 ADAS feature set”
• Changes in chapter 'TC39x Pin Definition and Functions' for package variant LFBGA-516
– Changes in LFBGA-516 Package Variant 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4,
P00.5, P00.11, P00.12
P01.13
P02.5, P02.8, P02.9, P02.10, P02.13, P02.14
P10.8
P11.8, P11.10, P11.12, P11.13, P11.14
– Changes in LFBGA-516 Package Variant 'Port 12 Functions' table; P12.0, P12.1
P13.9, P13.12
P14.9, P14.10, P14.13, P14.14, P14.15
Data Sheet 535 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
P15.5
P20.9, P20.10
P21.5
P22.7, P22.8, P22.9, P22.10, P22.11
P23.6, P23.7
P32.7
P33.5, P33.7, P33.8, P33.9, P33.10, P33.12, P33.13
– Changes in LFBGA-516 Package Variant 'Analog Inputs' table; Ball AD10, AB10
• Changes in chapter 'TC39x Pin Definition and Functions' for package variant LFBGA-292
P00.5, P00.11, P00.12
P02.5, P02.8, P02.9, P02.10
P10.8
P11.8, P11.10, P11.12, P11.13, P11.14
– Changes in LFBGA-292 Package Variant 'Port 13 Functions' table; P13.0, P13.1, P13.2
P14.9, P14.10
P15.5
P20.9, P20.10
P21.5
P22.7, P22.8, P22.9, P22.10, P22.11
P23.6, P23.7
P32.7
P33.5, P33.7, P33.8, P33.9, P33.10, P33.12, P33.13
Data Sheet 536 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Changes in LFBGA-292 Package Variant 'Analog Inputs' table; Ball W5, U5

• Changes in chapter 'TC39x Pin Definition and Functions' for package variant LFBGA-292 ADAS
– Changes in LFBGA-292 ADAS Package Variant 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3,
P00.4, P00.5, P00.11, P00.12
P02.4, P02.5, P02.8
P10.7, P10.8
P11.7, P11.8, P11.10, P11.12, P11.13, P11.14
– Changes in LFBGA-292 ADAS Package Variant 'Port 12 Functions' table; P12.0, P12.1
P14.8, P14.9, P14.10
P15.4, P15.5
P20.8, P20.9, P20.10
P21.4, P21.5
P22.6, P22.7, P22.8, P22.9, P22.10, P22.11
P23.5, P23.6, P23.7
P32.6, P32.7
P33.4, P33.5, P33.7, P33.8, P33.9, P33.10, P33.12, P33.13
– Changes in LFBGA-292 ADAS Package Variant 'Port 34 Functions' table; P34.1, P34.2
– Changes in LFBGA-292 Package Variant 'Analog Inputs' table; Ball W5, U5
• Changes in chapter 'Pin Position Definition'
– Changes in table “Pad List”, Number 206
• Changed description in chapter 'Legend'
– Column “Buffer Type”: PU2
– add link to Spirit file
• Changes in chapter “Electrical Specification”
• Changed wording in sub-chapter “Parameter Interpretation”
• Changes in table 'Absolute Maximum Ratings'
– Added footnote 2) for VDD
– Changed order of footnotes
• Changes in table "Overload Parameters"
– Changed table numbers in description
– Changed parameter condition of "KOVAN"
– Changed parameter condition of "KOVAP"
– Added footnote 2) for “KOVAN” and "KOVAP"
Data Sheet 537 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
• Changes in table "Operating Conditions"

– Added footnote 1) for "VDD"
• Changes in table 'PORST Pad'
– Added values and notes for parameter VIH
– Added values and notes for parameter VIL
– Added footnote 2) for IPDL
• Changes in table 'Fast 5V GPIO' of Standard Pads
– Removed values and conditions of parameter IOZ
– Changed footnote 2) for tRF
– Added footnote 4) for IPUH
• Changes in table 'Fast 3.3V GPIO' of Standard Pads
– Combined equal values of IOZ in single line
• Changes in table 'Slow 5V GPIO' of Standard Pads
• Changes in table 'Slow 3.3V GPIO' of Standard Pads
• Changes in table 'RFast 5V GPIO' of Standard Pads
• Changes in table 'RFast 3.3V pad' of Standard Pads
• Changes in table 'Class S 5V' of Standard Pads
• Add table 'Class S 3.3V'
• Changes in table 'ADC Reference Pads' of Standard Pads
Data Sheet 538 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Changed values and notes of parameter IOZ2

– Added parameter and conditions for IOZ2
• Changes in table 'LVDS - IEEE standard LVDS general purpose link (GPL)' of LVDS Pads
– Added footnote 1) for tRISE20
– Added footnote 2) for tFALL20
• Changes in table 'VADC 5V'
– Added values and conditions of parameter VAREF
– Changed values and conditions of VAREF
– Added footnote 1) for VAREF
• Changes in table 'DSADC 5V'
– Changed value of parameter VAREF
– Added value and condition of parameter IREF
• Changes in table 'OSC_XTAL'
– Added parameter for DCX1
– Added parameter for JABSX1
– Added parameter for SRXTAL1
– Added footnote 3) for DCX1, JABSX1, SRXTAL1
• Changes in table 'Back-up Clock'
– Changed value of parameter fSB
– Changed footnote 1) for fBACKT
• Changes in table 'DTS PMS'
– Added parameter conditions for TNL
• Changes in table 'DTS Core'
– Added parameter conditions for TNL
• Changes in description of chapter 'Power Supply Current'
– Changed information of real power pattern
– Added peripherals information
– Added max power pattern
– Added ADAS power pattern
• Changes in table 'Current Consumption'
– Added value and conditions for parameter IDDRAIL
– Added parameter for parameter PDSR
– Added conditions for parameter PDSR
– Changed value for parameter ISLEEP
– Addded parameter for IDDP3RAIL
– Remove footnote 1) for IDDP3RAIL
– Changed footnote 1) for IDDPORST , IEXTFLEX , IEVRSB , ISLEEP
– Mapped footnote 2) to all values of IDD3RAIL
– Changed footnote 3) for IEXTFLEX
Data Sheet 539 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Added footnote 5) for IEXTFLEX

• Changes in table 'Module Current Consumption'
– Changed value and condition of parameter IEXTLVDS
– Added footnote 3) to IEXTLVDS
– Added footnote 5) to IDDM
– Changed footnote 8) for ISCRIDLE
• Changes in table 'Module Core Current Consumption'
– Changed footnote 1) for IDDHSM
– Changed footnote for IDDSPU2
– Removed parameter IDDSPU1
– Removed parameter IDDSPULJ1
• Changes in chapter “Supply Ramp-up and Ramp-down Behavior”
– Changed Figure and textual description for “Single supply mode (a)”
– Changed Figure and textual description for “Single supply mode (e)”
– Changed Figure and textual description for “Single supply mode (d)”
– Changed Figure and textual description for “Single supply mode (h)”
• Changes in table 'Reset'
– Added parameter tWARMRSTSEQ
– Shift typ limit to max limits for mode0 and mode1 and removed typ limits for parameter tSCR
• Changes in table 'EVR33 LDO'
– Added footnote 7) for dVOUT / dIOUT
• Changes in table 'Supply Monitors'
– Changed condition of parameter VRST33
– Changed condition of parameter VRSTC
– Changed values of parameter VEXTMON
– Changed footnote 2) for VEXTPRIUV, VDDP3PRIUV, VDDPRIUV,
– Changed footnote 3) for VDDP3PRIUV, VDDPRIUV,
– Added footnote 5) for VEXTMON, VDDP3MON, VDDMON
• Changes in table 'EVRC SMPS External Components'
– Add values of parameter 'LDC' for condition 0.8MHz
• Changed chapter naming from 'Phase Locked Loop (PLL)' to 'System Phase Locked Loop (SYS_PLL)'
• Changes in table 'PLL System'
– Removed parameter values of 'fMV'
• Changes in table 'QSPI Master Mode Timing'
– Added footnote 1) for all parameters
• Changes in table 'MSC LVDS clock/data'
– Added footnote 3) for all parameters
• Changes in chapter 'HSCT Parameters'
– Added table for “HSCT”
• Add chapter FSP Parameter
• Changes in table 'Flash'
– Changed description of parameter of NDFD
Data Sheet 540 V 1.1 2019-09
OPEN MARKET VERSION

TC39x BC/BD-Step
– Added parameter NDFDC

– Added parameter NUCBD
– Added parameter tVER_PAGE_DC
– Added parameter tVER_PAGE_DS
– Removed parameter tVER_PAGE_D
– Changed parameter note tRTU
• Removed chapter 'Parameters Specific to the Emulation Part Only'
• Changes in table 'Package Parameters'
– Changed parameter value of RTH_JCB
– Changed parameter values of RTH_JCT
• Changes in table ‘Platform Feature Overview‘ - changed package types.

• Changes in chapter ‘Pin Position Definition’ added definition of ‘neighbor pads’
• Changes in chapter ‘Legend’ - changed explanation for PD2
• Changes in table ‘Absolute Maximum Ratings’
– Added footnote 5
– Changed description of parameter IIN
• Changes in table ‘Slow 5V GPIO’ - Parameter IOZ- removed note ‘no analog input’
• Changes in table ‘Slow 3.3V GPIO’ - Parameter IOZ- removed note ‘no analog input’
• Changes in chapter ‘High Performance LVDS Pads’- added two notes
• Changes in table ‘LVDS - IEEE Standard LVDS general purpose link (GPL)’ of LVDS pads
– Changed value for parameter Vl
– Changed condition for parameter Vidth
– Added values for parameter Vidth
– Changed condition for parameter Rin
• Changes in table ‘VADC 5V’ - Parameter VAIN - added note to parameter
• Changes in table ‘DSADC 5V’ - Parameter EDGain - added footnote 4
• Changes in table ‘OSC_XTAL’ - Parameter tOSCS - changed footnote 1
• Changes in chapter ‘Power Supply Current’ - Section ‘ADAS power pattern’ - added SPU frequency
• Changes in table ‘Current Consumption’ - Parameter VEVRSB - changed footnote 8
• Changes in table ‘Module Core Current Consumption’ - added Parameter IDDSPU1 and IIDDSPULJ1
• Changes in table ‘Module Core Current Consumption’ - Parameter IDDSPU2 and IIDDSPULJ2 changed footnote 2
• Changes in table ‘Supply ramp’ - added comment for power cycles
• Changed in chapter ‘ETH RGMII Parameters’ - added figures ETH RGMII TX Signal Timing (Delay on
Destination ((DoD))
• Changed in chapter ‘ETH RGMII Parameters’ - added figures ETH RGMII RX Signal Timing (Delay on Source
((DoS))
• Changes in table ‘Quality Parmeters’ - Parameter VHBM1 - changed max. limit
• Changes in chapter ‘Package Outline’ - changed package types.
Data Sheet 541 V 1.1 2019-09
OPEN MARKET VERSION

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32-Bit

32-Bit Single-Chip Microcontroller

OPEN MARKET VERSION

Data Sheet 3 V 1.1 2019-09

OPEN MARKET VERSION

Trademarks of Infineon Technologies AG

Data Sheet 4 V 1.1 2019-09

OPEN MARKET VERSION

Data Sheet 5 V 1.1, 2019-09

OPEN MARKET VERSION

3.30 Radar Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Data Sheet 6 V 1.1 2019-09

OPEN MARKET VERSION

Data Sheet 7 V 1.1 2019-09

OPEN MARKET VERSION

Data Sheet 8 V 1.1 2019-09

OPEN MARKET VERSION

Table 1-1 Platform Feature Overview

Data Sheet 9 V 1.1 2019-09

OPEN MARKET VERSION

Table 1-1 Platform Feature Overview (cont’d)

Data Sheet 10 V 1.1 2019-09

OPEN MARKET VERSION

Table 1-1 Platform Feature Overview (cont’d)

Tambient Range −40 … +150°C

Data Sheet 11 V 1.1 2019-09

OPEN MARKET VERSION

Pin Definition and Functions:

2 Pin Definition and Functions:

H NC NC P02.2 P02.1 P15.2 P20.14 VSS VSS H

AN68 / AN69 / AN33 / Y

AN67 / VAREF VAGND VEVRS AA

AN64 / AN29 / AN28 / AN17 / AB

AN63 / AN62 / AN27 / AN26 / AC

AF AN56 AN57 P25.2 P25.1 AF

TC39xed - (top view)

Figure 2-1 Logic Symbol for the package variant LFBGA-516

Data Sheet 12 V 1.1 2019-09

OPEN MARKET VERSION

Pin Definition and Functions:

C P02.2 P02.1 P15.2 P20.14 C

F P02.8 P02.7 P02.11 P02.10 ESR0 P20.6 P20.7 P20.8 F

VAREF VAGND VEVRS

AN29 / AN28 / AN17 /

TC39xed - (top view)

Figure 2-2 Logic Symbol for the package variant LFBGA-292

Data Sheet 13 V 1.1 2019-09

OPEN MARKET VERSION

Pin Definition and Functions:

C P50_1 P50_0 P15.2 P20.14 C

F P50_7 P50_6 P10.1 P10.2 ESR0 P20.6 P20.7 P20.8 F

P50_1 P50_1 P21.7 / P21.6 /

VAREF VAGND AN24 / VEVRS

TC39xed_adas - (top view)

Data Sheet 14 V 1.1 2019-09

OPEN MARKET VERSION

Pin Definition and Functions:LFBGA-516 Package Variant Pin Configuration

2.1 LFBGA-516 Package Variant Pin Configuration

Table 2-1 Port 00 Functions