MC78L00A Series, NCV78L00A 100 Ma Positive Voltage Regulators

MC78L00A Series,
NCV78L00A
100 mA Positive Voltage

Regulators
The MC78L00A Series of positive voltage regulators are
inexpensive, easy−to−use devices suitable for a multitude of www.onsemi.com
applications that require a regulated supply of up to 100 mA. Like
their higher powered MC7800 and MC78M00 Series cousins, these
regulators feature internal current limiting and thermal shutdown
making them remarkably rugged. No external components are
required with the MC78L00 devices in many applications.
These devices offer a substantial performance advantage over the
traditional zener diode−resistor combination, as output impedance
12 1
and quiescent current are substantially reduced. 2
3 3
Features STRAIGHT LEAD BENT LEAD
BULK PACK TAPE & REEL
• Wide Range of Available, Fixed Output Voltages AMMO PACK
• Low Cost TO−92 Pin: 1. Output
• Internal Short Circuit Current Limiting P SUFFIX 2. Ground
3. Input
CASE 029
• Internal Thermal Overload Protection
• No External Components Required
• Complementary Negative Regulators Offered (MC79L00A Series)
• NCV Prefix for Automotive and Other Applications Requiring SOIC−8*
Unique Site and Control Change Requirements; AEC−Q100 D SUFFIX SOT−89
Qualified and PPAP Capable CASE 751 CASE 528AG
• These are Pb−Free Devices *SOIC−8 is an internally modified SO−8 package. Pins
2, 3, 6, and 7 are electrically common to the die attach
flag. This internal lead frame modification decreases
Input package thermal resistance and increases power
15k Q3 Q5 Q11 dissipation capability when appropriately mounted on
a printed circuit board. SOIC−8 conforms to all ex-
Q12 ternal dimensions of the standard SO−8 package.
Q1
Q10
PIN CONNECTIONS
5.0k 3.0 Output
3.8k
VOUT 1 8 VIN
Q4 Q6
0-25k
GND 2 7 GND
GND 3 6 GND
1.9k 19k 2.2k
1.2k NC 4 5 NC
C Q9
(Top View)
Q2 Q8
Z1 2.85k TAB
Q7
420
1.0k
Ground
1 2 3
VOUT GND VIN
(Top View)
Figure 1. Representative Schematic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
DEVICE MARKING INFORMATION

See general marking information in the device marking
section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 1999 1 Publication Order Number:

October, 2016 − Rev. 18 MC78L00A/D
This datasheet has been downloaded from http://www.digchip.com at this page

MC78L00A Series, NCV78L00A
Input MC78LXXA Output
Cin*
CO**
0.33 mF
0.1 mF
Figure 2. Standard Application
A common ground is required between the input and the output voltages. The input voltage must remain typically 2.0 V above the output
voltage even during the low point on the input ripple voltage.
* Cin is required if regulator is located an appreciable distance from power supply filter.
** CO is not needed for stability; however, it does improve transient response.
ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit
Input Voltage (5.0 V−9.0 V) VI 30 Vdc
Input Voltage (12 V−18 V) 35
Input Voltage (24 V) 40
Storage Temperature Range Tstg −65 to +150 °C
Maximum Junction Temperature TJ 150 °C
Moisture Sensitivity Level MSL 1 −
ESD Capability, Human Body Model (Note 1) ESDHBM 2000 V
ESD Capability, Machine Model (Note 1) ESDMM 200 V
ESD Capability, Charged Device Model (Note 1) ESDCDM 2000 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD Charged Device Model tested per EIA/JES D22/C101, Field Induced Charge Model.
THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Package Dissipation PD Internally Limited W
Thermal Characteristics, TO−92 RqJA 200 °C/W
Thermal Resistance, Junction−to−Ambient
Thermal Characteristics, SOIC8 RqJA Refer to Figure 8 °C/W
Thermal Characteristics, SOT−89 RqJA 55 °C/W
2. Thermal Resistance, Junction−to−Ambient depends on P.C.B. Copper area. See details in Figure 8.
Thermal Resistance, Junction−to−Case is not defined. SOIC 8 lead and TO-92 packages that do not have a heat sink like other packages
may have. This is the reason that a Theta JC is never specified. A little heat transfer will occur through the package but since it is plastic, it is
minimal. The majority of the heat that is transferred is through the leads where they connect to the circuit board.
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ELECTRICAL CHARACTERISTICS (VI = 10 V, IO = 40 mA, CI = 0.33 mF, CO = 0.1 mF, − 40°C < TJ < +125°C (for MC78LXXAB,
NCV78L05A), 0°C < TJ < +125°C (for MC78LXXAC), unless otherwise noted.)
MC78L05AC, AB, NCV78L05A
Characteristics Symbol Min Typ Max Unit
Output Voltage (TJ = +25°C) VO 4.8 5.0 5.2 Vdc
Line Regulation Regline mV
(TJ = +25°C, IO = 40 mA)
7.0 Vdc ≤ VI ≤ 20 Vdc − 55 150
8.0 Vdc ≤ VI ≤ 20 Vdc − 45 100
Load Regulation Regload mV
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) − 11 60
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) − 5.0 30
Output Voltage VO Vdc
(7.0 Vdc ≤ VI ≤ 20 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 4.75 − 5.25
(VI = 10 V, 1.0 mA ≤ IO ≤ 70 mA) 4.75 − 5.25
Input Bias Current IIB mA
(TJ = +25°C) − 3.8 6.0
(TJ = +125°C) − − 5.5
Input Bias Current Change DIIB mA
(8.0 Vdc ≤ VI ≤ 20 Vdc) − − 1.5
(1.0 mA ≤ IO ≤ 40 mA) − − 0.1
Output Noise Voltage Vn − 40 − mV
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
Ripple Rejection (IO = 40 mA, RR 41 49 − dB
f = 120 Hz, 8.0 Vdc ≤ VI ≤ 18 V, TJ = +25°C)
Dropout Voltage (TJ = +25°C) VI − VO − 1.7 − Vdc
NOTE: NCV78L05A: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring
site and change control.
ELECTRICAL CHARACTERISTICS (VI = 14 V, IO = 40 mA, CI = 0.33 mF, CO = 0.1 mF, − 40°C < TJ < +125°C (for MC78LXXAB),
0°C < TJ < +125°C (for MC78LXXAC), unless otherwise noted.)
MC78L08AC, AB
(TJ = +25°C, IO = 40 mA)
10.5 Vdc ≤ VI ≤ 23 Vdc − 20 175
11 Vdc ≤ VI ≤ 23 Vdc − 12 125
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) − 15 80
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) − 8.0 40
(10.5 Vdc ≤ VI ≤ 23 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 7.6 − 8.4
(VI = 14 V, 1.0 mA ≤ IO ≤ 70 mA) 7.6 − 8.4
(TJ = +25°C) − 3.0 6.0
(TJ = +125°C) − − 5.5
(11 Vdc ≤ VI ≤ 23 Vdc) − − 1.5
(1.0 mA ≤ IO ≤ 40 mA) − − 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
f = 120 Hz, 12 V ≤ VI ≤ 23 V, TJ = +25°C)
Dropout Voltage (TJ = +25°C) VI − VO − 1.7 − Vdc
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MC78L09AC, AB
(TJ = +25°C, IO = 40 mA)
11.5 Vdc ≤ VI ≤ 24 Vdc − 20 175
12 Vdc ≤ VI ≤ 24 Vdc − 12 125
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) − 15 90
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) − 8.0 40
(11.5 Vdc ≤ VI ≤ 24 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 8.5 − 9.5
(VI = 15 V, 1.0 mA ≤ IO ≤ 70 mA) 8.5 − 9.5
(TJ = +25°C) − 3.0 6.0
(TJ = +125°C) − − 5.5
(11 Vdc ≤ VI ≤ 23 Vdc) − − 1.5
(1.0 mA ≤ IO ≤ 40 mA) − − 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
f = 120 Hz, 13 V ≤ VI ≤ 24 V, TJ = +25°C)
Dropout Voltage VI − VO − 1.7 − Vdc
(TJ = +25°C)
MC78L12AC, AB
Output Voltage (TJ = +25°C) VO 11.5 12 12.5 Vdc
(TJ = +25°C, IO = 40 Ma)
14.5 Vdc ≤ VI ≤ 27 Vdc − 120 250
16 Vdc ≤ VI ≤ 27 Vdc − 100 200
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) − 20 100
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) − 10 50
(14.5 Vdc ≤ VI ≤ 27 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 11.4 − 12.6
(VI = 19 V, 1.0 mA ≤ IO ≤ 70 mA) 11.4 − 12.6
(TJ = +25°C) − 4.2 6.5
(TJ = +125°C) − − 6.0
(16 Vdc ≤ VI ≤ 27 Vdc) − − 1.5
(1.0 mA ≤ IO ≤ 40 mA) − − 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
Ripple Rejection RR 37 42 − dB
(IO = 40 mA, f = 120 Hz, 15 V ≤ VI ≤ 25 V, TJ = +25°C)
(TJ = +25°C)
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MC78L15AC, AB / NCV78L15A
(TJ = +25°C, IO = 40 mA)
17.5 Vdc ≤ VI ≤ 30 Vdc − 130 300
20 Vdc ≤ VI ≤ 30 Vdc − 110 250
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) − 25 150
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) − 12 75
(17.5 Vdc ≤ VI ≤ 30 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 14.25 − 15.75
(VI = 23 V, 1.0 mA ≤ IO ≤ 70 mA) 14.25 − 15.75
(TJ = +25°C) − 4.4 6.5
(TJ = +125°C) − − 6.0
(20 Vdc ≤ VI ≤ 30 Vdc) − − 1.5
(1.0 mA ≤ IO ≤ 40 mA) − − 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
(IO = 40 mA, f = 120 Hz, 18.5 V ≤ VI ≤ 28.5 V, TJ = +25°C)
(TJ = +25°C)
ELECTRICAL CHARACTERISTICS (VI = 27 V, IO = 40 mA, CI = 0.33 mF, CO = 0.1 mF, 0°C < TJ < +125°C, unless otherwise noted.)
MC78L18AC
(TJ = +25°C, IO = 40 mA)
21.4 Vdc ≤ VI ≤ 33 Vdc
20.7 Vdc ≤ VI ≤ 33 Vdc − 45 325
22 Vdc ≤ VI ≤ 33 Vdc
21 Vdc ≤ VI ≤ 33 Vdc − 35 275
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) − 30 170
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) − 15 85
(21.4 Vdc ≤ VI ≤ 33 Vdc, 1.0 mA ≤ IO ≤ 40 mA)
(20.7 Vdc ≤ VI ≤ 33 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 17.1 − 18.9
(VI = 27 V, 1.0 mA ≤ IO ≤ 70 mA)
(VI = 27 V, 1.0 mA ≤ IO ≤ 70 mA) 17.1 − 18.9
(TJ = +25°C) − 3.1 6.5
(TJ = +125°C) − − 6.0
(22 Vdc ≤ VI ≤ 33 Vdc)
(21 Vdc ≤ VI ≤ 33 Vdc) − − 1.5
(1.0 mA ≤ IO ≤ 40 mA) − − 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
(IO = 40 mA, f = 120 Hz, 23 V ≤ VI ≤ 33 V, TJ = +25°C)
(TJ = +25°C)
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ELECTRICAL CHARACTERISTICS (VI = 33 V, IO = 40 mA, CI = 0.33 mF, CO = 0.1 mF, 0°C < TJ < +125°C, unless otherwise noted.)
MC78L24AC
Output Voltage (TJ = +25°C) VO 23 24 25 Vdc
(TJ = +25°C, IO = 40 mA)
27.5 Vdc ≤ VI ≤ 38 Vdc − − −
28 Vdc ≤ VI ≤ 80 Vdc − 50 300
27 Vdc ≤ VI ≤ 38 Vdc − 60 350
(TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA) − 40 200
(TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA) − 20 100
(28 Vdc ≤ VI ≤ 38 Vdc, 1.0 mA ≤ IO ≤ 40 mA)
(27 Vdc ≤ VI ≤ 38 Vdc, 1.0 mA ≤ IO ≤ 40 mA) 22.8 − 25.2
(28 Vdc ≤ VI = 33 Vdc, 1.0 mA ≤ IO ≤ 70 mA)
(27 Vdc ≤ VI ≤ 33 Vdc, 1.0 mA ≤ IO ≤ 70 mA) 22.8 − 25.2
(TJ = +25°C) − 3.1 6.5
(TJ = +125°C) − − 6.0
(28 Vdc ≤ VI ≤ 38 Vdc) − − 1.5
(1.0 mA ≤ IO ≤ 40 mA) − − 0.1
(TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)
(IO = 40 mA, f = 120 Hz, 29 V ≤ VI ≤ 35 V, TJ = +25°C)
(TJ = +25°C)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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8.0
V I -V O , INPUT/OUTPUT DIFFERENTIAL VOLTAGE (V)

2.5
MC78L05AC IO = 70 mA
VO, OUTPUT VOLTAGE (V)
Vout = 5.0 V 2.0

6.0 TJ = 25°C
1.5
IO = 1.0 mA
4.0
1.0 IO = 40 mA
IO = 40 mA IO = 100 mA IO = 1.0 mA
2.0 Dropout of Regulation is
0.5 defined as when
VO = 2% of VO
0 0
0 2.0 4.0 6.0 8.0 10 0 25 50 75 100 125
VI, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Dropout Characteristics Figure 4. Dropout Voltage versus
Junction Temperature
4.2 5.0
I IB , INPUT BIAS CURRENT (mA)
I IB , INPUT BIAS CURRENT (mA)

4.0
4.0
3.8
3.0 MC78L05AC
3.6
Vout = 5.0 V
IO = 40 mA
3.4 2.0 TJ = 25°C
3.2 MC78L05AC
VI = 10 V 1.0
3.0 VO= 5.0 V
IO = 40 mA
0 0
0 25 50 75 100 125 0 5.0 10 15 20 25 30 35 40
TA, AMBIENT TEMPERATURE (°C) VI, INPUT VOLTAGE (V)
Figure 5. Input Bias Current versus Figure 6. Input Bias Current
Ambient Temperature versus Input Voltage
R θ JA, THERMAL RESISTANCE JUNCTION‐TO‐AIR (° C/W)
10,000 170 3.2
PD, MAXIMUM POWER DISSIPATION (W)

150 2.8
PD , POWER DISSIPATION (mW)
PD(max) for TA = 50°C

No Heatsink 130 2.4
ÎÎÎ ÎÎÎ
1000
110 2.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
Graph represents symmetrical layout
ÎÎÎ
ÎÎÎ
ÎÎÎ
90 2.0 oz. 1.6
L
Copper
100 70 1.2
L 3.0 mm
RqJA = 200°C/W 50 0.8
PD(max) to 25°C = 625 mW RqJA
10 30 0.4
25 50 75 100 125 150 0 10 20 30 40 50
TA, AMBIENT TEMPERATURE (°C) L, LENGTH OF COPPER (mm)
Figure 7. Maximum Average Power Dissipation versus Figure 8. SOIC−8 Thermal Resistance and Maximum
Ambient Temperature − TO−92 Type Package Power Dissipation versus P.C.B. Copper Length
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APPLICATIONS INFORMATION
Design Considerations input bypass capacitor should be selected to provide good
The MC78L00A Series of fixed voltage regulators are high−frequency characteristics to insure stable operation
designed with Thermal Overload Protection that shuts under all load conditions. A 0.33 mF or larger tantalum,
down the circuit when subjected to an excessive power mylar, or other capacitor having low internal impedance at
overload condition. Internal Short Circuit Protection limits high frequencies should be chosen. The bypass capacitor
the maximum current the circuit will pass. should be mounted with the shortest possible leads directly
In many low current applications, compensation across the regulators input terminals. Good construction
capacitors are not required. However, it is recommended techniques should be used to minimize ground loops and
that the regulator input be bypassed with a capacitor if the lead resistance drops since the regulator has no external
regulator is connected to the power supply filter with long sense lead. Bypassing the output is also recommended.
wire lengths, or if the output load capacitance is large. The
+20V MC78L15A +VO

0.33mF 10k
7 2
Input MC78L05A -
6
R MC1741
0.33mF Constant 3
+
Current to 4
10k
Grounded Load
IO 0.33mF
MPS A70
6.5
20V -VO
The MC78L00 regulators can also be used as a current source MPS U55
when connected as above. In order to minimize dissipation the
MC78L05C is chosen in this application. Resistor R determines Figure 10. +15 V Tracking Voltage Regulator
the current as follows:
5.0 V
IO = + IB
R +VI MC78LXXA +VO
0.33mF 0.1mF
IIB = 3.8 mA over line and load changes
-VI MC79LXXA
For example, a 100 mA current source would require R to be a
0.33mF 0.1mF
50W, 1/2 W resistor and the output voltage compliance would be
the input voltage less 7 V. -VO
Figure 9. Current Regulator Figure 11. Positive and Negative Regulator
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ORDERING INFORMATION
Operating
Device Output Voltage Temperature Range Package Shipping†
MC78L05ABDG 5.0 V TJ = −40° to +125°C SOIC−8 98 Units / Rail
(Pb−Free)
NCV78L05ABDG* 5.0 V TJ = −40° to +125°C SOIC−8 98 Units / Rail

(Pb−Free)
MC78L05ABDR2G 5.0 V TJ = −40° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
NCV78L05ABDR2G* 5.0 V TJ = −40° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
MC78L05ABPG 5.0 V TJ = −40° to +125°C TO−92 2000 Units / Bag
(Pb−Free)
NCV78L05ABPG* 5.0 V TJ = −40° to +125°C TO−92 2000 Units / Bag
(Pb−Free)
MC78L05ABPRAG 5.0 V TJ = −40° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
NCV78L05ABPRAG* 5.0 V TJ = −40° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L05ABPREG 5.0 V TJ = −40° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
NCV78L05ABPREG* 5.0 V TJ = −40° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L05ABPRMG 5.0 V TJ = −40° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
NCV78L05ABPRMG* 5.0 V TJ = −40° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
NCV78L05ABPRPG* 5.0 V TJ = −40° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
MC78L05ACDG 5.0 V TJ = 0° to +125°C SOIC−8 98 Units / Rail
(Pb−Free)
MC78L05ACDR2G 5.0 V TJ = 0° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
MC78L05ACPG 5.0 V TJ = 0° to +125°C TO−92 2000 Units / Bag
(Pb−Free)
MC78L05ACPRAG 5.0 V TJ = 0° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L05ACPREG 5.0 V TJ = 0° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L05ACPRMG 5.0 V TJ = 0° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
MC78L05ACPRPG 5.0 V TJ = 0° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
MC78L05ACHT1G 5.0 V TJ = 0° to +125°C SOT−89 2500 / Tape & Reel
(Pb−Free)
(Pb−Free)
*NCV78L05A, NCV78L12A, NCV78L15A: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifica-
tions Brochure, BRD8011/D.
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ORDERING INFORMATION (continued)

Operating
(Pb−Free)
NCV78L08ABDR2G* 8.0 V TJ = −40° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
MC78L08ABPG 8.0 V TJ = −40° to +125°C TO−92 2000 Units / Bag
(Pb−Free)
(Pb−Free)
MC78L08ABPRPG 8.0 V TJ = −40° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
MC78L08ACPRAG 8.0 V TJ = 0° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L08ACPREG 8.0 V TJ = 0° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L08ACPRPG 8.0 V TJ = 0° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
MC78L09ABPRPG 9.0 V TJ = −40° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
MC78L12ABDG 12 V TJ = −40° to +125°C SOIC−8 98 Units / Rail
(Pb−Free)
MC78L12ABDR2G 12 V TJ = −40° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
NCV78L12ABDG* 12 V TJ = −40° to +125°C SOIC−8 98 Units / Rail
(Pb−Free)
NCV78L12ABDR2G* 12 V TJ = −40° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
MC78L12ABPG 12 V TJ = −40° to +125°C TO−92 2000 Units / Bag
(Pb−Free)
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Operating
MC78L12ABPRPG 12 V TJ = −40° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
NCV78L12ABPG* 12 V TJ = −40° to +125°C TO−92 2000 Units / Bag
(Pb−Free)
MC78L12ACDG 12 V TJ = 0° to +125°C SOIC−8 98 Units / Rail
(Pb−Free)
MC78L12ACDR2G 12 V TJ = 0° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
MC78L12ACPG 12 V TJ = 0° to +125°C TO−92 2000 Units / Bag
(Pb−Free)
MC78L12ACPRAG 12 V TJ = 0° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L12ACPREG 12 V TJ = 0° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L12ACPRMG 12 V TJ = 0° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
MC78L12ACPRPG 12 V TJ = 0° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
MC78L15ABDG 15 V TJ = −40° to +125°C SOIC−8 98 Units / Rail
(Pb−Free)
MC78L15ABDR2G 15 V TJ = −40° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
NCV78L15ABDR2G* 15 V TJ = −40° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
(Pb−Free)
MC78L15ABPRAG 15 V TJ = −40° to +125°C TO−92 2000 / Tape & Reel
(Pb−Free)
MC78L15ABPRPG 15 V TJ = −40° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
MC78L15ACDG 15 V TJ = 0° to +125°C SOIC−8 98 Units / Rail
(Pb−Free)
MC78L15ACDR2G 15 V TJ = 0° to +125°C SOIC−8 2500 / Tape & Reel
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
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Operating
MC78L18ACPRMG 18 V TJ = 0° to +125°C TO−92 2000 / Ammo Pack
(Pb−Free)
(Pb−Free)
(Pb−Free)
NCV78L24ABPRPG* 24 V TJ = −40° to +125°C TO−92 2000 Units / Bag
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
MARKING DIAGRAMS
SOIC−8 TO−92
D SUFFIX P SUFFIX
CASE 751 CASE 029
MC78L MC78L
8 8
zzABP zzACP
8LxxA 8LxxA ALYWG ALYWG
ALYWB ALYWC G G
G G
1 1
xx = 05, 08, 09, 12, or 15

A = Assembly Location
L = Wafer Lot
Y = Year 1 2 3 1 2 3
W = Work Week
B, C = Temperature Range zz = 05, 08, 09, 12, 15, 18 or 24
G = Pb−Free Package A = Assembly Location
L = Wafer Lot
Y = Year
SOT−89
W = Work Week
CASE 528AG
G = Pb−Free Package
(Note: Microdot may be in either location)
Y W
X X
Y = Year
W = Work Week
XX = Specific Device Code
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT

CASE 29−10
SCALE 1:1 ISSUE A
DATE 08 MAY 2012
12 1
2
3 3
STRAIGHT LEAD BENT LEAD
A
NOTES:
STRAIGHT LEAD 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1994.
B 2. CONTROLLING DIMENSION: INCHES.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS
R UNCONTROLLED.
4. DIMENSION F APPLIES BETWEEN DIMENSIONS P
P AND L. DIMENSIONS D AND J APPLY BETWEEN DI
L MENSIONS L AND K MINIMUM. THE LEAD
F DIMENSIONS ARE UNCONTROLLED IN DIMENSION
K P AND BEYOND DIMENSION K MINIMUM.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.175 0.205 4.44 5.21
B 0.290 0.310 7.37 7.87
X X D C 0.125 0.165 3.18 4.19
G D 0.018 0.021 0.46 0.53
F 0.016 0.019 0.41 0.48
H J G 0.045 0.055 1.15 1.39
H 0.095 0.105 2.42 2.66
V C J 0.018 0.024 0.46 0.61
SECTION X−X K 0.500 --- 12.70 ---
L 0.250 --- 6.35 ---
1 N N 0.080 0.105 2.04 2.66
P --- 0.100 --- 2.54
N R 0.135 --- 3.43 ---
V 0.135 --- 3.43 ---
A
NOTES:
R BENT LEAD 1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
B 2. CONTROLLING DIMENSION: INCHES.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS
UNCONTROLLED.
4. DIMENSION F APPLIES BETWEEN DIMENSIONS P
P AND L. DIMENSIONS D AND J APPLY BETWEEN
T DIMENSIONS L AND K MINIMUM. THE LEAD
DIMENSIONS ARE UNCONTROLLED IN DIMENSION
SEATING
PLANE K P AND BEYOND DIMENSION K MINIMUM.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.175 0.205 4.44 5.21
B 0.290 0.310 7.37 7.87
X X D C 0.125 0.165 3.18 4.19
G D 0.018 0.021 0.46 0.53
G 0.094 0.102 2.40 2.80
J J 0.018 0.024 0.46 0.61
V K 0.500 --- 12.70 ---
C N 0.080 0.105 2.04 2.66
SECTION X−X P --- 0.100 --- 2.54
R 0.135 --- 3.43 ---
1 N V 0.135 --- 3.43 ---
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON52857E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TO−92 (TO−226) 1 WATT PAGE 1 OF 2
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE A
DATE 08 MAY 2012
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:

PIN 1. EMITTER PIN 1. BASE PIN 1. ANODE PIN 1. CATHODE PIN 1. DRAIN
2. BASE 2. EMITTER 2. ANODE 2. CATHODE 2. SOURCE
3. COLLECTOR 3. COLLECTOR 3. CATHODE 3. ANODE 3. GATE

PIN 1. GATE PIN 1. SOURCE PIN 1. DRAIN PIN 1. BASE 1 PIN 1. CATHODE
2. SOURCE & SUBSTRATE 2. DRAIN 2. GATE 2. EMITTER 2. GATE
3. DRAIN 3. GATE 3. SOURCE & SUBSTRATE 3. BASE 2 3. ANODE
PIN 1. ANODE PIN 1. MAIN TERMINAL 1 PIN 1. ANODE 1 PIN 1. EMITTER PIN 1. ANODE 1
2. CATHODE & ANODE 2. GATE 2. GATE 2. COLLECTOR 2. CATHODE
3. CATHODE 3. MAIN TERMINAL 2 3. CATHODE 2 3. BASE 3. ANODE 2
PIN 1. ANODE PIN 1. COLLECTOR PIN 1. ANODE PIN 1. GATE PIN 1. NOT CONNECTED
2. GATE 2. BASE 2. CATHODE 2. ANODE 2. CATHODE
3. CATHODE 3. EMITTER 3. NOT CONNECTED 3. CATHODE 3. ANODE
PIN 1. COLLECTOR PIN 1. SOURCE PIN 1. GATE PIN 1. EMITTER PIN 1. MT 1
2. EMITTER 2. GATE 2. SOURCE 2. COLLECTOR/ANODE 2. GATE
3. BASE 3. DRAIN 3. DRAIN 3. CATHODE 3. MT 2
PIN 1. VCC PIN 1. MT PIN 1. CATHODE PIN 1. NOT CONNECTED PIN 1. DRAIN
2. GROUND 2 2. SUBSTRATE 2. ANODE 2. ANODE 2. GATE
3. OUTPUT 3. MT 3. GATE 3. CATHODE 3. SOURCE
PIN 1. GATE PIN 1. BASE PIN 1. RETURN PIN 1. INPUT PIN 1. GATE
2. DRAIN 2. COLLECTOR 2. INPUT 2. GROUND 2. COLLECTOR
3. SOURCE 3. EMITTER 3. OUTPUT 3. LOGIC 3. EMITTER
DOCUMENT NUMBER: 98AON52857E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TO−92 (TO−226) 1 WATT PAGE 2 OF 2
rights of others.

PACKAGE DIMENSIONS
SOT−89, 3 LEAD
CASE 528AG
ISSUE O
DATE 04 MAR 2014
SCALE 2:1
A NOTES:
D 1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. LEAD THICKNESS INCLUDES LEAD FINISH.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
E H 5. DIMENSIONS L, L2, D2, AND H ARE MEASURED AT
DATUM PLANE C.
6. CENTER LEAD CONTOUR MAY VARY WITHIN THE
REGION DEFINED BY DIMENSION E.
1 2 3 7. DIMENSION D2 IS DEFINED AT ITS WIDEST POINT.
MILLIMETERS
DIM MIN MAX
TOP VIEW A 1.40 1.60
b 0.38 0.47
b1 0.46 0.55
c 0.40 0.44
D 4.40 4.60
c D2 1.60 1.90
A
E 2.40 2.60
e 1.50 BSC
0.10 C H 4.05 4.25
L 0.89 1.20
C SIDE VIEW
GENERIC
e e MARKING DIAGRAM*
b1 b L2
Y W
1 2 3
L X X
Y = Year
W = Work Week
XX = Specific Device Code
B D2
*This information is generic. Please refer
BOTTOM VIEW to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
RECOMMENDED
MOUNTING FOOTPRINT*
PACKAGE 2.00
OUTLINE
4.45
1.57
1 0.86
2X 0.50
0.58
2X 1.50
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER: 98AON82692F Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: SOT−89, 3 LEAD PAGE 1 OF 1
rights of others.

PACKAGE DIMENSIONS
SOIC−8 NB
8 CASE 751−07
1 ISSUE AK
SCALE 1:1 DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
ALYWX ALYWX AYWW AYWW
1.52
G G
0.060
1 1 1 1
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week G = Pb−Free Package
G = Pb−Free Package
0.6 1.270 *This information is generic. Please refer to

0.024 0.050 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
SCALE 6:1 ǒinches
mm Ǔ or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: SOIC−8 NB PAGE 1 OF 2
rights of others.

SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1: STYLE 2: STYLE 3: STYLE 4:
PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE
5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE
6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE
7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE
PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1
2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1
3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2
4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2
5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2
6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2
7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1
8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1
PIN 1. EMITTER, COMMON PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE
2. COLLECTOR, DIE #1 2. BIAS 1 2. GATE 1 2. SOURCE
3. COLLECTOR, DIE #2 3. OUTPUT 3. SOURCE 2 3. SOURCE
4. EMITTER, COMMON 4. GROUND 4. GATE 2 4. GATE
5. EMITTER, COMMON 5. GROUND 5. DRAIN 2 5. DRAIN
6. BASE, DIE #2 6. BIAS 2 6. DRAIN 2 6. DRAIN
7. BASE, DIE #1 7. INPUT 7. DRAIN 1 7. DRAIN
8. EMITTER, COMMON 8. GROUND 8. DRAIN 1 8. DRAIN

PIN 1. N.C. PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1
2. SOURCE 2. N−GATE 2. ANODE 1 2. BASE, DIE #1
3. SOURCE 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2
4. GATE 4. P−GATE 4. ANODE 1 4. BASE, DIE #2
5. DRAIN 5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2
6. DRAIN 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2
7. DRAIN 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1
8. DRAIN 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1

PIN 1. VCC PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N)
2. V2OUT 2. ANODE 2. GATE 1 2. GATE (N)
3. V1OUT 3. SOURCE 3. SOURCE 2 3. SOURCE (P)
4. TXE 4. GATE 4. GATE 2 4. GATE (P)
5. RXE 5. DRAIN 5. DRAIN 2 5. DRAIN
6. VEE 6. DRAIN 6. MIRROR 2 6. DRAIN
7. GND 7. CATHODE 7. DRAIN 1 7. DRAIN
8. ACC 8. CATHODE 8. MIRROR 1 8. DRAIN
PIN 1. CATHODE 1 PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE
2. CATHODE 2 2. COMMON CATHODE/VCC 2. COMMON ANODE/GND 2. EMITTER
3. CATHODE 3 3. COMMON CATHODE/VCC 3. COMMON ANODE/GND 3. COLLECTOR/ANODE
4. CATHODE 4 4. I/O LINE 3 4. LINE 2 IN 4. COLLECTOR/ANODE
5. CATHODE 5 5. COMMON ANODE/GND 5. LINE 2 OUT 5. CATHODE
6. COMMON ANODE 6. I/O LINE 4 6. COMMON ANODE/GND 6. CATHODE
7. COMMON ANODE 7. I/O LINE 5 7. COMMON ANODE/GND 7. COLLECTOR/ANODE
8. CATHODE 6 8. COMMON ANODE/GND 8. LINE 1 OUT 8. COLLECTOR/ANODE

PIN 1. VIN PIN 1. GND PIN 1. ILIMIT PIN 1. SW_TO_GND
2. N/C 2. dv/dt 2. OVLO 2. DASIC_OFF
3. REXT 3. ENABLE 3. UVLO 3. DASIC_SW_DET
4. GND 4. ILIMIT 4. INPUT+ 4. GND
5. IOUT 5. SOURCE 5. SOURCE 5. V_MON
6. IOUT 6. SOURCE 6. SOURCE 6. VBULK
7. IOUT 7. SOURCE 7. SOURCE 7. VBULK
8. IOUT 8. VCC 8. DRAIN 8. VIN
STYLE 29: STYLE 30:
PIN 1. BASE, DIE #1 PIN 1. DRAIN 1
2. EMITTER, #1 2. DRAIN 1
3. BASE, #2 3. GATE 2
4. EMITTER, #2 4. SOURCE 2
5. COLLECTOR, #2 5. SOURCE 1/DRAIN 2
8. COLLECTOR, #1 8. GATE 1
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: SOIC−8 NB PAGE 2 OF 2
rights of others.

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MC78L00A Series, NCV78L00A 100 Ma Positive Voltage Regulators

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MC78L00A Series,

100 mA Positive Voltage

DEVICE MARKING INFORMATION

© Semiconductor Components Industries, LLC, 1999 1 Publication Order Number:

This datasheet has been downloaded from http://www.digchip.com at this page

Input MC78LXXA Output

Figure 2. Standard Application

ABSOLUTE MAXIMUM RATINGS

V I -V O , INPUT/OUTPUT DIFFERENTIAL VOLTAGE (V)

Vout = 5.0 V 2.0

I IB , INPUT BIAS CURRENT (mA)

10,000 170 3.2

PD, MAXIMUM POWER DISSIPATION (W)

PD(max) for TA = 50°C

+20V MC78L15A +VO

Figure 9. Current Regulator Figure 11. Positive and Negative Regulator

NCV78L05ABDG* 5.0 V TJ = −40° to +125°C SOIC−8 98 Units / Rail

ORDERING INFORMATION (continued)

ORDERING INFORMATION (continued)

ORDERING INFORMATION (continued)

xx = 05, 08, 09, 12, or 15

TO−92 (TO−226) 1 WATT

DESCRIPTION: TO−92 (TO−226) 1 WATT PAGE 1 OF 2

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:

STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10:

DESCRIPTION: TO−92 (TO−226) 1 WATT PAGE 2 OF 2

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

*For additional information on our Pb−Free strategy and soldering

DESCRIPTION: SOT−89, 3 LEAD PAGE 1 OF 1

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

0.6 1.270 *This information is generic. Please refer to

DESCRIPTION: SOIC−8 NB PAGE 1 OF 2

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

STYLE 13: STYLE 14: STYLE 15: STYLE 16:

STYLE 17: STYLE 18: STYLE 19: STYLE 20:

STYLE 25: STYLE 26: STYLE 27: STYLE 28:

DESCRIPTION: SOIC−8 NB PAGE 2 OF 2

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

PUBLICATION ORDERING INFORMATION

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