Input Output Interface:  

  

     Input-output interface provides a method for transferring information between internal storage
and external I/O devices. Peripherals connected to a computer need special communication links
for interfacing them with the central processing unit. The purpose of the communication link is
to resolve the differences that exist between the central computer and each peripheral. The major
differences are:

1. Peripherals are electromechanical and electromagnetic devices and their manner of

operation is different from the operation of the CPU and memory, which are electronic
devices. Therefore, a conversion of signal values may be required.
2. The data transfer rate of peripherals is usually slower than the transfer rate of the CPU,
and consequently, a synchronization mechanism may be needed.
3. Data codes and formats in peripherals differ from the word format in the CPU and
memory.
4. The operating modes of peripherals are different from each other and each must be
controlled so as not to disturb the operation of other peripherals connected to the CPU.

     To resolve these differences, computer systems include special hardware components
between the CPU and peripherals to supervise and synchronize all input and output transfers.
These  components are called interface units because they interface between the processor bus
and the peripheral device.

Need for I/O interface

1. Peripherals are electromechanical devices.But CPU and Memory are electronic devices.
Therefore conversion of signal values may be required.
2. Data codes and formats in peripherals differ from the word format in CPU and memory.
3. Data transfer rate of peripherals are slower than CPU, So synchronization may be needed.
4. The operating modes of peripherals are different. So they must be controlled so as not to
disturb the operation of other peripherals that are connected to CPU.

When Memory and I/O devices are interfaced to a processor either an isolated I/O scheme or
memory mapped I/O scheme is used.

Isolated I/O:
     The isolated I/O configuration separates all I/O interface addresses from the memory
addresses. In the isolated I/O configuration, the CPU has distinct input and output instructions. In
isolated I/O configuration the memory address and I/O address have its own address space. If the
address of interface registers are placed on the  address lines the I/O read or I/O write control
lines are enabled. If the memory address is placed on the address lines the memory read and
memory write control lines are enabled.
Memory - Mapped I/O:
     In this configuration same address space is used for both memory and I/O. There are no
specific I/O instructions. It allows the computer to used the same instructions for both I/O
transfers and  memory transfers. Some instructions are memory reference instructions and others
are I/O reference. They are only one set of read/write control signals

This method of asynchronous data transfer uses a single control line to time each transfer. The
strobe may be activated by the source or the destination unit.

(i) Source Initiated Data Transfer:

 The data bus carries the information from source to destination. The strobe is a single
line. The signal on this line informs the destination unit when a data word is available in
the bus.

 The strobe signal is given after a brief delay, after placing the data on the data bus. A
brief period after the strobe pulse is disabled the source stops sending the data.

Source - initiated strobe for data transfer

(ii) Destination Initiated Data Transfer:

 In this case the destination unit activates the strobe pulse informing the source to send
data. The source places the data on the data bus. The transmission is stopped briefly after
the strobe pulse is removed.

 The disadvantage of the strobe is that the source unit that initiates the transfer has no way
of knowing whether the destination unit has received the data or not. Similarly if the
destination initiates the transfer it has no way of knowing whether the source unit has
placed data on the bus or not. This difficulty is solved by using hand shaking method of
data transfer.
Destination - initiated strobe for data transfer

An example of an I/O interface unit is shown in figure. It consists of two data registers called
ports, a control register, a status register, bus buffers and timing and control circuits.

     The four registers communicate directly with the I/O device attached to the interface. The I/O
data  to and from the device can be transferred into either port A or port B. Port A may be
defined as an input port and port B may be defined as an output port. The output device such as
magnetic disk transfers data in both directions. So bidirectional data bus is used. CPU gives
control information to control register. The bits in the status register are used for status
conditions. It is also used for recording errors that may occur during the data transfer. The bus
buffers use the bidirectional data bus to communicate with the CPU. A timing and control circuit
is used to detect the address assigned to the bus buffers.

Register
CS RS1 RS0
selected
None: data bus
0 X X in high-
impedance
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register

Input and Output Organization–Summary

1. Peripheral Devices :
(a) The devices used to communicate with the computers are called peripheral devices.
(b) If the device input the data to the computer then it is a input device
(c) Output devices are these get the data from the computer
(d) The devices which communicate to the computer and from the computer an input-output
devices

2. Peripheral Interface : The hardware unit that is placed between the computer and the I/O
devices is known as peripheral interface.

3. Data Transfer Modes :

(a) In case of synchronous data transfer, the source and destination systems share a common
clock frequency and data in transmitted continuously at the rate given by the clock pulse.
(b) Storage controlled data transfer uses a single control line to time each data transfer. The
strobe may be activated either by source or the destination unit.
(c) In the case of the destination initiated data transfer, the destination unit activates the strobe
pulse informing the source to send data.
(d) In case of hand shaking, the control signal is introduced that provides a reply to the unit that
initiated the data transfer
(i) Source initiated data transferring method uses a signal generated by the source unit and data
accepted signal is generated by the destination unit
(ii) In case of the destination initiated data transfer, the source unit does not place the data for
transfer, unless it receives the ready for data signal from the destination unit.
(e) Data item transfers if initiated by an instruction in the program, then it is known as
programmed I/O method of data transfer.
(f) A priority interrupt is a system that gives a priority over the various sources to determine
which interrupt is to be served first when two or more request arrive simultaneously the parity
interrupt can be established by software or hardware.
(g) In direct memory access (DMA) extra hardware is implement which provides a direct path to
memory for I/O data transfers.

4. Input Output Processor : A general purpose CPU which is dedicated for I/O operations is
replaced by a I/O units is called I/O processors (IOP).

5. Bus System :
(a) Buses are the physical link between different units with in the computers and between it and
its peripheral devices.
(b) Input output bus is used for most of the I/O operations.
(c) Memory bus is used for communication between memory and CPU
(d) System bus consist of control bus, address bus and data bus.

Asynchronous Data Transfer

This data transfer takes place in two different ways (i) Strobe Control (ii) Hand Shaking.

1. Strobe Control : This method of asynchronous data transfer uses a single control line to time
each transfer. The strobe may be activated by the source or the destination unit.

(i) Source Initiated Data Transfer:

The data bus carries the information from source to destination. The strobe is a single line. The
signal on this line informs the destination unit when a data word is available in the bus.
The strobe signal is given after a brief delay, after placing the data on the data bus. A brief period
after the strobe pulse is disabled the source stops sending the data.

(ii) Destination Initiated Data Transfer:

In this case the destination unit activates the strobe pulse informing the source to send data. The
source places the data on the data bus. The transmission is stopped briefly after the strobe pulse
is removed.

The disadvantage of the strobe is that the source unit that initiates the transfer has no way of
knowing whether the destination unit has received the data or not. Similarly if the destination
initiates the transfer it has no way of knowing whether the source unit has placed data on the bus
or not. This difficulty is solved by using hand shaking method of data transfer.
Synchronous Data Transfer
In this scheme the transmitter and the receiver share a common clock frequency and bits are
transmitted continuously at the rate given by the clock pulses. This type of transmission is
preferred when the speed of the I/O device and CPU are almost same whenever an I/O operation
is to be performed a suitable instruction is issued by the CPU. If the distance between source and
the destination are small, same clock is used. In long distance data transfer each unit is driven by
a separate clock of the same frequency. Synchronization signals are transmitted periodically
between the two units to keep their clocks in step with each other. This scheme is simplest of all
data transfer schemes

Handshaking
In hand shaking method second control signal is introduced that provides a reply to the unit that
initiates the transfer. In this scheme also there are two ways.

Source Initiated Transfer Using Hand Shaking:

The figure shows the data transfer procedure when initiated by the source. The two handshaking
lines are data valid which is generated by the source unit and data accepted generated by the
destination unit. The timing diagram shows the exchange of signals between two units. The
source unit initiates the transfer by placing the data on the bus and enabling its data valid signal.
The data accepted signal is activated by the destination unit after it accepts the data from the bus.
The source unit then disables its data valid signal, which invalidates the data on the bus. The
destination unit disables its data accepted signal and the system goes into its initial state.

Destination Initiated Transfer Using Hand Shaking:

The destination initiated transfer using hand shaking lines is as shown in the figure. The source
unit in this case does not place data on the bus until after it receives the ready for data signal
from the destination unit. From this onwards the hand shaking procedure follows the same
pattern as in the source – initiated case.

The hand shaking scheme provides a high degree of flexibility and reliability.
Data Transfer Modes
In a computer system data transfer takes place between (i) CPU and Memory (ii) CPU and I/O
devices (iii) Memory and I/O devices. Various data transfer modes are developed for this
purpose which helps in compensating the time delays etc. The two basic categories used for data
transfer are :

1. Programmed Data Transfer.

2. Direct Memory Access Transfer.

The basic difference between the two is the first one uses a software routine for data transfer
whereas in the later the processor is held till the data transfer is over.

The different types of data transfer modes are :

1. Synchronous and Asynchronous data transfer.

2. Hand Shaking Method of data transfer.
3. Programmed I/O method of data transfer.
4. DMA and priority interrupt mode of data transfer.

Programmed I/O Method of Data Transfer

Programmed I/O operations are the result of I/O instructions written in computer program. Each
data item transfer is initiated by an instruction in the program. The I/O device does not have
direct access to memory. A transfer from an I/O device to memory requires the execution of
several instructions by the CPU. The data transfer can be synchronous or asynchronous
depending upon the type and the speed of the I/O devices.

If the speeds match then synchronous data transfer is used. When there is mismatch then
asynchronous data transfer is used. The transfer is to and from a CPU register and peripheral.
Other instructions are needed to transfer the data to and from CPU and memory. This method
requires constant monitoring of the peripheral by the CPU. Once a data transfer is initiated the
CPU is required to monitor the interface to see when a transfer can again be made.

In this method the CPU stays in a loop till the I/O unit indicates that it is ready for data transfer.
This is time consuming process which can be solved by using interrupt.
DMA and Priority Interrupt Mode of Data
Transfer
In a computer application a number of I/O devices are attached to the computer with each device
being able to give an interrupt request. The first job of the CPU is to identify which device has
interrupted. There is also the possibility that several I/O devices may interrupt the CPU at a time.
In this case the system must be in a position to identify which device should be serviced first. A
priority interrupt is a system that gives a priority over the various sources to determine which
interrupt is to be serviced first when two or more requests arrive simultaneously. When two
devices interrupt the computer at the same time the computer services the device with the higher
priority first.

The priority interrupt can he established using either software or hardware. In software polling a
simple procedure is used. Each and every source is tested for interrupt starting from the highest
priority source. After identifying the source control is transferred to its service subroutine
corresponding to that source.

DMA Data Transfer :

A hardware priority interrupt unit functions as an overall manager in an interrupt system

environment. It accept interrupt requests from many sources, determines which of the incoming
request has the highest priority and issues an interrupt request to the computer, based on this
determination. Other types of priority interrupts are daisy chaining priority and vectored
interrupts.

For data transfer in this scheme extra hardware is implemented. This hard ware enables the I/O
unit to transfer data directly from a peripheral to main memory without going through the control
unit and ALU. Because it provides a direct path to memory for I/O data transfers it has been
given the name direct memory access or DMA.
DMA unit has some intelligence and decision making ability in its control logic, but it must be
told what operations to be performed. This is done by having the CPU store information into
DMA controller. This is called programming the DMA.

It is required that the DMA unit to transfer a block of data from a peripheral into memory.
Examine the DMA program for this operation. The program and its corresponding flow chart
that setup the DMA are shown in figure. Programming the DMA is simple. All that is required is
store the necessary information into the registers in the DMA. Once this is complete the DMA
transfer is initiated with the I/O start command just as though it were a peripheral. DMA-
performs only data transfer, the CPU must send commands to the I/O unit that will cause the
peripheral device to start the desired operation. After the peripheral has been started the DMA
unit takes over control of the data transfer. It sends all the signals to the system and I/O buses
necessary to complete the transfer.

Advantages of DMA Transfer:

1. Useful for transferring bulk amounts of data.
2. The data can be transferred at fastest rate.
3. CPU can be utihsed for other jobs during the process of DMA.

For a DMA transfer the following sequences of events happens.

1. The peripheral controller places an interrupt request signal on the 10 bus signifying that it is
ready to transfer data.
2. The DMA recognizes that the interrupt request is from the device it is controlling.
3. The DMA sends an interrupt acknowledge to the-peripheral
4. The peripheral places data on the I/O bus.
5. The DMA stores the data into its data assembly register.
6. The DMA takes control of the system bus.
7. The DMA places the contents of its memory address register onto the system bus along with a
memory write request.
8. After completion of the memory write,the DMA relinquishe s control of the system bus.
9. The DMA increments its memory address register and decrements its word count register.
10. If the word count register is zero the DMA sends an interrupt request to the 10 unit.

Each time the device is ready to transfer data to memory the DMA unit takes over and performs
the above operations. These operations are called cycle stealing.

The DMA must share the system bus with the CPU therefore something must be responsible for
deciding which
will be given control of the bus when both want the bus. The logic that makes this decision is
called bus arbiter

Interrupt initiated I/O

• This can be avoided by using an interrupt facility and special commands to inform the interface
to issue an interrupt request signal when the data are available from the device.

• Meanwhile, CPU can proceed to execute another program. The interfaces keeps monitoring the
device.

• When the interface determines that the device is ready for data transfer, it generates an
interrupt request to the computer.
and control), categories of I/O operations, and I/O interfacing. INPUT/OUTPUT  PROCESSOR
For those computers that have an I/O processor, the physical organization of I/O is similar to the
other major functional areas: CPU and memory. I/O processors can vary from many pcb’s that
makeup a module/unit to a single  pcb.  Larger  mainframe  computers  use  the modular
arrangement: multiple  components  on multiple pcb’s that comprise one or more modules or
units. Mini-  and  microcomputers  use  chassis  or assemblies, cages or racks, and
motherboard/backplane arrangements. Minis   and   micros   use   multiple components on one
pcb or groups of pcb’s (usually not more than seven) to form the I/O processor. The  I/O
processor  controls  the  transfer  of information between the computer’s main memory and the
external  equipments.  I/O  processors  are  packaged two different ways: (1) IOC/IOA modules
or multiple IOC/IOA pcb’s, and (2) I/O pcb’s. Regardless of the setup, computers with an I/O
processor will use some sort of controller to regulate the signals in the I/O processor  itself
(includes  IOC/IOA  setup)  and  memory. IOC/IOA Module or Multiple IOC/IOA Pcb’s I/O
processors  that  are  packaged  as  IOC/IOA modules or multiple IOC/IOA pcb’s are divided
into two  sections.  The  two  sections  are  a  single  module/unit or group of pcb’s for the I/O
controller (IOC) and a single module/unit or group of pcb’s for the  I/O adapter (IOA) (fig. 7-2).
Mainframes and some minis use this arrangement. IOC. —The IOC relieves the CPU of the
necessity to   perform   the   time   consuming   functions   of establishing,  directing,  and
monitoring  transfers  with external  equipments. Data and control signals are exchanged  with
external  equipments  via  the  IOA.  IOCs communicate by means of a bidirectional bus. An
IOC is   provided   with   a   repertoire   of   instructions (commands) that varies with the type of
computer. The IOC contains the necessary control and timing circuits (digital) necessary to
function asynchronously with the CPU  and  controls  the  transfer  of  data  between accessible
main memory and the external equipments. IOC  programs  are  initiated  by  instructions  from
the CPU and executed by a repertoire of IOC commands stored in main memory. Included in the
repertoire are those commands that establish the conditions for data

Memory Mapped I/O versus Isolated I/O

Although this concept was explained earlier as well, it will be useful to review it again in this
context. In isolated I/O, a separate address space of the CPU is reserved for I/O operations. This
address space is totally different from the address space used for memory devices. In other
words, a CPU has two distinct address spaces, one for memory and one for input/output. Unique
CPU instructions are associated with the I/O space, which means that if those instructions are
executing on the CPU, then the accessed address space will be the I/O space and hence the
devices mapped on the I/O space. The x86 family with the in and the out instructions is a well
known example of this situation. Using the in instruction, the Pentium processor can receive
information from a peripheral device, and using the out instruction, the Pentium processor can
send information to a peripheral device. Thus, the I/O devices are mapped on the I/O space in
case of the Pentium processor. In some processors, like the SRC, there is no separate I/O space.
In this case, some address space out of the memory address space must be used to map I/O
devices. The benefit will be that all the instructions which access memory can be used for I/O
devices. There is no need for including separate I/O instructions in the ISA of the processor.
However, the disadvantage will be that the I/O interface will become complex. If partial
decoding is used to reduce the complexity of the I/O interface, then a lot of memory addresses
will be consumed. The given figure shows the memory address space

Last Modified: 01-Nov-06

as well as the I/O address space for the Pentium processor. The I/O space is of size 64 Kbytes,
organized as eight banks of 8 Kbytes each. A similar diagram for the FALCON-A was shown
earlier and is repeated here for easy reference. The next question to be answered is how the CPU
will differentiate between these two address spaces. How will the system components know
whether a particular transfer is meant for memory or an I/O device? The answer is simple: by
using signals

from the control bus, the CPU will indicate which address space is meant during a particular
transfer. Once again, using the Pentium as an example, if the in instruction is executing on the
processor, the IOR# signal will become active and the MEMR# signal will be deactivated. For a
mov instruction, the control logic will activate the MEMR# signal instead of the IOR# signal.
 Unit 5
Auxiliary memory
You are now clear that the operating speed of primary memory or main memory should be as
fast as possible to cope up with the CPU speed. These high-speed storage devices are very
expensive and hence the cost per bit of storage is also very high. Again the storage capacity of
the main memory is also very limited. Often it is necessary to store hundreds of millions of bytes
of data for the CPU to process. Therefore additional memory is required in all the computer
systems. This memory is called auxiliary memory or secondary storage.

In this type of memory the cost per bit of storage is low. However, the operating speed is slower
than that of the primary storage. Huge volume of data are stored here on permanent basis and
transferred to the primary storage as and when required. Most widely used secondary storage
devices are magnetic tapes and magnetic disk.

Magnetic drum
  A direct-access, or random-access, storage device. A magnetic drum, also referred to as
drum, is a metal cylinder coated with magnetic iron-oxide material on which data and
programs can be stored. Magnetic drums were once used as a primary storage device but
have since been implemented as auxiliary storage devices.

 The tracks on a magnetic drum are assigned to channels located around the circumference
of the drum, forming adjacent circular bands that wind around the drum. A single drum
can have up to 200 tracks. As the drum rotates at a speed of up to 3,000 rpm, the device's
read/write heads deposit magnetized spots on the drum during the write operation and
sense these spots during a read operation. This action is similar to that of a magnetic tape
or disk drive.

 Unlike some disk packs, the magnetic drum cannot be physically removed. The drum is
permanently mounted in the device. Magnetic drums are able to retrieve data at a quicker
rate than tape or disk devices but are not able to store as much data as either of them.

Magnetic disk
The primary computer storage device. Like tape, it is magnetically recorded and can be
re-recorded over and over. Disks are rotating platters with a mechanical arm that moves a
read/write head between the outer and inner edges of the platter's surface. It can take as long as
one second to find a location on a floppy disk to as little as a couple of milliseconds on a fast
hard disk. See hard disk for more details.

Tracks and Spots

The disk surface is divided into concentric tracks (circles within circles). The thinner the tracks,
the more storage. The data bits are recorded as tiny magnetic spots on the tracks. The smaller the
spot, the more bits per inch and the greater the storage.

Sectors
Tracks are further divided into sectors, which hold a block of data that is read or written at one
time; for example, READ SECTOR 782, WRITE SECTOR 5448. In order to update the disk,
one or more sectors are read into the computer, changed and written back to disk. The operating
system figures out how to fit data into these fixed spaces. Modern disks have more sectors in the
outer tracks than the inner ones because the outer radius of the platter is greater than the inner
radius

Magnetic tape
 Magnetic tape is an information storage medium consisting of a magnetisable coating on
a thin plastic strip. Nearly all recording tape is of this type, whether used for video with a
video cassette recorder, audio storage (reel-to-reel tape, compact audio cassette, digital
audio tape (DAT), digital linear tape (DLT) and other formats including 8-track
 cartridges) or general purpose digital data storage using a computer (specialized tape
formats, as well as the above-mentioned compact audio cassette, used with home
computers of the 1980s, and DAT, used for backup in workstation installations of the
1990s).

 Magneto-optical and optical tape storage products have been developed using many of
the same concepts as magnetic storage, but have achieved little commercial success.

Associative Memory
 Also called as Content-addressable memory (CAM), associative storage, or associative
array
 Content-addressed or associative memory refers to a memory organization in which the
memory is accessed by its content (as opposed to an explicit address).
 It is a special type of computer memory used in certain very high speed searching
applications.
 In standard computer memory (random access memory or RAM) the user supplies a
memory address and the RAM returns the data word stored at that address.
 In CAM the user supplies a data word and then CAM searches its entire memory to see if
that data word is stored anywhere in it. If the data word is found, the CAM returns a list
of one or more storage addresses where the word was found.
 CAM is designed to search its entire memory in a single operation.
 It is much faster than RAM in virtually all search applications.
 An associative memory is more expensive than RAM, as each cell must have storage
capability as well as  logic circuits for matching its content with an external argument.
 Associative memories are used in applications where the search time is very critical and
short.
 Associative memories are expensive compared to RAMs because of the add logic
associated with each cell.

Cache memory
      Cache (pronounced cash) memory is extremely fast memory that is built into a computer’s central
processing unit (CPU), or located next to it on a separate chip. The CPU uses cache memory to store
instructions that are repeatedly required to run programs, improving overall system speed. The
advantage of cache memory is that the CPU does not have to use the motherboard’s system bus for
data transfer. Whenever data must be passed through the system bus, the data transfer speed slows to
the motherboard’s capability. The CPU can process data much faster by avoiding the bottleneck created
by the system bus.

CACHE  WRITE
 

Write Through
         When writing into memory
                If Hit, both Cache and memory is written in parallel
                If Miss, Memory is written  For a read miss, missing block may be overloaded onto a
cache block
         Memory is always updated
         -> Important when CPU and DMA I/O are both executing Slow, due to the memory access
time
Write-Back (Copy-Back)
         When writing into memory
                If Hit, only Cache is written
                If Miss, missing block is brought to Cache and write into Cache For a read miss,
candidate block must be
                written back to the memory   

PERFORMANCE  OF  CACHE

Memory Access

   * All the memory accesses are directed first to Cache

   * If the word is in Cache; Access cache to provide it to CPU
   * If the word is not in Cache; Bring a block (or a line) including that word to replace a block now in
Cache

   - How can we know if the word that is required is there ?

   - If a new block is to replace one of the old blocks,which one should we choose ?

Performance of Cache Memory System

     Hit Ratio - % of memory accesses satisfied by Cache memory system

     Te:  Effective memory access time in Cache memory system
     Tc:  Cache access time
     Tm: Main memory access time

             Te = Tc + (1 - h) Tm

             Example: Tc = 0.4 ms, Tm = 1.2ms, h = 0.85%

                                   Te = 0.4 + (1 - 0.85) * 1.2 = 0

Virtual memory
    Virtual memory is a conccept used in large computers that permit the user to write large programs as
if the user has large main memory equal to that of the size of the auxiliary memory. This is made
possible by suitable mapping schemes which translate the CPU generated addresses (virtual address)
into physical memory addresses.