CHAPTER FIVE

INTERFACE AND COMMUNICATION

 Interface
Interface: is the special hardware components b/n the CPU and
peripherals to supervise and synchronize all inputs and outputs
transfer.
I/O interface: provides a method for transferring information between
internal storage and external I/O devices.
• Peripherals connected to a computer need special communication links for
interfacing them with the CPU.

I/O Bus and I/O Modules

 I/O Bus: a typical communication link b/n the processor and several
peripherals
 It consists of Data lines, Address line and Control lines
 I/O Modules
Module Function :The major functions or requirements for an I/O module fall
into the following categories:
-Control & Timing
– CPU Communication

– Device Communication
– Data Buffering
– Error Detection

Control and Timing:

 Required because of multiple devices communicating on the same

channel. Example : CPU checks I/O module device status

I/O module returns status
If ready, CPU requests data transfer
I/O module gets data from device
3
I/O module transfers data to CPU
CPU Communication :
 Commands from processor
Examples: READ SECTOR, WRITE SECTOR, SEEK track number
Data: Passed back and forth over the data bus
 Status reporting
• Request from the processor for the I/O Module's status
• May be as simple as BUSY and READY
 Address recognition
• The I/O module must recognize one unique address for each device
it controls

Device Communication
 Specific to each device (commands, status, data)
Data Buffering
 Due to the differences in speed (device is usually orders of magnitude
slower) the I/O module needs to buffer data to keep from tying up the CPU's
bus with slow reads or writes

Error Detection
− Distribute the error handling to the module
o Malfunctions by device (paper jam)
o Data errors (parity checking at the device level)
o Internal errors to the I/O module such as buffer overruns
I/O Module Structure

6
 Asynchronous Data Transfer
Synchronous data transfer:
• if the internal operations in a digital system are synchronized by means of
clock pluses supplied by a common pluses generator
• Clock pluses are applied to all registers within a unit and all data transfer
among internal registers occur simultaneously during the occurrences of a
clock pluses.
• Example two units CPU and an I/O interface design independently each other,
but the registers in the interface share a common clock with the CPU register,
then the transfer b/n the two units said to be Synchronous
• But, the internal timing in each unit is independent from the other, in that
case each uses its own private clock for the internal registers, and the two
units said to be asynchronous to each others. 7
• Asynchronous data transfer wide approach used in most computer system
• Asynchronous data transfer between two independent units requires Control
signals to indicates the time at which data is being transmitted.
• the data transfer in asynchronous mechanism may done either parallel or serials
ways
• In parallel data transmissions, each bit of message/ information has its own
path and the total message/information is transmitted at the same time.
o i.e. n- bit message must to be transmitted through n separate conductor
paths
o It is faster, but requires more wire
o It is used in short distances and its speed is important

• Serial transmission: each bit in the message is sent in sequences one at a time.
o it uses one pair of conductor or one conductor and a common ground
8
o It is slower , but less expensive since require only one pair of conductor
 Modes of Transfer
• Binary information received from an external devices is usually stored in
memory for later processing.
• Data transfer between the central computer and I/O devices may be
handled in a variety of modes.
• Some modes use the CPU as an intermediate path, others transfer the data
directly to and from the memory unit
• Data transfer to and from peripheral can be handled one of the three
possible modes
I. Programmed I/O
II. Interrupt -initiated I/O
III. Direct Memory Access (DMA)
Modes of Transfer

10
 1. Programmed I/O
 The CPU handles the transfers, which take place between registers and the
devices.
The main hardware components required for communications between the
processor and I/O devices.
 Programmed I/O operation are the result of I/O instructions written in the
computer program.
 Each data item transfer is initiated by an instruction in the program.
 Usually the transfer is to and from a CPU register and peripherals
 And other instructions needed to transfer the data to and from a CPU and
memory
2. Interrupt-initiated I/O
 An alternative to the CPU constantly monitoring the flag is to let the
interface inform the computer when it is ready to transfer data. This mode of
transfer uses the interrupt facility.
 While the CPU is running a program, it does not check the flag.
 However, when the flag is set, the computer is momentarily interrupted from
proceeding with the current program and is informed of the fact that the flag
has been set.
 The CPU deviates from what it is doing to take care of the input or output
transfer. After the transfer is completed, the computer returns to the previous
program to continue what it was doing before the interrupt.
Priority Interrupt
 A priority interrupt is a system that establishes a priority over the various
sources to determine which condition is to be serviced first when two or more
requests arrive simultaneously.
 The system may also determine which conditions are permitted to interrupt
the computer while another interrupt is being serviced.
 Higher-priority interrupt levels are assigned to requests, which, if delayed or
interrupted, could have serious consequences.
 Devices with high-speed transfers such as magnetic disks are given high
priority, and slow devices such as keyboards receive low priority.
 When two devices interrupt the computer at the same time, the computer
services the device, with the higher priority first.
How the priority is determined? a polling procedure is used to identify the
highest-priority source by software means.
 Direct Memory Access (DMA)
The main idea of direct memory access (DMA) is to enable peripheral devices
to cut out the “middle man” role of the CPU in data transfer.
 It allows peripheral devices to transfer data directly from and to memory
without the intervention of the CPU.
 Having peripheral devices access memory directly would allow the CPU to do
other work, which would lead to improved performance, especially in the cases
of large transfers.
The DMA controller is a piece of hardware that controls one or more peripheral
devices.
It allows devices to transfer data to or from the system’s memory without the
help of the processor.
In a typical DMA transfer, some event notifies the DMA controller that data
needs to be transferred to or from memory.
 Both the DMA and CPU use memory bus and only one or the other can use the
memory at the same time.
 The DMA controller then sends a request to the CPU asking its permission to use
the bus.
 The CPU returns an acknowledgment to the DMA controller granting it bus
access.
 The DMA can now take control of the bus to independently conduct memory
transfer.
 When the transfer is complete the DMA relinquishes its control of the bus to the
CPU.
 Processors that support DMA provide one or more input signals that the bus
requester can assert to gain control of the bus and one or more output signals that
the CPU asserts to indicate it has relinquished the bus.
Figure 7. 4 shows how the DMA controller shares the CPU’s memory bus.
Fig DMA controller shares the CPU’s memory bus
 A DMA controller has
I. an address register,
II. a word count register, and
III. a control register.
I. The address register: contains an address that specifies the memory
location of the data to be transferred.
 It is typically possible to have the DMA controller automatically increment
the address register after each word transfer, so that the next transfer will be
from the next memory location.

II. The word count register : holds the number of words to be transferred.
 The word count is decremented by one after each word transfer.

III. The control register: specifies the transfer mode.

 the transfer mode can be performed
• in burst mode or
• single cycle mode.
In burst mode,
 the DMA controller keeps control of the bus until all the data has been
transferred to (from) memory from (to) the peripheral device.
 This mode of transfer is needed for fast devices where data transfer cannot be
stopped until the entire transfer is done.

In single-cycle mode (cycle stealing),

 the DMA controller relinquishes the bus after each transfer of one data word.
 This minimizes the amount of time that the DMA controller keeps the CPU
from controlling the bus, but it requires that the bus request/acknowledge
sequence be performed for every single transfer.
 This overhead can result in a degradation of the performance.
 The single-cycle mode is preferred if the system cannot tolerate more than a
few
Serial Communication
 A data communication' processor is an I/O processor that distributes and
collects data from many remote terminals connected through telephone and other
communication lines.
 It is a specialized I/O processor designed to communicate directly with data
communication networks.
 A communication network may consist of any of a wide variety of devices,
such as printers, interactive display devices, digital sensors, or a remote
computing facility.
 With the use of a data communication processor, the computer can service
fragments of each network demand in an interspersed manner and thus have the
apparent behavior of serving many users at once. In this way the computer is able
to operate efficiently in a time-sharing environment.
All peripherals share the common bus and use it to transfer information to and
from the I/O processor.
A data communication processor communicates with each terminal through a
single pair of wires. Both data and control information are transferred in a serial
fashion with the result that the transfer rate is much slower.
The task of the data communication processor is to transmit and collect digital
information to and from each terminal, determine if the information is data or
control and respond to all requests according to predetermined established
procedures.
The way that remote terminals are connected to a data communication processor
is via telephone lines or other public or private communication facilities.
Since telephone lines were originally designed for voice communication and
computers communicate in terms of digital signals, some form of conversion
must be used.
The converters are called data sets /acoustic couplers, or modems (from
"modulator-demodulator").
A modem converts digital signals into audio tones to be transmitted over telephone lines
and also converts audio tones from the line to digital signals for machine use.
A communication line may be connected to a synchronous or asynchronous interface,
depending on the transmission method of the remote terminal.
• A half-duplex transmission system is one that is capable of transmitting in both
directions but data can be transmitted in only one direction at a time
• A full-duplex transmission can send and receive data in both directions simultaneously.
This can be achieved by means of a four-wire link, with a different pair of wires dedicated
to each direction of transmission.
•The communication lines, modems, and other equipment used in the transmission of
information between two or more stations are called a data link.
•The orderly transfer of information in a data link is accomplished by means of a protocol.
A data link control protocol is a set of rules that are followed by interconnecting
computers and terminals to ensure the orderly transfer of information.
 d !
En