Ch-11

Input Output
Organization
 Table of
contents
01
I/O
Interface
 I/O Bus and Interface Modules
 I/O versus Memory Bus
 Isolated versus Memory-Mapped I/O

02 03
Modes of Direct Memory
Transfer Access
 Example of Programmed I/O  DMA Controller
 Interrupt Initiated I/O
 0
I/O 1
Interface
Introduction
• Definition : The input-output interface facilitates the
transfer of information between internal storage (CPU
and memory) and external I/O devices (peripherals).

• Purpose: To bridge the communication gap between

the CPU and peripherals, addressing differences in
operation and data handling.
 Key Differences Between CPU and
Peripherals
• Signal Conversion: Peripherals are
electromechanical/magnetic; CPUs are electronic, necessitating
signal value conversion.
• Data Transfer Rates: Peripherals typically operate at slower
speeds than the CPU, requiring synchronization mechanisms.
• Data Formats: Peripherals use different data codes and formats
compared to the CPU and memory.
• Operating Modes: Each peripheral has unique operating modes
that must be managed to prevent interference with other
devices.
Interface Units and
Controllers
• Interface Units: Special hardware components that
supervise and synchronize I/O transfers between CPU and
Peripherals.

• Device Controllers: Each peripheral may have its own

controller to manage its specific operations, ensuring
efficient communication and operation without disrupting
the overall system.
 01(
A)and
I/O Bus
Interface
Modules
Introduction to I/O Bus

• The I/O bus serves as a communication link between the

processor and various peripheral devices such as disk
drivers, printers and magnetic tapes.
• It consists of data lines, address lines, and control lines,
enabling the processor to control and access data from
external devices.
• Each peripheral device is equipped with its own interface
unit to facilitate communication with the processor.
 I/O Bus
Connection
 Processor: Send instructions and receives data
through I/O Bus.
 I/O Bus: Central communication channel connecting
the processor to peripherals.
 Data Lines: Carry the actual information exchanged
between the processor and peripherals.
 Address Lines: Select specific peripheral devices for
communication.
 Control Lines: Provide signals for managing data
transfer and operations.
 Interface Units: Each peripheral has an interface
unit that manages communication with the I/O Bus
 Peripheral Examples: Keyboard, display, printer,
magnetic disk and magnetic tape.
 I/O Commands
• Overview
Set of instructions sent from the processor to the interface
units of peripheral devices.

Control Commands: Instruct peripherals to perform specific actions.

Status Commands: Check and report the status of peripheral devices.

Data Output Commands: Transfer data from the processor to peripherals.

Data Input Commands: Transfer data from peripherals to the processor.

Control and Status
Commands
Control Commands Status Commands

 Direct Peripherals to execute  Used to monitor the operational

tasks. status of peripheral devices.

 Used to monitor the  Essential do ensuring devices

operational status of are functioning correctly and for
peripheral devices. troubleshooting issues.
 01(
B)
I/O versus
Memory Bus
I/O BUS
versus MEMORY BUS
 In addition to communicating with I/O, the processor must
communicate with the memory unit. Like the I/O bus, the
memory bus contains data, address, and read/write control
lines. There are three different types by which I/O bus and
memory bus can be connected:

a. Use two separated buses , one for memory and other for I/O.
b. Use one common bus for memory and I/O but have separate
control lines for each (isolated I/O,I/O mapped I/O).
c. Use one common bus for memory end I/O with common
control lines (memory mapped I/O).
 a). Separated
buses

In the first method, two distinct

buses are employed- one
dedicated to memory and other
to I/O operations. This approach
ensures independent
communication pathways,
minimizing conflicts between the
two.
b). Common bus with separate control
lines
The second method involve
using a common bus(data and
address) for both memory and
I/O operations. However,
separate control lines are
designated for each. This
approach better resource
sharing while maintaining
control over distinct functions.
 c). Common bus with shared control
lines

The third method integrates both

Memory and I/O operations into a
common bus and the control lines
are shared between the two. This
Simplifies the overall design by
reducing the number of dedicated
control lines.
 01(
Isolated versus
C)
Memory-Mapped
I/0
 Isolated I/O Memory-Mapped I/O
Memory and I/O have separate address
Both have same address spaces.
space.

Address can be used by both

All address can be used by memory.
memory and I/O.

Separate control lines are used while Same instruction are used to control
reading and writing operations. both I/O and memory.

More efficient due to separate control

Lesser efficient.
bus.

Larger in size due to more buses. Smaller in size.

Complex due to separate logic is used Simpler logic is used as I/O is also
to control both. treated as memory only.
 0
Modes of 2
Transfer
 Mode of
Transfer
The data transfer between the CPU and the I/O device is
through the memory. Data transfer between the CPU
and the I/O may be handled in a variety of modes.
These are:

 Programmed I/O
 Interrupt Initiated I/O
 Direct Memory Access(DMA)
 Types of
1) Non-Vectored: Interrupts
• A fixed memory address is used for the ISR.
• All devices use the same ISR, making the system simpler but less
flexible.

2) Vectored:
• The interrupting device provides an Interrupt Vector containing:
1. Address of the ISR.
2. Or a pointer to a memory location storing the ISR
address.
• Offers better flexibility and faster response for multiple devices.
 02(
A) of
Example
Programmed I/O
 Definition
In the programmed I/O mode all data
transfer activity from the I/O to
memory or vice-versa take place
through the CPU by executing a
number of instruction. Figure shows
the interface through which the I/O
communicates with the CPU.
Following steps of operation take
place for I/O transfer.
 STEPS:-
 When the device is ready and data is available, it places the data
on the I/O bus and enables the data valid line.
 The interface accepts the byte into its data register and enables
the data accepted line.
 The interface sets the status fag to ‘1’ and disables the data valid
line.
 The device disables the data accepted line and is now ready to
make another transfer.
 The CPU reads the status register and check the status of the flag
bit.
 If the flag bit is not set to ‘1’ then it goes to step 5 else the CPU
reads the data register.
 02(B
)
Interrupt Initiated
I/O
What is Interrupt-Initiated I/O?
• Interrupt-Initiated I/O is a concept that enables efficient communication
between the CPU and peripheral devices.

• It is an alternative to the CPU constantly monitoring the flag is to let the

interface inform the computer when it is ready to transfer data.

• This technique plays a crucial role in the overall performance and

responsiveness of a computing system.

Benefits
• By leveraging interrupts, the CPU can focus on other tasks and
only respond when a peripheral device requires its attention.

• This approach helps to optimize the CPU's utilization, leading to

improved overall system performance and responsiveness.
 HOW IT WORKS?
Interrupt Efficient I/O
Interrupt Handling
Notification Processing

•It is an interrupt signal sent by a •It is more efficient than polling, •As an interrupt is received the
peripheral device when it needs in which the CPU constantly CPU suspends its current
the CPU's attention. checks devices for activity. program saving the necessary
It interrupts the CPU's current •It only interrupts the CPU when state information to allow it to
program execution and informs necessary, making it focus on resume the original program
that the device requires service. other tasks hence, improving later.
It contains information about the overall system performance and •The CPU then jumps to a
source of the interrupt, allowing responsiveness. dedicated interrupt service
the CPU to identify which device •It also allows the CPU to serve routine (ISR) in the operating
needs attention. multiple devices by handling system. Once the ISR has
their interrupt requests in the completed processing the
receiving order, rather than interrupt, the CPU restores the
wasting cycles checking each saved state and resumes
device in turn. execution of the original
program
 SOFTWARE
CONSIDERATION
Data Transfer
 Data is transferred item by item until complete.
 Control commands may trigger actions like stopping tape or printing characters.
 Error checking and other safeguards are often incorporated.

Interrupt-Controlled Transfers
 I/O software issues commands to peripherals to interrupt when ready for data transfer.
 This interrupt is then serviced by the software, handling the data transfer.

DMA Transfer
 The I/O software initiates a DMA channel to handle data transfer directly between the
peripheral and memory, freeing up the processor for other tasks.
 0
Direct Memory
3
Access
 • In DMA, the interface transfers data into and out of the memory through
memory bus.
• CPU initiates the transfer by supplying the interface with the starting
address and the number of words needed to be transformed and then
proceeds to execute other tasks.
• When the transfer is made, the DMA requests memory cycles through
the bus.
• When request is
granted by the memory
controller, the DMA
transfers the data
directly into memory.
• The CPU merely delays
its memory access
operation to allow the
direct memory I/O
transfer.
 The ways to place CPU in an idle
state:
●Bus request input is used by the DMA controller to request the CPU to
relinquish control of buses.
●When the input is active, the CPU terminates the execution of the current
instruction and places the address bus, the data bus, and the read and write
lines into a high-impedance state.
●The CPU activates the bus grant output to inform the external DMA that
the bus are in the high-impedance state.
●The DMA takes control of the buses to conduct memory transfer without
process intervention.
●When DMA terminates the transfer, it disables the bus request line.
●The CPU disables the bus grant, takes control of the buses and returns to
its normal operation.
 02(
DMA Controller
A)
 The unit communicates with the CPU via the data bus and
control lines.
 The registers in the DMA are selected by the CPU through the
address bus by enabling the DSC (DMA select) and RS
(Register select) input.
 Read and write inputs and bi-directional.
 When Bus Grant=0, the CPU can communicate with the DMA
register through the data bus to read from or write to the
DMA register.
 When Bus Grant=1, the CPU has relinquished the buses and
the DMA can communicate directly with the memory by
specifying an address in the address bus and activating
read/write control.
 Prepared
By
Kamayani Nitya
Mishra
Roll No.
CSC/24/06
Kapoor
Roll No.
CSC/24/19

Charu Suhani Diti Arora

Roll No.
CSC/24/25
Kamboj
Roll No.
CSC/24/37
Roll No.
CSC/24/49
Thank
You