Basic Concepts of Interfacing Why?

1) I/O devices are most of some signals to read from and write
case usually electrical/ mechanical/ to registers. • The interfacing
Definition of Interface: An electronic devices where processor process includes some key factors to
interface is a medium through is an electronic device. Also the match with the memory
which two separate components of a data transfer rates of I/O are often requirements and microprocessor
computer system exchange slower than the processor and signals. The interfacing circuit
information or interact with each memory. So it is significant that the therefore should be designed in such
other. The exchange can be between speed and electrical characteristics a way that it matches the memory
software, computer hardware, of I/O are different from CPU. 2) signal requirements with the signals
peripheral devices, humans and There are a variety of peripherals of the microprocessor.
combinations of these. The interface that exist and may need to be
in a microprocessor is an integrated connected to the same system bus. IO Interfacing: • There are various
circuit that performs the basic But it may be difficult to communication devices like the
functions of the central processing incorporate all the peripheral device keyboard, mouse, printer, etc. So,
unit. It enables a user to logic into CPU. This reduces we need to interface the keyboard
communicate with a computer. flexibility and creates hindrance in and other devices with the
new developments. 3) Peripheral microprocessor by using latches and
What is the need of interfacing buffers. This type of interfacing is
the microprocessor system? often use different data formats and
word lengths that used by the CPU known as I/O interfacing.
1) If you are not using interfacing, Incorporation of I/O module helps Block Diagram of Memory and
then it will be working with less to overcome these problems. I/O Interfacing: Fig of Tabij 2
options. 2) On interfacing, we can here.
add many features to it like:a. DMA Reasons Lead to Use I/O
which will give mode types of data Module?1) First, An I/O module is Comparison of Memory Mapped
transfer, b. PIC(peripheral interface a mediator between the processor I/O and Peripheral I/O:
controller) which will provide more and an I/O device/devices. 2)
number of interrupt handling Second, It controls the data Characte Memory Peripheral
exchange between the external ristics Mapped I/O
capacity, c. PIT(parallel interface)
devices and main memory; or I/O
for event driven task and many Device 16 bit 8 bit
more. 3) Interfacing also allow it to external devices and CPU registers.
Address
connect to other microprocessor and 3) Third, An I/O module provide an
Control MEMR/ IOR/IOW
make its computation more easy and interface internal to the computer signals MEMW
fast. which connects it to CPU and main Instructi STA,LD IN, OUT
memory and an interface external to ons A,STA
What is the need for peripherals the computer connecting it to X,LDA
interfacing with a external device or peripheral. 4) X,
MOV
microprocessor? Microprocessor Fourth, The I/O module should not
M,R
based system design involves only communicate the information ADDM
interfacing of the processor with from CPU to I/O device, but it etc.
one or more peripheral devices for should also coordinate these two. 5) Data Between Only
the purpose of communication with Fifth, In addition since there are transfer any between
various input and output devices speed differences between CPU and register I/O and
connected to it. I/O devices, the I/O module should and IO the
accumulat
have facilities like buffer (storage
Can we get any output directly or
area) and error detection Maximu 64K is 256 input
from a microprocessor without mechanism. m No. of shared devices
interfacing with peripherals? or I/Os between and 256
Can’t we connect / interface Memory Interfacing: • When we possible I/Os and output
directly the I/O devices to are executing any instruction, we system devices
processor ? No! You can’t get need the microprocessor to access memory
output directly from a the memory for reading instruction Executio 13 T- 10 T-
microprocessor without interfacing codes and the data stored in the n speed states(S states
TA,LD
with peripherals. memory. For this, both the memory
A)
and the microprocessor requires
 7 T- must be controlled so as not to the same clock. When the CPU and
states disturb the operation of each other I/O devices match in speed,
(MOV peripherals connected to CPU. Synchronous Data Transfer
M,R)
technique is employed. • The data
Types of Data Transfer Scheme: transfer with IO devices is
Hardwar More Less Different types of data transfer
e hardwar Hardware performed by executing IN and
techniques are available which can OUT instruction. The IN instruction
Require e is is required
ments needed to decode be broadly divided into two is used to read data from an input
to 8 bit categories: 1) device or input port. The OUT
decode address MICROPROCESSOR instruction is used to sends data
16 bit CONTROLLED: Here data transfer from CPU to the output device or
address. is controlled by microprocessor.
Other Arithme Not output port. As the CPU and the IO
Microprocessor is primarily devices match in speed, the I/O
features tic and Available
logical responsible for data transfer whether device is ready to transfer data when
operatio from I/O to the CPU or to the IN or OUT instruction is executed.
ns can memory or vice versa. 2) The status of the I/O device,
be PERIPHERAL/DEVICE whether it is ready or not, is not
directly CONTROLLED: Here data transfer
perform examined before the data is
is controlled by I/O device. Data is transferred. Asynchronous mode of
ed with
transferred in between I/O device transfer : •Asynchronous means ‘at
I/O data
Interfacing with External and memory without the irregular intervals’. In this method
Memory: • An external memory intervention of CPU such a transfer data transfer is not based on
interface is a bus protocol for increases rate of transfer and makes predetermined timing pattern. This
communication from an integrated the system more efficient. technique of data transfer is used
circuit, such as a microprocessor, to when the speed of an I/O device
Microprocessor Controlled DTS:
an external memory device located does not match the speed of the
Microprocessor based scheme is
on a circuit board. • The memory is microprocessor. • In this technique
further divided into two parts: a.
referred to as external because it is the status of the I/O device i.e.
Programmed Data Transfer Scheme.
not contained within the internal whether the device is ready or not,
b. Interrupt Control Data Transfer
circuitry of the integrated circuit is checked by the microprocessor
Scheme.
and thus is externally located on the before the data are transferred. The
circuit board. • The external a. Programmed Data Transfer microprocessor initiates the I/O
memory interface enables the Scheme: • Programmed data transfer device to get ready and then
processor to interface with third scheme is controlled by the CPU . continuously checks the status of
level caches, peripherals, and Data are transferred from an IO I/O device till the I/O device
external memory. • Some common device to the CPU or to the memory becomes ready to transfer data.
external memory interfaces include: through CPU or vice versa under the When I/O device becomes ready,
a. DDR b. DDR2 c. GDDR. control of programs which are the microprocessor executes
stored in memory. These programs instruction to transfer data. • This
Data Transfer Schemes:
are executed by the CPU when an mode of data transfer is also called
Need for Data Transfer Scheme: I/O device is ready to transfer data. handshaking mode of data transfer
• A wide variety of IO devices • The program data transfer schemes because some signals are exchanged
having wide range of speed and are employed when small amount of between microprocessor and I/O
other different characteristics are data are to be transferred. devices before the actual data
available. • A slow responding IO transfer takes place. Such signals
Figure tabij 2 here. are called handshake signals.
device cannot transfer data when
microprocessor issues instruction -Here also synchronous and Drawback of Programmed Data
for it as it takes some time to get asynchronous mode of transfer is Transfer Scheme: • The
ready. • Transfers rates of used. Synchronous Data microprocessor is too busy. • The
peripherals is usually slower than Transfer : • Synchronous means ‘at CPU is wasting time while checking
the transfer rates of CPU. • the same time’. The device which the flag instead of doing some
Operating modes of peripheral are sends data and the device which useful work.
different from each other and each received data are synchronized with
Interrupt Driven Data Transfer : • of transfer and hence will make the
The problem with programmed I/O system more efficient. This transfer
is that CPU has to wait along time technique is called DMA Data
for the I/O device to be ready for Transfer. • During DMA transfer
reception or transmission of microprocessor is idle, so it has no
data .The CPU while waiting, must longer control on the system buses.
repeatedly interrogate the status of A DMA Controller takes over the
the I/O device . As a result the level buses and manage the transfer
of the performance of the entire directly between the peripheral and
system is severely degraded. • An the memory. • It is fastest scheme
alternative is interrupt driven IO then Programmed Data Transfer
data transfer. Scheme and the microprocessor
regains the control of buses after
Transfer Operation: • In this scheme data transfer.
when the I/O device becomes ready
to transfer data, it sends a high
signal to the microprocessor through
a special input line called an
interrupt line. In other words it
interrupts the normal processing
sequence of the microprocessor. •
On receiving interrupt the
microprocessor completes the
current instruction, saves the
contents of the program counter on
stack first and then attends the I/O
devices. It take up a subroutine
called ISS (Interrupt Service
Subroutine). It execute ISS to
transfer data from or to the I/O
device. Different ISS are to be
provided for different IO devices.
After completing the data transfer
the microprocessor returns back to
the main program which it was
executing before the interrupt
occurred.

Fig. of tabij 2 here.

Drawback of Interrupt Driven Data

Transfer: • The normal operation of
the microprocessor is interrupted. •
It needs to continue monitoring for
interrupt signals.

Device Control Data Transfer : •

The transfer of data between the
mass storage device and a system
memory is often limited by the
speed of microprocessor. Removing
the microprocessor during such a
transfer and letting the peripheral
manage the transfer to or from
memory would improve the speed