L T P C

Course Code: 2161ME102

Course Name: MICROCONTROLLERS AND APPLICATIONS
PREAMBLE: 3 0 0 3
To give sufficient background for 8 &16 bit microcontroller and embedded C for system
design.

1.PRE-REQUISITE:
 Electronic devices and circuits
 Microprocessors

2.LINKS TO OTHER COURSES

 Embedded Control Systems

3.COURSE EDUCATIONAL OBJECTIVES

 To introduce students to the 8051 microcontroller and programming.
 To introduce Embedded C and its programming with 8051 microcontroller.
 To introduce about the 8096 16 bit microcontroller
 To learn about 8 &16 bit microcontroller applications.

4.COURSE OUTCOMES
Students undergoing this course are able to
 Ability to program in assembly language.
 Design and implement interfaces between digital and analog hardware.
 Understand current applications, trends and new directions in microcontrollers.
 Student will be able to apply engineering techniques to real worlds problems by designing solutions
appropriate to the needs.
 Ability to design, build and debug systems using combined hardware and software solutions.

5.COURSE CONTENT
UNIT I 8051 Architecture 9
Introduction to 8085 Architecture-Basic organization – 8051 CPU structure – Register file – Interrupts –
Timers – Port circuits – Instruction set – Timing diagram – Addressing modes – Simple Program and Applications-
Introduction to ARM 32 bit controllers.
UNITII Peripherals and Interfacing 9
Typical Bus structure – Bus – memory organization – Timing characteristics – Extended Model and
Memory Interfacing – Polling – Interfacing Basic I/O devices – Analog and Digital interfacing – PWM mode
operation – Serial port application.
UNIT III 8096 Architecture 9
CPU operation – Interrupt structure – Timers – High Speed Input / Output Ports – I/O control and Status
registers – Instruction Set – Addressing Modes – Simple Programming – Queues – Tables and Strings – Stack
Memories – Key Switch – Parsing.

UNIT IV Peripherals and Interfacing 9

Analog Interface – Serial Ports – Watch dog timers – Real Time Clock – Multitasking – Bus Control –
Memory Timing – External ROM and RAM expansion – PWM control – A/D interfacing.

UNIT V Case Study for 8051 and 8096 9

Real Time clock – DC Motor Speed Control – Generation of Gating Signals for converters and
Inverters -Frequency Measurement -Temperature Control,Basic ARM 32 bit processors, ARM cortex M.

TOTAL : 45periods
 MICROCONTROLLERS

MICROPROCESSORS AND MICROCONTROLLERS

Microprocessor Microcontroller

Arithmetic and logic

ALU Timer/ IO Ports
unit
Counter
Accumulator
Accumulator Interrupt
Registers
Internal Circuits
Working Registers
Internal RAM ROM
Program Counter Stack Pointer Stack Pointer Clock

Clock Circuit Interrupt circuit Program Counter

Block diagram of microprocessor Block diagram of microcontroller

Microprocessor contains ALU, General purpose Microcontroller contains the circuitry of

registers, stack pointer, program counter, clock microprocessor, and in addition it has built in
timing circuit, interrupt circuit ROM, RAM, I/O Devices, Timers/Counters etc.

It has many instructions to move data between It has few instructions to move data between
memory and CPU memory and CPU

Few bit handling instruction It has many bit handling instructions

Less number of pins are multifunctional More number of pins are multifunctional

Single memory map for data and code Separate memory map for data and code
(program) (program)

Access time for memory and IO are more Less access time for built in memory and IO.

Microprocessor based system requires It requires less additional hardwares

additional hardware

More flexible in the design point of view Less flexible since the additional circuits which is
residing inside the microcontroller is fixed for a
particular microcontroller

Large number of instructions with flexible Limited number of instructions with few
addressing modes addressing modes

1
RISC AND CISC CPU ARCHITECTURES
Microcontrollers with small instruction set are called reduced instruction set computer (RISC)
machines and those with complex instruction set are called complex instruction set computer
(CISC). Intel 8051 is an example of CISC machine whereas microchip PIC 18F87X is an example of
RISC machine.

RISC CISC

Instruction takes one or two cycles Instruction takes multiple cycles

Only load/store instructions are used to access In additions to load and store instructions,
memory memory access is possible with other instructions
also.

Instructions executed by hardware Instructions executed by the micro program

Fixed format instruction Variable format instructions

Few addressing modes Many addressing modes

Few instructions Complex instruction set

Most of the have multiple register banks Single register bank

Highly pipelined Less pipelined

Complexity is in the compiler Complexity in the microprogram

2
HARVARD & VON- NEUMANN CPU ARCHITECTURE
Von-Neumann (Princeton architecture) Harvard architecture

Program Data Data

Data
Memory Memory
CPU CPU Address Bus

Data Program
Data
Memory Memory
Address Bus
Address Bus

Von-Neumann (Princeton architecture) Harvard architecture

It uses single memory space for both It has separate program memory and data
instructions and data. memory

It is not possible to fetch instruction code and Instruction code and data can be fetched
data simultaneously

Execution of instruction takes more machine Execution of instruction takes less machine
cycle cycle

Uses CISC architecture Uses RISC architecture

Instruction pre-fetching is a main feature Instruction parallelism is a main feature

Also known as control flow or control driven Also known as data flow or data driven
computers computers

Simplifies the chip design because of single Chip design is complex due to separate memory
memory space space

Eg. 8085, 8086, MC6800 Eg. General purpose microcontrollers, special

DSP chips etc.

3
COMPUTER SOFTWARE
A set of instructions written in a specific sequence for the computer to solve a specific task is called
a program and software is a collection of such programs.

The program stored in the computer memory in the form of binary numbers is called machine
instructions. The machine language program is called object code.

An assembly language is a mnemonic representation of machine language. Machine language and

assembly language are low level languages and are processor specific.

The assembly language program the programmer enters is called source code. The source code
(assembly language) is translated to object code (machine language) using assembler.

Programs can be written in high level languages such as C, C++ etc. High level language will be
converted to machine language using compiler or interpreter. Compiler reads the entire program
and translate into the object code and then it is executed by the processor. Interpreter takes one
statement of the high level language as input and translate it into object code and then executes.

THE 8051 ARCHITECTURE

Introduction

Salient features of 8051 microcontroller are given below.

Eight bit CPU
On chip clock oscillator
4Kbytes of internal program memory (code memory) [ROM]
128 bytes of internal data memory [RAM]
64 Kbytes of external program memory address space.
64 Kbytes of external data memory address space.
32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O
lines)
Two 16 Bit Timer/Counter :T0, T1
Full Duplex serial data receiver/transmitter
Four Register banks with 8 registers in each bank.
Sixteen bit Program counter (PC) and a data pointer (DPTR)
8 Bit Program Status Word (PSW)
8 Bit Stack Pointer
Five vector interrupt structure (RESET not considered as an interrupt.)
8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’ , B register,
PSW, SP, 16 bit program counter, stack pointer.
ALU can perform arithmetic and logic functions on 8 bit variables.
8051 has 128 bytes of internal RAM which is divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]

4
The 8051 architecture.
I/O
A0-A7
ALU PSW Port 0
SFR D0-D7

General
A B Purpose I/O
RAM Port 1

I/O
A8-
Port 2 A15

ROM
I/O INT
DPTR CNTR
PC
DPH Port 3 SERIAL
RD/WR
DPL

IE
E
System General IP
ALE Timing purpose PCON
PSEN area SBUF
System SCON
XTAL1 interrupt
Bit addressible TCON
XTAL2 timers area TMOD
RESET Register Bank 3 TL0
Data
Register Bank 2 TH0
buffers
Register Bank 1 TL1
Register Bank 0
Memory TH1
control SFR and
VCC
General Purpose RAM
GND

8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the
program size is more than 4 K Bytes 8051 will fetch the code automatically from external
memory.
Accumulator is an 8 bit register widely used for all arithmetic and logical operations.
Accumulator is also used to transfer data between external memory. B register is used along
with Accumulator for multiplication and division. A and B registers together is also called
MATH registers.

5
 PSW (Program Status Word). This is an 8 bit register which contains the arithmetic status of
ALU and the bank select bits of register banks.
CY AC F0 RS1 RS0 OV - P
CY - carry flag
AC - auxiliary carry flag
F0 - available to the user for general purpose
RS1,RS0 - register bank select bits
OV - overflow
P - parity
Stack Pointer (SP) – it contains the address of the data item on the top of the stack. Stack
may reside anywhere on the internal RAM. On reset, SP is initialized to 07 so that the default
stack will start from address 08 onwards.
Data Pointer (DPTR) – DPH (Data pointer higher byte), DPL (Data pointer lower byte). This
is a 16 bit register which is used to furnish address information for internal and external
program memory and for external data memory.
Program Counter (PC) – 16 bit PC contains the address of next instruction to be executed.
On reset PC will set to 0000. After fetching every instruction PC will increment by one.

PIN DIAGRAM

Pinout Description
Pins 1-8 PORT 1. Each of these pins can be configured as an input or an output.
Pin 9 RESET. A logic one on this pin disables the microcontroller and clears the contents of
most registers. In other words, the positive voltage on this pin resets the
microcontroller. By applying logic zero to this pin, the program starts execution from
the beginning.
Pins10-17 PORT 3. Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions

6
Pin 10 RXD. Serial asynchronous communication input or Serial synchronous communication
output.
Pin 11 TXD. Serial asynchronous communication output or Serial synchronous
communication clock output.
Pin 12 INT0.External Interrupt 0 input
Pin 13 INT1. External Interrupt 1 input
Pin 14 T0. Counter 0 clock input
Pin 15 T1. Counter 1 clock input
Pin 16 WR. Write to external (additional) RAM
Pin 17 RD. Read from external RAM
Pin 18, 19 XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins.
Pin 20 GND. Ground.
Pin 21-28 Port 2. If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher
address byte, i.e. addresses A8-A15 will appear on this port. Even though memory
with capacity of 64Kb is not used, which means that not all eight port bits are used for
its addressing, the rest of them are not available as inputs/outputs.
Pin 29 PSEN. If external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.
Pin 30 ALE. Prior to reading from external memory, the microcontroller puts the lower address
byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE
pin, the external latch latches the state of P0 and uses it as a memory chip address.
Immediately after that, the ALE pin is returned its previous logic state and P0 is now
used as a Data Bus.
Pin 31 EA. By applying logic zero to this pin, P2 and P3 are used for data and address
transmission with no regard to whether there is internal memory or not. It means that
even there is a program written to the microcontroller, it will not be executed. Instead,
the program written to external ROM will be executed. By applying logic one to the EA
pin, the microcontroller will use both memories, first internal then external (if exists).
Pin 32-39 PORT 0. Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when
the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven
low (0).
Pin 40 VCC. +5V power supply.

10
ADDRESSING MODES
Various methods of accessing the data are called addressing
modes.

8051 addressing modes are classified as

follows.

1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.
1. Immediate
addressing.
In this addressing mode the data is provided as a part of instruction itself. In other
words data immediately follows the instruction.
Eg. MOV
A,#30H
ADD A, #83 # Symbol indicates the data is immediate.

2. Register
addressing.
In this addressing mode the register will hold the data. One of the eight general
registers
(R0 to R7) can be used and specified as the operand.
Eg. MOV A,R0
ADD A,R6
R0 – R7 will be selected from the current selection of register bank. The default register bank will be bank
0.
3. Direct addressing
There are two ways to access the internal memory. Using direct address and indirect address.
Using direct addressing mode we can not only address the internal memory but SFRs also. In direct
addressing, an 8 bit internal data memory address is specified as part of the instruction and hence, it can
specify the address only in the range of 00H to FFH. In this addressing mode, data is obtained directly from
the memory.
Eg. MOV A,60h
ADD A,30h
4. Indirect
addressing
The indirect addressing mode uses a register to hold the actual address that will be used in data
movement. Registers R0 and R1 and DPTR are the only registers that can be used as data pointers. Indirect
addressing cannot be used to refer to SFR registers. Both R0 and R1 can hold 8 bit address and DPTR can
hold
 16 bit address.
Eg. MOV A,@R0
ADD A,@R1
MOVX A,@DPTR
5. Indexed
addressing.
In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—
is used to hold the base address, and the A is used to hold the offset address. Adding the value of
the base address to the value of the offset address forms the effective address. Indexed addressing
is used with JMP or MOVC instructions. Look up tables are easily implemented with the help of
index addressing.
Eg. MOVC A, @A+DPTR // copies the contents of memory location pointed by the sum of
the
accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC // copies the contents of memory location pointed by the sum
of the accumulator A and the program counter into accumulator A.
6. Relative
Addressing.
Relative addressing is used only with conditional jump instructions. The relative
address, (offset), is an 8 bit signed number, which is automatically added to the PC to make
the address of
the next instruction. The 8 bit signed offset value gives an address range of +127 to —128
locations. The jump destination is usually specified using a label and the assembler calculates
the jump offset accordingly. The advantage of relative addressing is that the program code is
easy to relocate and the address is relative to position in the memory.
Eg. SJMP LOOP1
JC BACK
7. Absolute
addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute
Call) instructions. These are 2 bytes instructions. The absolute addressing mode specifies the
lowest 11 bit of the memory address as part of the instruction. The upper 5 bit of the
destination address are the upper 5 bit of the current program counter. Hence, absolute
addressing allows branching only within the current 2 Kbyte page of the program memory.
Eg. AJMP LOOP1
ACALL LOOP2

8. Long Addressing
The long addressing mode is used with the instructions LJMP and LCALL. These are 3 byte
instructions. The address specifies a full 16 bit destination address so that a jump or a call can be
made to a location within a 64 Kbyte code memory space.
Eg. LJMP FINISH
LCALL DELAY

9. Bit Inherent Addressing

In this addressing, the address of the flag which contains the operand, is implied in the opcode
of the instruction.
Eg. CLR C ; Clears the carry flag to 0
10. Bit Direct Addressing
In this addressing mode the direct address of the bit is specified in the instruction. The RAM
space 20H to 2FH and most of the special function registers are bit addressable. Bit address values
are between 00H to 7FH.
Eg. CLR 07h ; Clears the bit 7 of 20h RAM space
SETB 07H ; Sets the bit 7 of 20H RAM space.

INSTRUCTION SET.
1. Instruction Timings
The 8051 internal operations and external read/write operations are controlled by the oscillator
clock.
T-state, Machine cycle and Instruction cycle are terms used in instruction timings.
T-state is defined as one subdivision of the operation performed in one clock period. The terms 'T-
state' and 'clock period' are often used synonymously.
Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six states and each
state lasts for two oscillator periods. An instruction takes one to four machine cycles to execute an
instruction. Instruction cycle is defined as the time required for completing the execution of an
instruction. The 8051 instruction cycle consists of one to four machine cycles.
Eg. If 8051 microcontroller is operated with 12 MHz oscillator, find the execution time for the
following four instructions.
1. ADD A, 45H
2. SUBB A, #55H
3. MOV DPTR, #2000H
4. MUL AB
Since the oscillator frequency is 12 MHz, the clock period is, Clock period = 1/12 MHz = 0.08333 µS.
Time for 1 machine cycle = 0.08333 µS x 12 =1 µS.
Instruction No. of machine cycles Execution time
1. ADD A, 45H 1 1 µs
2. SUBB A, #55H 2 2 µs
3. MOV DPTR, #2000H 2 2 µs
4. MUL AB 4 4 µs

2. 8051 Instructions
The instructions of 8051 can be broadly classified under the following headings.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions

Data transfer instructions.

In this group, the instructions perform data transfer operations of the following types.
a. Move the contents of a register Rn to A
i. MOV A,R2
 ii. MOV A,R7
b. Move the contents of a register A to Rn
i. MOV R4,A
ii. MOV R1,A
c. Move an immediate 8 bit data to register A or to Rn or to a memory location(direct or
indirect)
i. MOV A, #45H iv. MOV @R0, #0E8H
ii. MOV R6, #51H v. MOV DPTR, #0F5A2H
iii. MOV 30H, #44H vi. MOV DPTR, #5467H

d. Move the contents of a memory location to A or A to a memory location using direct and
indirect addressing
i. MOV A, 65H iii. MOV 45H, A
ii. MOV A, @R0 iv. MOV @R1, A

e. Move the contents of a memory location to Rn or Rn to a memory location using direct

addressing
i. MOV R3, 65H
ii. MOV 45H, R2
f. Move the contents of memory location to another memory location using direct and
indirect addressing
i. MOV 47H, 65H
ii. MOV 45H, @R0
g. Move the contents of an external memory to A or A to an external memory
i. MOVX A,@R1 iii. MOVX A,@DPTR
ii. MOVX @R0,A iv. MOVX@DPTR
h. Move the contents of program memory to A
i. MOVC A, @A+PC
ii. MOVC A, @A+DPTR
 FIG. Addressing Using MOV, MOVX and MOVC

i. Push and Pop instructions

[SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)
MOV R6, #25H [R6]=25H //CONTENT OF R6 IS 25H
MOV R1, #12H [R1]=12H //CONTENT OF R1 IS 12H
MOV R4, #0F3H [R4]=F3H //CONTENT OF R4 IS F3H

PUSH 6 [SP]=08 [08]=[06]=25H //CONTENT OF 08 IS 25H

PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H

POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H

POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H
j. Exchange instructions
The content of source ie., register, direct memory or indirect memory will be exchanged
with the contents of destination ie., accumulator.
i. XCH A, R3
ii. XCH A, @R1
iii. XCH A, 54h
k. Exchange digit. Exchange the lower order nibble of Accumulator (A0-A3) with lower
order nibble of the internal RAM location which is indirectly addressed by the register.
i. XCHD A,@R1
ii. XCHD A,@R0
Arithmetic instructions.

The 8051 can perform addition, subtraction. Multiplication and division operations on 8 bit
numbers.

Addition
In this group, we have instructions to
i. Add the contents of A with immediate data with or without carry.
i. ADD A, #45H
ii. ADDC A, #OB4H
ii. Add the contents of A with register Rn with or without carry.
i. ADD A, R5
ii. ADDC A, R2
iii. Add the contents of A with contents of memory with or without carry using direct and
indirect addressing
i. ADD A, 51H
ii. ADDC A, 75H
iii. ADD A, @R1
iv. ADDC A, @R0

CY AC and OV flags will be affected by this operation.

Subtraction
In this group, we have instructions to
i. Subtract the contents of A with immediate data with or without carry.
i. SUBB A, #45H
ii. SUBB A, #OB4H
ii. Subtract the contents of A with register Rn with or without carry.
i. SUBB A, R5
ii. SUBB A, R2
iii. Subtract the contents of A with contents of memory with or without carry using direct and
indirect addressing
i. SUBB A, 51H
ii. SUBB A, 75H
iii. SUBB A, @R1
iv. SUBB A, @R0

CY AC and OV flags will be affected by this operation.

Multiplication

MUL AB. This instruction multiplies two 8 bit unsigned numbers which are stored in A and B register.
After multiplication the lower byte of the result will be stored in accumulator and higher byte of result
will be stored in B register.
Eg. MOV A,#45H ;[A]=45H
MOV B,#0F5H ;[B]=F5H
MUL AB ;[A] x [B] = 45 x F5 = 4209
;[A]=09H, [B]=42H
Division
DIV AB. This instruction divides the 8 bit unsigned number which is stored in A by the 8 bit
unsigned number which is stored in B register. After division the result will be stored in
accumulator and remainder will be stored in B register.
Eg. MOV A,#45H ;[A]=0E8H
MOV B,#0F5H ;[B]=1BH
DIV AB ;[A] / [B] = E8 /1B = 08 H with remainder 10H
;[A] = 08H, [B]=10H

DA A (Decimal Adjust After Addition).

When two BCD numbers are added, the answer is a non-BCD number. To get the result in BCD, we
use DA A instruction after the addition. DA A works as follows.
If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble.
If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble.

Eg 1: MOV A,#23H
MOV R1,#55H
ADD A,R1 // [A]=78
DA A // [A]=78 no changes in the accumulator after da a

Eg 2: MOV A,#53H
MOV R1,#58H
ADD A,R1 // [A]=ABh
DA A // [A]=11, C=1 . ANSWER IS 111. Accumulator data is changed after DA A

Increment: increments the operand by one.

INC A INC Rn INC DIRECT INC @RiINC DPTR

INC increments the value of source by 1. If the initial value of register is FFh, incrementing the value
will cause it to reset to 0. The Carry Flag is not set when the value "rolls over" from 255 to 0.

In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is incremented. If the
initial value of DPTR is FFFFh, incrementing the value will cause it to reset to 0.

Decrement: decrements the operand by one.

DEC A DEC Rn DEC DIRECT DEC @Ri

DEC decrements the value of source by 1. If the initial value of is 0, decrementing the value will cause
it to reset to FFh. The Carry Flag is not set when the value "rolls over" from 0 to FFh.

Logical Instructions

Logical AND

ANL destination, source: ANL does a bitwise "AND" operation between source and destination,
leaving the resulting value in destination. The value in source is not affected. "AND" instruction
logically AND the bits of source and destination.
ANL A,#DATA ANL A, Rn
ANL A,DIRECT ANL A,@Ri
ANL DIRECT,A ANL DIRECT, #DATA

Logical OR

ORL destination, source: ORL does a bitwise "OR" operation between source and destination,
 leaving the resulting value in destination. The value in source is not affected. " OR " instruction
logically OR the bits of source and destination.
ORL A,#DATA ORL A, Rn
ORL A,DIRECT ORL A,@Ri
ORL DIRECT,A ORL DIRECT, #DATA

Logical Ex-OR

XRL destination, source: XRL does a bitwise "EX-OR" operation between source and
destination, leaving the resulting value in destination. The value in source is not affected. " XRL "
instruction logically EX-OR the bits of source and destination.
XRL A,#DATA XRL A,Rn
XRL A,DIRECT XRL A,@Ri
XRL DIRECT,A XRL DIRECT, #DATA

Logical NOT

CPL complements operand, leaving the result in operand. If operand is a single bit then the state of
the bit will be reversed. If operand is the Accumulator then all the bits in the Accumulator will be
reversed.

CPL A, CPL C, CPL bit address

SWAP A – Swap the upper nibble and lower nibble of A.

Rotate Instructions

RR A
This instruction is rotate right the accumulator. Its operation is illustrated below. Each bit is shifted one
location to the right, with bit 0 going to bit 7.

RL A
Rotate left the accumulator. Each bit is shifted one location to the left, with bit 7 going to bit 0

RRC A
Rotate right through the carry. Each bit is shifted one location to the right, with bit 0 going into the carry bit in
the PSW, while the carry was at goes into bit 7

RLC A
Rotate left through the carry. Each bit is shifted one location to the left, with bit 7 going into the carry bit in
the PSW, while the carry goes into bit 0.
Branch (JUMP) Instructions

Jump and Call Program Range

There are 3 types of jump instructions. They are:-
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump

Relative Jump
Jump that replaces the PC (program counter) content with a new address that is greater than (the
address following the jump instruction by 127 or less) or less than (the address following the jump
by 128 or less) is called a relative jump. Schematically, the relative jump can be shown as follows: -

The advantages of the relative jump are as follows:-

1. Only 1 byte of jump address needs to be specified in the 2's complement form, ie. For
jumping ahead, the range is 0 to 127 and for jumping back, the range is -1 to -128.
2. Specifying only one byte reduces the size of the instruction and speeds up program
execution.
3. The program with relative jumps can be relocated without reassembling to generate
absolute jump addresses.

Disadvantages of the absolute jump: -

1. Short jump range (-128 to 127 from the instruction following the jump instruction)

Instructions that use Relative Jump

SJMP <relative address>; this is unconditional jump

The remaining relative jumps are conditional jumps

JC <relative address>
JNC <relative address>
JB bit, <relative address>
JNB bit, <relative address>
JBC bit, <relative address>
CJNE <destination byte>, <source byte>, <relative address>
DJNZ <byte>, <relative address>
JZ <relative address>
JNZ <relative address>

Short Absolute Jump

In this case only 11bits of the absolute jump address are needed. The absolute jump address is
calculated in the following manner.
In 8051, 64 kbyte of program memory space is divided into 32 pages of 2 kbyte each. The
hexadecimal addresses of the pages are given as follows:-

Page (Hex) Address (Hex)

00 0000 - 07FF
01 0800 - 0FFF
02 1000 - 17FF
03 1800 - 1FFF
.
.
1E F000 - F7FF
1F F800 - FFFF

It can be seen that the upper 5bits of the program counter (PC) hold the page number and the lower
11bits of the PC hold the address within that page. Thus, an absolute address is formed by taking
page numbers of the instruction (from the program counter) following the jump and attaching the
specified 11bits to it to form the 16-bit address.

Advantage: The instruction length becomes 2 bytes.

Example of short absolute jump: -

ACALL <address 11>
AJMP <address 11>

Long Absolute Jump/Call

Applications that need to access the entire program memory from 0000H to FFFFH use long
absolute jump. Since the absolute address has to be specified in the op-code, the instruction length
is 3 bytes (except for JMP @ A+DPTR). This jump is not re-locatable.

Example: -

LCALL <address 16>

LJMP <address 16>
JMP @A+DPTR

Another classification of jump instructions is

1. Unconditional Jump
2. Conditional Jump

1. The unconditional jump is a jump in which control is transferred unconditionally to the target location.
a. LJMP (long jump). This is a 3-byte instruction. First byte is the op-code and second and third
bytes represent the 16-bit target address which is any memory location from 0000 to FFFFH
eg: LJMP 3000H
b. AJMP: this causes unconditional branch to the indicated address, by loading the 11 bit address to
0 -10 bits of the program counter. The destination must be therefore within the same 2K blocks.
c. SJMP (short jump). This is a 2-byte instruction. First byte is the op-code and second byte is the
relative target address, 00 to FFH (forward +127 and backward -128 bytes from the current PC
value). To calculate the target address of a short jump, the second byte is added to the PC value
which is address of the instruction immediately below the jump.
2. Conditional Jump instructions.
JBC Jump if bit ＝ 1 and clear bit
JNB Jump if bit ＝ 0
JB Jump if bit ＝ 1
JNC Jump if CY ＝ 0
JC Jump if CY ＝ 1
CJNE reg,#data Jump if byte ≠ #data
CJNE A,byte Jump if A ≠ byte
DJNZ Decrement and Jump if A ≠ 0
JNZ Jump if A ≠ 0
JZ Jump if A ＝ 0

All conditional jumps are short jumps.

Bit level jump instructions:

Bit level JUMP instructions will check the conditions of the bit and if condition is true, it jumps to the
address specified in the instruction. All the bit jumps are relative jumps.

JB bit, rel ; jump if the direct bit is set to the relative address specified.
JNB bit, rel ; jump if the direct bit is clear to the relative address specified.
JBC bit, rel ; jump if the direct bit is set to the relative address specified and then clear the bit.

Subroutine CALL And RETURN Instructions

Subroutines are handled by CALL and RET instructions

There are two types of CALL instructions

1. LCALL address(16 bit)

This is long call instruction which unconditionally calls the subroutine located at the indicated 16 bit
address. This is a 3 byte instruction. The LCALL instruction works as follows.
a. During execution of LCALL, [PC] = [PC]+3; (if address where LCALL resides is say, 0x3254;
during execution of this instruction [PC] = 3254h + 3h = 3257h
b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and [SP]=08
c. [[SP]] = [PC7-0]; (lower byte of PC content ie., 57 will be stored in memory location 08.
d. [SP]=[SP]+1; (SP increments again and [SP]=09)
e. [[SP]] = [PC15-8]; (higher byte of PC content ie., 32 will be stored in memory location 09.

With these the address (0x3254) which was in PC is stored in stack.

f. [PC]= address (16 bit); the new address of subroutine is loaded to PC. No flags are affected.

2. ACALL address(11 bit)

This is absolute call instruction which unconditionally calls the subroutine located at the indicated 11
bit address. This is a 2 byte instruction. The SCALL instruction works as follows.
a. During execution of SCALL, [PC] = [PC]+2; (if address where LCALL resides is say, 0x8549;
during execution of this instruction [PC] = 8549h + 2h = 854Bh
b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and [SP]=08
c. [[SP]] = [PC7-0]; (lower byte of PC content ie., 4B will be stored in memory location 08.
d. [SP]=[SP]+1; (SP increments again and [SP]=09)
e. [[SP]] = [PC15-8]; (higher byte of PC content ie., 85 will be stored in memory location 09.

With these the address (0x854B) which was in PC is stored in stack.

 f. [PC10-0]= address (11 bit); the new address of subroutine is loaded to PC. No flags are
affected.

RET instruction
RET instruction pops top two contents from the stack and load it to PC.
g. [PC15-8] = [[SP]] ;content of current top of the stack will be moved to higher byte of PC.
h. [SP]=[SP]-1; (SP decrements)
i. [PC7-0] = [[SP]] ;content of bottom of the stack will be moved to lower byte of PC.
j. [SP]=[SP]-1; (SP decrements again)

Bit manipulation instructions.

8051 has 128 bit addressable memory. Bit addressable SFRs and bit addressable PORT pins. It is possible to
perform following bit wise operations for these bit addressable locations.

1. LOGICAL AND
a. ANL C,BIT(BIT ADDRESS) ; ‘LOGICALLY AND’ CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
b. ANL C, /BIT; ; ‘LOGICALLY AND’ CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY

2. LOGICAL OR
a. ORL C,BIT(BIT ADDRESS) ; ‘LOGICALLY OR’ CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
b. ORL C, /BIT; ; ‘LOGICALLY OR’ CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
3. CLR bit
a. CLR bit ; CONTENT OF BIT ADDRESS SPECIFIED WILL BE CLEARED.
b. CLR C ; CONTENT OF CARRY WILL BE CLEARED.
4. CPL bit
a. CPL bit ; CONTENT OF BIT ADDRESS SPECIFIED WILL BE COMPLEMENTED.
b. CPL C ; CONTENT OF CARRY WILL BE COMPLEMENTED.

BASICS OF INTERRUPTS.
During program execution if peripheral devices needs service from microcontroller, device will
generate interrupt and gets the service from microcontroller. When peripheral device activate the
interrupt signal, the processor branches to a program called interrupt service routine. After executing
the interrupt service routine the processor returns to the main program.

Steps taken by processor while processing an interrupt:

1. It completes the execution of the current instruction.

2. PSW is pushed to stack.
3. PC content is pushed to stack.
4. Interrupt flag is reset.
5. PC is loaded with ISR address.

ISR will always ends with RETI instruction. The execution of RETI instruction results in the following.

1. POP the current stack top to the PC.

2. POP the current stack top to PSW.
Classification of interrupts.

1. External and internal interrupts.

External interrupts are those initiated by peripheral devices through the external pins of
the microcontroller.
Internal interrupts are those activated by the internal peripherals of the microcontroller
like timers, serial controller etc.)
2. Maskable and non-maskable interrupts.
The category of interrupts which can be disabled by the processor using program is called
maskable interrupts.
Non-maskable interrupts are those category by which the programmer cannot disable it
using program.
3. Vectored and non-vectored interrupt.
Starting address of the ISR is called interrupt vector. In vectored interrupts the starting
address is predefined. In non-vectored interrputs, the starting address is provided by the
peripheral as follows.
Microcontroller receives an interrupt request from external device.
Controller sends an acknowledgement (INTA) after completing the execution of
current instruction.
The peripheral device sends the interrupt vector to the microcontroller.
8051 INTERRUPT STRUCTURE.
8051 has five interrupts. They are maskable and vectored interrupts. Out of these five, two are
external interrupt and three are internal interrupts.

Interrupt source Type Vector address Priority

External interrupt 0 External 0003 Highest
Timer 0 interrupt Internal 000B
External interrupt 1 External 0013
Timer 1 interrupt Internal 001B
Serial interrupt Internal 0023 Lowest

8051 makes use of two registers to deal with interrupts.

1. IE Register
This is an 8 bit register used for enabling or disabling the interrupts. The structure of IE
register is shown below.

2. IP Register.
This is an 8 bit register used for setting the priority of the interrupts.
TIMERS AND COUNTERS
Timers/Counters are used generally for
Time reference
Creating delay
Wave form properties measurement
Periodic interrupt generation
Waveform generation
8051 has two timers, Timer 0 and Timer 1.

Timer in 8051 is used as timer, counter and baud rate generator. Timer always counts up irrespective
of whether it is used as timer, counter, or baud rate generator: Timer is always incremented by the
microcontroller. The time taken to count one digit up is based on master clock
frequency.
If Master CLK=12 MHz,
Timer Clock frequency = Master CLK/12 = 1 MHz
Timer Clock Period = 1micro second
This indicates that one increment in count will take 1 micro second.
The two timers in 8051 share two SFRs (TMOD and TCON) which control the timers, and each timer
also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1).

The following are timer related SFRs in 8051.

SFR Name Description SFR Address
TH0 Timer 0 High Byte 8Ch
TL0 Timer 0 Low Byte 8Ah
TH1 Timer 1 High Byte 8Dh
TL1 Timer 1 Low Byte 8Bh
TCON Timer Control 88h
TMOD Timer Mode 89h
TMOD Register

TCON Register
Timer/ Counter Control Logic.

TIMER MODES

Timers can operate in four different modes. They are as follows

Timer Mode-0: In this mode, the timer is used as a 13-bit UP counter as follows.

Fig. Operation of Timer on Mode-0

The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.Upper 3 bits of TLX are ignored.
When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is generated. The
input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the counter
continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the counter is
controlled by input. This mode is useful to measure the width of a given pulse fed to input.

Timer Mode-1: This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit
mode.

Fig: Operation of Timer in Mode 1

Timer Mode-2: (Auto-Reload Mode): This is a 8 bit counter/timer operation. Counting is

performed in TLX while THX stores a constant value. In this mode when the timer overflows i.e. TLX
becomes FFH, it is fed with the value stored in THX. For example if we load THX with 50H then the
timer in mode 2 will count from 50H to FFH. After that 50H is again reloaded. This mode is useful in
applications like fixed time sampling.

Fig: Operation of Timer in Mode 2

Timer Mode-3: Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0.
Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.

Fig: Operation of Timer in Mode 3

Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0
are available to Timer-0 lower 8 bits(TL0)
PROGRAMS.

1. Write a program to add the values of locations 50H and 51H and store the result in locations
in 52h and 53H.

ORG 0000H ; Set program counter 0000H

MOV A,50H ; Load the contents of Memory location 50H into A ADD ADD A,51H
; Add the contents of memory 51H with CONTENTS A
MOV 52H,A ; Save the LS byte of the result in 52H
MOV A, #00 ; Load 00H into A
ADDC A, #00 ; Add the immediate data and carry to A
MOV 53H,A ; Save the MS byte of the result in location 53h
END

2. Write a program to store data FFH into RAM memory locations 50H to 58H using direct
addressing mode

ORG 0000H ; Set program counter 0000H

MOV A, #0FFH ; Load FFH into A
MOV 50H, A ; Store contents of A in location 50H
MOV 51H, A ; Store contents of A in location 5IH
MOV 52H, A ; Store contents of A in location 52H
MOV 53H, A ; Store contents of A in location 53H
MOV 54H, A ; Store contents of A in location 54H
MOV 55H, A ; Store contents of A in location 55H
MOV 56H, A ; Store contents of A in location 56H
MOV 57H, A ; Store contents of A in location 57H
MOV 58H, A ; Store contents of A in location 58H
END

3. Write a program to subtract a 16 bit number stored at locations 51H-52H from 55H-56H and
store the result in locations 40H and 41H. Assume that the least significant byte of data or the
result is stored in low address. If the result is positive, then store 00H, else store 01H in 42H.
ORG 0000H ; Set program counter 0000H
MOV A, 55H ; Load the contents of memory location 55 into A
CLR C ; Clear the borrow flag
SUBB A,51H ; Sub the contents of memory 51H from contents of A
MOV 40H, A ; Save the LSByte of the result in location 40H
MOV A, 56H ; Load the contents of memory location 56H into A
SUBB A, 52H ; Subtract the content of memory 52H from the content A
MOV 41H, ; Save the MSbyte of the result in location 415.
MOV A, #00 ; Load 005 into A
ADDC A, #00 ; Add the immediate data and the carry flag to A
MOV 42H, A ; If result is positive, store00H, else store 0lH in 42H
END
4. Write a program to add two 16 bit numbers stored at locations 51H -52H and 55H-56H and
store the result in locations 40H, 41H and 42H. Assume that the least significant byte of
data and the result is stored in low address and the most significant byte of data or the result
is stored in high address.

ORG 0000H ; Set p rogram counter 0000H

MOV A,51H ; Load the contents of memory location 51H into A
ADD A,55H ; Add the contents of 55H with contents of A
MOV 40H,A ; Save the LS byte of the result in location 40H
MOV A,52H ; Load the contents of 52H into A
ADDC A,56H ; Add the contents of 56H and CY flag with A
MOV 41H,A ; Save the second byte of the result in 41H
MOV A,#00 ; Load 00H into A
ADDC A, #00 ; Ad d t h e i m m e d i a t e d a t a 0 0 H a n d C Y to A
MOV 42H,A ; Save the MS byte of the result in location 42H
END

5. Write a program to store data FFH into RAM memory locations 50H to 58H using indirect
addressing mode.
ORG 0000H ; Set program counter 0000H
MOV A, #0FFH ; Load FFH into A
MOV RO, #50H ; Load pointer, R0-50H
MOV R5, #08H ; Load counter, R5-08H
Start:MOV @ R O , A ; Copy contents of A to RAM pointed by R0
INC RO ; Increment pointer
DJNZ R5, start ; Repeat until R5 is zero
END
6. Write a program to add two Binary Coded Decimal (BCD) numbers stored at locations 60H
and 61H and store the result in BCD at memory locations 52H and 53H. Assume that the
least significant byte of the result is stored in low address.

ORG 0000H ; Set program counter 00004

MOV A,60H ; Load the contents of memory location 6.0.H into A
ADD A,61H ; Add the contents of memory location 61H with contents of A
DA A ; Decimal adjustment of the sum in A
MOV 52H, A ; Save the least significant byte of the result in location 52H
MOV A,#00 ; Load 00H into .A
ADDC A,#00H ; Add the immediate data and the contents of carry flag to A
MOV 53H,A ; Save the most significant byte of the result in location 53:,
END

7. Write a program to clear 10 RAM locations starting at RAM address 1000H.

ORG 0000H ;Set program counter 0000H

MOV DPTR, #1000H ;Copy address 1000H to DPTR
CLR A ;Clear A
MOV R6, #0AH ;Load 0AH to R6
again: MOVX @DPTR,A ;Clear RAM location pointed by DPTR
 INC DPTR ;Increment DPTR
DJNZ R6, again ;Loop until counter R6=0
END
8. Write a program to compute 1 + 2 + 3 + N (say N=15) and save the sum at70H
ORG 0000H ; Set program counter 0000H
N EQU 15
MOV R0, #00 ; Clear R0
CLR A ; Clear A
agai n: INC R0 ; Increment R0
ADD A, R0 ; Add the contents of R0 with A
CJNE R0,# N,aga in ; Lo o p u ntil c ou nter, R0, N
MOV 70H,A ; Sav e th e r esult i n loca ti on 70 H END
9. Write a program to multiply two 8 bit numbers stored at locations 70H and 71H and store the
result at memory locations 52H and 53H. Assume that the least significant byte of the result is
stored in low address.
ORG 0000H ; Set program counter 00 OH
MOV A, 70H ; Load the contents of memory location 70h into A
MOV B, 71H ; Load the contents of memory location 71H into B
MUL AB ; Perform multiplication
MOV 52H,A ; Save the least significant byte of the result in location 52H MOV 53H,B ; Save the most
significant byte of the result in location 53
END
10. Ten 8 bit nu mbers are s tored in internal data m emory from location 5o H. Write a
program to increment the data.
A s s u m e t h a t t e n 8 b i t n u m b e r s a r e s t o r e d i n i n t e r n a l d a t a m e m o r y from location 50H, hence
R0 or R1 must be used as a pointer.
The program is as follows.
OPT 0000H
MOV R0,#50H
MOV R3,#0AH
Loopl: INC @R0
INC RO
DJNZ R3, loopl END
END
11. Write a program to find the average of five 8 bit numbers. Store the result in H.
(Assume that after adding five 8 bit numbers, the result is 8 bit only).
ORG 0000H
MOV 40H,#05H
MOV 41H,#55H
MOV 42H,#06H
MOV 43H,#1AH
MOV 44H,#09H
MOV R0,#40H
MOV R5,#05H
MOV B,R5
CLR A
Loop: ADD A,@RO
INC RO
 DJNZ R5,Loop
DIV AB
MOV 55H,A END
12. Write a program to find the cube of an 8 bit number program is as follows
ORG 0000H
MOV R1,#N
MOV A,R1
MOV B,R1
MUL AB //SQUARE IS COMPUTED
MOV R2, B
MOV B, R1
MUL AB
MOV 50,A
MOV 51,B
MOV A,R2
MOV B, R1
MUL AB
ADD A, 51H
MOV 51H, A
MOV 52H, B
MOV A, # 00H
ADDC A, 52H
MOV 52H, A //CUBE IS STORED IN 52H,51H,50H
END

13. Write a program to exchange the lower nibble of data present in external memory 6000H and
6001H
OR G 0000H ; Set program counter 00h
MOV DPTR, #6000H ; Copy address 6000H to DP TR
M O V X A , @D P T R ; Copy contents of 60008 to A
M O V R 0 , #4 5 H ; Load pointer, R0=45H
M O V @R O , A ; Copy co nt of A to RAM poi nted by 80
INC D PL ; Increment pointer
M O V X A , @D P T R ; Copy contents of 60018 to A
XC H D A , @R 0 ; Exchange l ower nibbl e of A wit h RAM point ed by RO

M OVX @DPTR, A ; Copy contents of A to 60018

DEC DPL ; Decrement pointer
M O V A , @R0 ; Copy cont of RAM pointed by R0 to A
MOVX @DPTR, A ; Copy cont of A to RAM pointed by DPTR
END

14. Write a program to count the number of and o's of 8 bit data stored in location 6000H.
ORG 00008 ; Set program counter 00008
MOV DPTR, #6000h ; Copy address 6000H to DPTR
M O V X A , @D P T R ; Copy number to A
M O V R 0 , #0 8 ; Copy 08 in RO
M O V R 2 , #0 0 ; C o py 00 in R2
M O V R 3 , #0 0 ; C o py 00 in R3
CLR C ; Clear carry flag
BA CK: RLC A ; Rotate A through carry flag
 JC N E XT ; If CF = 1, branch to next
I N C R2 ; I f C F = 0 , i n c r e m e n t R 2 AJMP NEXT2
N E XT : I N C R 3 ; If CF = 1, increment R3
N E XT 2 : D JN Z R O , B A C K ; Repeat until RO is zero
END

15. Write a program to shift a 24 bit number stored at 57H-55H to the left logically four places.
Assume that the least significant byte of data is stored in lower address.
ORG 0000H ; Set program counter 0000h
MOV R1,#04 ; Set up loop count to 4
again: MOV A,55H ; Place the least significant byte of data in A
CLR C ; Clear tne carry flag
RLC A ; Rotate contents of A (55h) left through carry
MOV
55H,A
MOV
A,56H
RLC A ; Rotate contents of A (56H) left through carry
MOV
56H,A
MOV
A,57H
RLC A ; Rotate contents of A (57H) left through carry
MOV 57H,A
DJNZ R1,again ; Repeat until R1 is zero
END
Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

Module 1 learning unit 1

• A Computer is a programmable machine.

• The two principal characteristics of a computer are:
• It responds to a specific set of instructions in a well-defined manner.
• It can execute a prerecorded list of instructions (a program ).
• Modern computers are electronic and digital.
• The actual machinery wires, transistors, and circuits is called hardware. the
instructions and data are called software.
•

• All general-purpose computers require the following hardware components:

• Memory: Enables a computer to store, at least temporarily, data and programs.
• Mass storage device: Allows a computer to permanently retain large amounts of
data. Common mass storage devices include disk drives and tape drives.
• Input device: Usually a keyboard and mouse are the input device through which
data and instructions enter a computer.
• Output device: A display screen, printer, or other device that lets you see what
the computer has accomplished.
• Central processing unit (CPU): The heart of the computer, this is the component
that actually executes instructions.
• In addition to these components, many others make it possible for the basic
components to work together efficiently.
• For example, every computer requires a bus that transmits data from one part of
the computer to another.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/1

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

• Computers can be generally classified by size and power as follows, though there
is considerable overlap:
• Personal computer: A small, single-user computer based on a microprocessor.
• In addition to the microprocessor, a personal computer has a keyboard for
entering data, a monitor for displaying information, and a storage device for
saving data.
• Working station: A powerful, single-user computer. A workstation is like a
personal computer, but it has a more powerful microprocessor and a higher-
quality monitor.
• Minicomputer: A multi-user computer capable of supporting from 10 to
hundreds of users simultaneously.
• Mainframe: A powerful multi-user computer capable of supporting many
hundreds or thousands of users simultaneously.
• Supercomputer: An extremely fast computer that can perform hundreds of
millions of instructions per second.
Minicomputer:
• A midsized computer. In size and power, minicomputers lie between workstations
and mainframes.
• A minicomputer, a term no longer much used, is a computer of a size intermediate
between a microcomputer and a mainframe.
• Typically, minicomputers have been stand-alone computers (computer systems
with attached terminals and other devices) sold to small and mid-size businesses
for general business applications and to large enterprises for department-level
operations.
• In recent years, the minicomputer has evolved into the "mid-range server" and is
part of a network. IBM's AS/400e is a good example.
• The AS/400 - formally renamed the "IBM iSeries," but still commonly known as
AS/400 - is a midrange server designed for small businesses and departments in
large enterprises and now redesigned so that it will work well in distributed
networks with Web applications.
• The AS/400 uses the PowerPC microprocessor with its reduced instruction set
computer technology. Its operating system is called the OS/400.
• With multi-terabytes of disk storage and a Java virtual memory closely tied into
the operating system, IBM hopes to make the AS/400 a kind of versatile all-
purpose server that can replace PC servers and Web servers in the world's
businesses, competing with both Wintel and Unix servers, while giving its present
enormous customer base an immediate leap into the Internet.
Workstation:
1) A type of computer used for engineering applications (CAD/CAM), desktop
publishing, software development, and other types of applications that require a
moderate amount of computing power and relatively high quality graphics
capabilities.
• Workstations generally come with a large, high- resolution graphics screen, at
least 64 MB (mega bytes) of RAM, built-in network support, and a graphical user
interface.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/2

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

• Most workstations also have a mass storage device such as a disk drive, but a
special type of workstation, called a diskless workstation, comes without a disk
drive.
• The most common operating systems for workstations are UNIX and Windows
NT.
• In terms of computing power, workstations lie between personal computers and
minicomputers, although the line is fuzzy on both ends.
• High-end personal computers are equivalent to low-end workstations. And high-
end workstations are equivalent to minicomputers.
• Like personal computers, most workstations are single-user computers. However,
workstations are typically linked together to form a local-area network, although
they can also be used as stand-alone systems.
2) In networking, workstation refers to any computer connected to a local-area
network. It could be a workstation or a personal computer.
• Mainframe: A very large and expensive computer capable of supporting
hundreds, or even thousands, of users simultaneously. In the hierarchy that starts
with a simple microprocessors (in watches, for example) at the bottom and moves
to supercomputer at the top, mainframes are just below supercomputers.
• In some ways, mainframes are more powerful than supercomputers because they
support more simultaneous programs.
• But supercomputers can execute a single program faster than a mainframe. The
distinction between small mainframes and minicomputers is vague, depending
really on how the manufacturer wants to market its machines.
• Microcomputer: The term microcomputer is generally synonymous with
personal computer, or a computer that depends on a microprocessor.
• Microcomputers are designed to be used by individuals, whether in the form of
PCs, workstations or notebook computers.
• A microcomputer contains a CPU on a microchip (the microprocessor), a memory
system (typically ROM and RAM), a bus system and I/O ports, typically housed
in a motherboard.
• Microprocessor: A silicon chip that contains a CPU. In the world of personal
computers, the terms microprocessor and CPU are used interchangeably.
• A microprocessor (sometimes abbreviated µP) is a digital electronic component
with miniaturized transistors on a single semiconductor integrated circuit (IC).
• One or more microprocessors typically serve as a central processing unit (CPU) in
a computer system or handheld device.
• Microprocessors made possible the advent of the microcomputer.
• At the heart of all personal computers and most working stations sits a
microprocessor.
• Microprocessors also control the logic of almost all digital devices, from clock
radios to fuel-injection systems for automobiles.
• Three basic characteristics differentiate microprocessors:
• Instruction set: The set of instructions that the microprocessor can execute.
• Bandwidth: The number of bits processed in a single instruction.
• Clock speed: Given in megahertz (MHz), the clock speed determines how many
instructions per second the processor can execute.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/3

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

• In both cases, the higher the value, the more powerful the CPU. For example, a 32
bit microprocessor that runs at 50MHz is more powerful than a 16-bit
microprocessor that runs at 25MHz.
• In addition to bandwidth and clock speed, microprocessors are classified as being
either RISC (reduced instruction set computer) or CISC (complex instruction set
computer).
• Supercomputer: A supercomputer is a computer that performs at or near the
currently highest operational rate for computers.
• A supercomputer is typically used for scientific and engineering applications that
must handle very large databases or do a great amount of computation (or both).
• At any given time, there are usually a few well-publicized supercomputers that
operate at the very latest and always incredible speeds.
• The term is also sometimes applied to far slower (but still impressively fast)
computers.
• Most supercomputers are really multiple computers that perform parallel
processing.
• In general, there are two parallel processing approaches: symmetric
multiprocessing (SMP) and massively parallel processing (MPP).
• Microcontroller: A highly integrated chip that contains all the components
comprising a controller.
• Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers.
• Unlike a general-purpose computer, which also includes all of these components,
a microcontroller is designed for a very specific task - to control a particular
system.
• A microcontroller differs from a microprocessor, which is a general-purpose chip
that is used to create a multi-function computer or device and requires multiple
chips to handle various tasks.
• A microcontroller is meant to be more self-contained and independent, and
functions as a tiny, dedicated computer.
• The great advantage of microcontrollers, as opposed to using larger
microprocessors, is that the parts-count and design costs of the item being
controlled can be kept to a minimum.
• They are typically designed using CMOS (complementary metal oxide
semiconductor) technology, an efficient fabrication technique that uses less power
and is more immune to power spikes than other techniques.
• Microcontrollers are sometimes called embedded microcontrollers, which just
means that they are part of an embedded system that is, one part of a larger device
or system.
• Controller: A device that controls the transfer of data from a computer to a
peripheral device and vice versa.
• For example, disk drives, display screens, keyboards and printers all require
controllers.
• In personal computers, the controllers are often single chips.
• When you purchase a computer, it comes with all the necessary controllers for
standard components, such as the display screen, keyboard, and disk drives.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

• If you attach additional devices, however, you may need to insert new controllers
that come on expansion boards.
• Controllers must be designed to communicate with the computer's expansion bus.
• There are three standard bus architectures for PCs - the AT bus, PCI (Peripheral
Component Interconnect ) and SCSI.
• When you purchase a controller, therefore, you must ensure that it conforms to
the bus architecture that your computer uses.
• Short for Peripheral Component Interconnect, a local bus standard developed by
Intel Corporation.
• Most modern PCs include a PCI bus in addition to a more general IAS expansion
bus.
• PCI is also used on newer versions of the Macintosh computer.
• PCI is a 64-bit bus, though it is usually implemented as a 32 bit bus. It can run at
clock speeds of 33 or 66 MHz.
• At 32 bits and 33 MHz, it yields a throughput rate of 133 MBps.
• Short for small computer system interface, a parallel interface standard used by
Apple Macintosh computers, PCs, and many UNIX systems for attaching
peripheral devices to computers.
• Nearly all Apple Macintosh computers, excluding only the earliest Macs and the
recent iMac, come with a SCSI port for attaching devices such as disk drives and
printers.
• SCSI interfaces provide for faster data transmission rates (up to 80 megabytes per
second) than standard serial and parallel ports. In addition, you can attach many
devices to a single SCSI port, so that SCSI is really an I/O bus rather than simply
an interface
• Although SCSI is an ANSI standard, there are many variations of it, so two SCSI
interfaces may be incompatible.
• For example, SCSI supports several types of connectors.
• While SCSI has been the standard interface for Macintoshes, the iMac comes with
IDE, a less expensive interface, in which the controller is integrated into the disk
or CD-ROM drive.
• The following varieties of SCSI are currently implemented:
• SCSI-1: Uses an 8-bit bus, and supports data rates of 4 MBps.
• SCSI-2: Same as SCSI-1, but uses a 50-pin connector instead of a 25-pin
connector, and supports multiple devices. This is what most people mean when
they refer to plain SCSI.
• Wide SCSI: Uses a wider cable (168 cable lines to 68 pins) to support 16-bit
transfers.
• Fast SCSI: Uses an 8-bit bus, but doubles the clock rate to support data rates of 10
MBps.
• Fast Wide SCSI: Uses a 16-bit bus and supports data rates of 20 MBps.
• Ultra SCSI: Uses an 8-bit bus, and supports data rates of 20 MBps.
• Wide Ultra2 SCSI: Uses a 16-bit bus and supports data rates of 80 MBps.
• SCSI-3: Uses a 16-bit bus and supports data rates of 40 MBps. Also called Ultra
Wide SCSI.
• Ultra2 SCSI: Uses an 8-bit bus and supports data rates of 40 MBps.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

• Embedded system: A specialized computer system that is part of a larger system

or machine.
• Typically, an embedded system is housed on a single microprocessor board with
the programs stored in ROM.
• Virtually all appliances that have a digital Interface- watches, microwaves, VCRs,
cars -utilize embedded systems.
• Some embedded systems include an operating system, but many are so
specialized that the entire logic can be implemented as a single program.
MICRO CONTROLLER MICRO PROCESSER
• It is a single chip • It is a CPU
• Consists Memory, • Memory, I/O Ports to be
I/o ports connected externally

CP
CPU MEMORY
MEMORY
I/O PORTS
I/O PORTS
Definitions:
• A Digital Signal Processor is a special-purpose CPU (Central Processing Unit)
that provides ultra-fast instruction sequences, such as shift and add, and multiply
and add, which are commonly used in math-intensive signal processing
applications.
• A digital signal processor (DSP) is a specialized microprocessor designed
specifically for digital signal processing, generally in real time.
Digital
– operating by the use of discrete signals to represent data in the form of
numbers.
Signal
– a variable parameter by which information is conveyed through an
electronic circuit.
Processing
– to perform operations on data according to programmed instructions.
Digital Signal processing
– changing or analysing information which is measured as discrete
sequences of numbers.
• Digital signal processing (DSP) is the study of signals in a digital representation
and the processing methods of these signals.
• DSP and analog signal processing are subfields of signal processing.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

DSP has three major subfields:

• Audio signal processing, Digital image processing and Speech processing.
• Since the goal of DSP is usually to measure or filter continuous real-world analog
signals, the first step is usually to convert the signal from an analog to a digital
form, by using an analog to digital converter.
• Often, the required output signal is another analog output signal, which requires a
digital to analog converter.
Characteristics of Digital Signal Processors:
• Separate program and data memories (Harvard architecture).
• Special Instructions for SIMD (Single Instruction, Multiple Data) operations.
• Only parallel processing, no multitasking.
• The ability to act as a direct memory access device if in a host environment.
• Takes digital data from ADC (Analog-Digital Converter) and passes out data
which is finally output by converting into analog by DAC (Digital-Analog
Converter).
• analog input-->ADC-->DSP-->DAC--> analog output.
Analog front end Analog back end
Analog Antialiasing DSP D/A converter, Analog
signal in filter, S/H, A/D Processor reconstruction signal
converter filter output

DAP System
Multiply-accumulate hardware:
• Multiply accumulate is the most frequently used operation in digital signal
processing.
• In order to implement this efficiently, the DSP has an hardware multiplier, an
accumulator with an adequate number of bits to hold the sum of products and at
explicit multiply-accumulate instructions.
• Harvard architecture: in this memory architecture, there are two memory spaces.
Program memory and data memory.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

X Y
n n

Multiplier

Product register

2n

ADD / SUB

Accumulator
2n

A MAC

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

X Y
16 16

Multiplier

32

40

ADD / SUB

40
Guard bits
8 32

A MAC unit with accumulator guard bits

• The processor core connects to these memory spaces by two separate bus sets,
allowing two simultaneous access to memory. This arrangement doubles the
processor memory bandwidth.
•
• Zero-overhead looping: one common characteristics of DSP algorithms is that
most of the processing time is split on executing instructions contained with
relatively small loops.
• The term zero overhead looping means that the processor can execute loops
without consuming cycles to test the value of the loop counter, perform a
conditional branch to the top of the loop, and decrement the loop counter.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

Processing Result
unit Data bus

Operands

Status Opcode
Instructions Data / Instructions

Control unit Data program

memory

Von Neuman Architecture

Processing Result / operands

unit Data
memory
Address

Status Opcode

Control unit
Program memory
Instructions

Address

Harvard Architecture

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

Processing Result / operands

unit Data
memory
Address

Status Opcode

Control unit
program memory
Instructions

Address

Modified Harvard Architecture

Data bus

MEMORY Peripheral
Program Data / Data Serial
ROM program DARAM port 1
SARAM Data /
program Serial
DARAM port 2
TDM
Serial port
Program bus Buffered
serial port
Memory Program controller Memory CALU CPU
control Multiplier Timer
Program counter mapped
Multiproc Status/control registers Accumulator Parallel Host
essing registers ACC buffer logic unit port
Auxiliary shifters (PAL) interface
Interrupt Hardware stack Resisters arithmetic
Generation logic Arithmetic
Initialisation logic unit Test /
Oscillator/ Instruction register Unit (ARAU) (ALU) emulation
timer
Data bus
Internal Architecture of the TMS320C5X DSP
• The advantages of DSP are:
Versatility:
• digital systems can be reprogrammed for other applications (at least where
programmable DSP chips are used)
• digital systems can be ported to different hardware (for example a different DSP
chip or board level product)
Repeatability:
• digital systems can be easily duplicated
• digital system responses do not drift with temperature

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

• digital systems do not depend on strict component tolerances.

•
Simplicity:
• some things can be done more easily digitally than with analogue systems
• DSP is used in a very wide variety of applications but most share some common
features:
• they use a lot of multiplying and adding signals.
• they deal with signals that come from the real world.
• they require a response in a certain time.
•

Figure: A block diagram (or dataflow graph)

• What is the difference between a DSP and a microprocessor ?
• The essential difference between a DSP and a microprocessor is that a DSP
processor has features designed to support high-performance, repetitive,
numerically intensive tasks.
• In contrast, general-purpose processors or microcontrollers (GPPs / MCUs for
short) are either not specialized for a specific kind of applications (in the case of
general-purpose processors), or they are designed for control-oriented
applications (in the case of microcontrollers).
• Features that accelerate performance in DSP applications include:
• Single-cycle multiply-accumulate capability; high-performance DSPs often have
two multipliers that enable two multiply-accumulate operations per instruction
cycle; some DSP have four or more multipliers.
•
• Specialized addressing modes, for example, pre- and post-modification of address
pointers, circular addressing, and bit-reversed addressing.
• Most DSPs provide various configurations of on-chip memory and peripherals
tailored for DSP applications. DSPs generally feature multiple-access memory
architectures that enable DSPs to complete several accesses to memory in a single
instruction cycle.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

• Specialized execution control. Usually, DSP processors provide a loop instruction

that allows tight loops to be repeated without spending any instruction cycles for
updating and testing the loop counter or for jumping back to the top of the loop
• DSP processors are known for their irregular instruction sets, which generally
allow several operations to be encoded in a single instruction.
• For example, a processor that uses 32-bit instructions may encode two additions,
two multiplications, and four 16-bit data moves into a single instruction.
• In general, DSP processor instruction sets allow a data move to be performed in
parallel with an arithmetic operation. GPPs / MCUs, in contrast, usually specify a
single operation per instruction.
• What is really important is to choose the processor that is best suited for your
application.
• If a GPP/MCU is better suited for your DSP application than a DSP processor, the
processor of choice is the GPP/MCU.
• It is also worth noting that the difference between DSPs and GPPs/MCUs is
fading: many GPPs/MCUs now include DSP features, and DSPs are increasingly
adding microcontroller features.
Module 1: learning unit 2
8085 Microprocessor
ContentsGeneral definitions
• Overview of 8085 microprocessor
• Overview of 8086 microprocessor
• Signals and pins of 8086 microprocessor
The salient features of 8085 µp are:
• It is a 8 bit microprocessor.
• It is manufactured with N-MOS technology.
• It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB)
memory locations through A0-A15.
• The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7.
• Data bus is a group of 8 lines D0 – D7.
• It supports external interrupt request.
• A 16 bit program counter (PC)
• A 16 bit stack pointer (SP)
• Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
• It requires a signal +5V power supply and operates at 3.2 MHZ single phase
clock.
• It is enclosed with 40 pins DIP (Dual in line package).
Overview of 8085 microprocessor
¾ 8085 Architecture
• Pin Diagram
• Functional Block Diagram

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

X1 1 40 Vcc
X2 39 HOLD
2 DMA
RESE OUT 3 38 HLDA
SOD 4 37 CLK ( OUT)
Serial i/p, o/p signals RESET IN
SID 5 36
TRAP 6 35 READY
7
IO / M
RST 7.5 34
RST 6.5 8 33 S1
RST 5.5
9
8085 A 32 RD
INTR 10 31 WR
IN T A 11
30 ALE
AD0 12
29 S0
AD1 13
28 A15
AD2 A14
14 27
AD3 15 26 A13
AD4 25 A12
16
AD5 24 A11
17
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8

Pin Diagram of 8085

Signal Groups of 8085
+5V GND
XTAL
X1 X2 Vcc Vss
A15
SID 5 High order Address bus
A8
SOD 4
TRAP AD7
RESET 7.5
RESET 6.5 AD0
RESET 5.5 ALE
INTR S1
READY S0
HOLD
IO / M
____
RESET IN
HLDA RD
WR
INTA

REST OUT CLK OUT

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

RES RES RES TRAP SID

INTA SIO
5. 5 6. 5 7. 5

INT
SERIAL I / O CONTROL
INTERRUPT CONTROL

8 BIT INTERNAL
DATA BUS

INSTRUCTION
ACCUMU- (8) MULTIPLXER
REGISTER( 8 )
LATOR TEMP REG
(8) R W(8)
E TEMP. REG.
G C REG ( 8 )
B REG ( 8 )
FLAG ( 5) .
S D REG ( 8 )
FLIP FLOPS E REG ( 8 )
E
INSTRUCTION H REG ( 8 ) L REG ( 8 )
ARITHEMETIC L
DECODER AND E
LOGIC UNIT ( ALU) STACK POINTER ( 16 )
MACHINE C
ENCODING PROGRAM COUNTER ( 16 )
(8) T
+5V INCREAMENT / DECREAMENT
ADDRESS LATCH ( 16 )
GND

X1 TIMING AND CONTROL

CLK
ADDRESS BUFFER ( DATA / ADDRESS
GEN 8)
X2 BUFFER ( 8 )
CONTROL STATUS DMA

CLK A 15 – A8
RESET IN
OUT READY RD WR ALE S0 S1 IO / M HOLD HLDA RESET OUT ADDRESS BUS
AD7 – AD0 ADDRESS /
BUFFER BUS

Block Diagram

Flag Registers
D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

General Purpose Registers

INDIVIDUAL B, C, D, E, H, L

COMBININATON
B & C, D & E, H&L

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

Memory
• Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.
• Program memory - program can be located anywhere in memory. Jump, branch
and call instructions use 16-bit addresses, i.e. they can be used to jump/branch
anywhere within 64 KB. All jump/branch instructions use absolute addressing.
• Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere.
• Stack memory is limited only by the size of memory. Stack grows downward.
• First 64 bytes in a zero memory page should be reserved for vectors used by RST
instructions.
Interrupts
• The processor has 5 interrupts. They are presented below in the order of their
priority (from lowest to highest):
•
• INTR is maskable 8080A compatible interrupt. When the interrupt occurs the
processor fetches from the bus one instruction, usually one of these instructions:
• One of the 8 RST instructions (RST0 - RST7). The processor saves current
program counter into stack and branches to memory location N * 8 (where N is a
3-bit number from 0 to 7 supplied with the RST instruction).
• CALL instruction (3 byte instruction). The processor calls the subroutine, address
of which is specified in the second and third bytes of the instruction.
• RST5.5 is a maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 2CH
(hexadecimal) address.
• RST6.5 is a maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 34H
(hexadecimal) address.
• RST7.5 is a maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 3CH
(hexadecimal) address.
• TRAP is a non-maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 24H
(hexadecimal) address.
• All maskable interrupts can be enabled or disabled using EI and DI instructions.
RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually
using SIM instruction.
Reset Signals
• RESET IN: When this signal goes low, the program counter (PC) is set to Zero,
µp is reset and resets the interrupt enable and HLDA flip-flops.
• The data and address buses and the control lines are 3-stated during RESET and
because of asynchronous nature of RESET, the processor internal registers and
flags may be altered by RESET with unpredictable results.
• RESET IN is a Schmitt-triggered input, allowing connection to an R-C network
for power-on RESET delay.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

• Upon power-up, RESET IN must remain low for at least 10 ms after minimum
Vcc has been reached.
• For proper reset operation after the power – up duration, RESET IN should be
kept low a minimum of three clock periods.
• The CPU is held in the reset condition as long as RESET IN is applied. Typical
Power-on RESET RC values R1 = 75KΩ, C1 = 1µF.
• RESET OUT: This signal indicates that µp is being reset. This signal can be used
to reset other devices. The signal is synchronized to the processor clock and lasts
an integral number of clock periods.
Serial communication Signal
• SID - Serial Input Data Line: The data on this line is loaded into accumulator bit
7 whenever a RIM instruction is executed.
• SOD – Serial Output Data Line: The SIM instruction loads the value of bit 7 of
the accumulator into SOD latch if bit 6 (SOE) of the accumulator is 1.
DMA Signals
• HOLD: Indicates that another master is requesting the use of the address and data
buses. The CPU, upon receiving the hold request, will relinquish the use of the
bus as soon as the completion of the current bus transfer.
• Internal processing can continue. The processor can regain the bus only after the
HOLD is removed.
• When the HOLD is acknowledged, the Address, Data RD, WR and IO/M lines are
3-stated.
• HLDA: Hold Acknowledge: Indicates that the CPU has received the HOLD
request and that it will relinquish the bus in the next clock cycle.
• HLDA goes low after the Hold request is removed. The CPU takes the bus one
half-clock cycle after HLDA goes low.
• READY: This signal Synchronizes the fast CPU and the slow memory,
peripherals.
• If READY is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data.
• If READY is low, the CPU will wait an integral number of clock cycle for
READY to go high before completing the read or write cycle.
• READY must conform to specified setup and hold times.
Registers
• Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and
load/store operations.
• Flag Register has five 1-bit flags.
• Sign - set if the most significant bit of the result is set.
• Zero - set if the result is zero.
• Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
• Parity - set if the parity (the number of set bits in the result) is even.
• Carry - set if there was a carry during addition, or borrow during
subtraction/comparison/rotation.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

General Registers
• 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When
used as a pair the C register contains low-order byte. Some instructions may use
BC register as a data pointer.
• 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When
used as a pair the E register contains low-order byte. Some instructions may use
DE register as a data pointer.
• 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When
used as a pair the L register contains low-order byte. HL register usually contains
a data pointer used to reference memory addresses.
• Stack pointer is a 16 bit register. This register is always
decremented/incremented by 2 during push and pop.
• Program counter is a 16-bit register.
Instruction Set
• 8085 instruction set consists of the following instructions:
• Data moving instructions.
• Arithmetic - add, subtract, increment and decrement.
• Logic - AND, OR, XOR and rotate.
• Control transfer - conditional, unconditional, call subroutine, return from
subroutine and restarts.
• Input/Output instructions.
• Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations,
etc.
Addressing mode
• Register - references the data in a register or in a register pair.
Register indirect - instruction specifies register pair containing address, where
the data is located.
Direct, Immediate - 8 or 16-bit data.
Module 1: learning unit 3
8086 Microprocessor
•It is a 16-bit µp.
•8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
•It can support up to 64K I/O ports.
•It provides 14, 16 -bit registers.
•It has multiplexed address and data bus AD0- AD15 and A16 – A19.
•It requires single phase clock with 33% duty cycle to provide internal timing.
•8086 is designed to operate in two modes, Minimum and Maximum.
•It can prefetches upto 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
•It requires +5V power supply.
•A 40 pin dual in line package
Minimum and Maximum Modes:
•The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a
single microprocessor configuration.
•The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a
multi micro processors configuration.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

GND 1 40 VCC
AD14 39 AD15
2
AD13 3 38 A16 / S3
AD12 4 37 A17 / S4
AD11 5 36 A18 / S5
AD10 6 35 A19/S6
AD9 7 34 BHE / S7
____
AD8
AD7
8 8086 33 MN/ MX

AD6
9
10
CPU 32 RD _____ _____
RQ / GT0 ( HOLD)
31 ___ _____
AD5 11 RQ / GT1
AD4
30 ( HLDA)
12 _______ ___
29 LOCK (WR) ____
AD3 13
28 ___ S2 (M / IO )
___
AD2
14 27 S1 (DT / R )
_____
AD1 15 26
AD0 S0 ( DEN )
16 25 ________ QS0 (ALE)
NMI 24 QS1 ( INTA )
17
INTR 18 23 TEST
CLK 19 22
READY
GND 20 21
RESET
Pin Diagram of 8086

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

VCC GND

A0 - A15, A16 / S3 – A19/S6

INTR

INTA ADDRESS / DATA BUS

INTERRUPT
INTERFACE
TEST D0 - D15

NMI 8086 ALE

MPU ___
RESET BHE / S7

M / IO
MEMORY I
/O
HOLD DMA ____ DT / R
CONTROLS
INTERFACE RD
_____
HLDA
WR
VCC
DEN
MODE
____
SELECT READY
MN / MX

CLK

Signal Groups of 8086

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

AH AL
ADDRESS BUS
BH BL ∑
CH CL ( 20 )
GENERAL DH DL BITS
REGISTERS
SP DATA BUS
BP
( 16 )
SI BITS
DI
ES
CS
SS
DS
ALU DATA IP
8
16 BITS 0
BUS 8
6
TEMPORARY REGISTERS CONTR B
OL U
LOGIC S

EU INSTRUCTION QUEUE
ALU CONTROQ BUS
L 1 2 3 4 5 6
SYSTEM
8 BIT

FLAGS BUS INTERFACE UNIT ( BIU)

EXECUTION UNIT ( EU )

Block Diagram of 8086

Internal Architecture of 8086
•8086 has two blocks BIU and EU.
•The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
•EU executes instructions from the instruction system byte queue.
•Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the
system bus and system performance.
•BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
•EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,
Flag register.
BUS INTERFACR UNIT:
•It provides a full 16 bit bidirectional data bus and 20 bit address bus.
•The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
•Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and
Bus control.
•The BIU uses a mechanism known as an instruction stream queue to implement a
pipeline architecture.
•This queue permits prefetch of up to six bytes of instruction code. When ever the queue
of the BIU is not full, it has room for at least two more bytes and at the same time the EU

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

is not requesting it to read or write operands from memory, the BIU is free to look ahead
in the program by prefetching the next sequential instruction.
•These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the
BIU fetches two instruction bytes in a single memory cycle.
•After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.
•The EU accesses the queue from the output end. It reads one instruction byte after the
other from the output of the queue. If the queue is full and the EU is not requesting access
to operand in memory.
•These intervals of no bus activity, which may occur between bus cycles are known as
Idle state.
•If the BIU is already in the process of fetching an instruction when the EU request it to
read or write operands from memory or I/O, the BIU first completes the instruction fetch
bus cycle before initiating the operand read / write cycle.
•The BIU also contains a dedicated adder which is used to generate the 20bit physical
address that is output on the address bus. This address is formed by adding an appended
16 bit segment address and a 16 bit offset address.
•For example: The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents
of the instruction pointer IP register.
•The BIU is also responsible for generating bus control signals such as those for memory
read or write and I/O read or write.
EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
•The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to perform the
read or write bys cycles to memory or I/O and perform the operation specified by the
instruction on the operands.
•During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.
•If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue.
•When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
•Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.
Module 1 and learning unit 4:
Signal Description of 8086•The Microprocessor 8086 is a 16-bit CPU available in
different clock rates and packaged in a 40 pin CERDIP or plastic package.
•The 8086 operates in single processor or multiprocessor configuration to achieve high
performance. The pins serve a particular function in minimum mode (single processor
mode) and other function in maximum mode configuration (multiprocessor mode ).
•The 8086 signals can be categorised in three groups. The first are the signal having
common functions in minimum as well as maximum mode.
•The second are the signals which have special functions for minimum mode and third
are the signals having special functions for maximum mode.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•The following signal descriptions are common for both modes.

•AD15-AD0: These are the time multiplexed memory I/O address and data lines.
• Address remains on the lines during T1 state, while the data is available on the data bus
during T2, T3, Tw and T4.
•These lines are active high and float to a tristate during interrupt acknowledge and local
bus hold acknowledge cycles.
•A19/S6,A18/S5,A17/S4,A16/S3: These are the time multiplexed address and status
lines.
•During T1 these are the most significant address lines for memory operations.
•During I/O operations, these lines are low. During memory or I/O operations, status
information is available on those lines for T2,T3,Tw and T4.
•The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.
•The S4 and S3 combinedly indicate which segment register is presently being used for
memory accesses as in below fig.
•These lines float to tri-state off during the local bus hold acknowledge. The status line
S6 is always low.
•The address bit are separated from the status bit using latches controlled by the ALE
signal.
S4 S3 Indication
0 0 Alternate Data
0 1 Stack
1 0 Code or none
1 1 Data

• BHE /S7: The bus high enable is used to indicate the transfer of data over the higher
order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-
D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is
low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be
transferred on higher byte of data bus. The status information is available during T2, T3
and T4. The signal is active low and tristated during hold. It is low during T1 for the first
pulse of the interrupt acknowledges cycle.
BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd
evenaddress
address
1 0 Lower byte from or to even address
1 1 None

• RD Read: This signal on low indicates the peripheral that the processor is performing s
memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of
any read cycle. The signal remains tristated during the hold acknowledge.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•READY: This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the 8086. the signal is active high.
•INTR-Interrupt Request: This is a triggered input. This is sampled during the last
clock cycles of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle.
•This can be internally masked by resulting the interrupt enable flag. This signal is active
high and internally synchronized.
• TEST This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low,
execution will continue, else the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
•CLK- Clock Input: The clock input provides the basic timing for processor operation
and bus control activity. Its an asymmetric square wave with 33% duty cycle.
•MN/ MX : The logic level at this pin decides whether the processor is to operate in either
minimum or maximum mode.
•The following pin functions are for the minimum mode operation of 8086.
•M/ IO – Memory/IO: This is a status line logically equivalent to S2 in maximum mode.
When it is low, it indicates the CPU is having an I/O operation, and when it is high, it
indicates that the CPU is having a memory operation. This line becomes active high in
the previous T4 and remains active till final T4 of the current cycle. It is tristated during
local bus “hold acknowledge “.
• INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt
acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.
•ALE – Address Latch Enable: This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches. This
signal is active high and is never tristated.
•DT/ R – Data Transmit/Receive: This output is used to decide the direction of data
flow through the transreceivers (bidirectional buffers). When the processor sends out
data, this signal is high and when the processor is receiving data, this signal is low.
•DEN – Data Enable: This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to
separate the data from the multiplexed address/data signal. It is active from the middle of
T2 until the middle of T4. This is tristated during ‘ hold acknowledge’ cycle.
•HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the
processor that another master is requesting the bus access.
•The processor, after receiving the HOLD request, issues the hold acknowledge signal on
HLDA pin, in the middle of the next clock cycle after completing the current bus
cycle.•At the same time, the processor floats the local bus and control lines. When the
processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an
asynchronous input, and is should be externally synchronized.
•If the DMA request is made while the CPU is performing a memory or I/O cycle, it will
release the local bus during T4 provided:
1.The request occurs on or before T2 state of the current cycle.
2.The current cycle is not operating over the lower byte of a word.
3.The current cycle is not the first acknowledge of an interrupt acknowledge sequence.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

4. A Lock instruction is not being executed.

•The following pin function are applicable for maximum mode operation of 8086.
•S2, S1, S0 – Status Lines: These are the status lines which reflect the type of operation,
being carried out by the processor. These become activity during T4 of the previous cycle
and active during T1 and T2 of the current bus cycles.
S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
• LOCK This output pin indicates that other system bus master will be prevented from
gaining the system bus, while the LOCK signal is low.
•The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until
the completion of the next instruction. When the CPU is executing a critical instruction
which requires the system bus, the LOCK prefix instruction ensures that other processors
connected in the system will not gain the control of the bus.
•The 8086, while executing the prefixed instruction, asserts the bus lock signal output,
which may be connected to an external bus controller.
•QS1, QS0 – Queue Status: These lines give information about the status of the code-
prefetch queue. These are active during the CLK cycle after while the queue operation is
performed.
•This modification in a simple fetch and execute architecture of a conventional
microprocessor offers an added advantage of pipelined processing of the instructions.
•The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6-
bytes) instruction can be prefetched from the memory and stored in the prefetch. This
results in a faster execution of the instructions.
•In 8085 an instruction is fetched, decoded and executed and only after the execution of
this instruction, the next one is fetched.
•By prefetching the instruction, there is a considerable speeding up in instruction
execution in 8086. This is known as instruction pipelining.
•At the starting the CS:IP is loaded with the required address from which the execution is
to be started. Initially, the queue will be empty an the microprocessor starts a fetch
operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd
or two bytes at a time, if the CS:IP address is even.
•The first byte is a complete opcode in case of some instruction (one byte opcode
instruction) and is a part of opcode, in case of some instructions ( two byte opcode
instructions), the remaining part of code lie in second byte.
•The second byte is then decoded in continuation with the first byte to decide the
instruction length and the number of subsequent bytes to be treated as instruction data.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•The queue is updated after every byte is read from the queue but the fetch cycle is
initiated by BIU only if at least two bytes of the queue are empty and the EU may be
concurrently executing the fetched instructions.
•The next byte after the instruction is completed is again the first opcode byte of the next
instruction. A similar procedure is repeated till the complete execution of the
program.•The fetch operation of the next instruction is overlapped with the execution of
the current instruction. As in the architecture, there are two separate units, namely
Execution unit and Bus interface unit.
•While the execution unit is busy in executing an instruction, after it is completely
decoded, the bus interface unit may be fetching the bytes of the next instruction from
memory, depending upon the queue status.
QS1 QS0 Indication
0 0 No operation
0 1 First byte of the opcode from the queue
1 0 Empty queue
1 1 Subsequent byte from the queue

• RQ / GT0 , RQ / GT1 – Request/Grant: These pins are used by the other local bus master
in maximum mode, to force the processor to release the local bus at the end of the
processor current bus cycle.
•Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
•RQ/GT pins have internal pull-up resistors and may be left unconnected.
•Request/Grant sequence is as follows:
1.A pulse of one clock wide from another bus master requests the bus access to 8086.
2.During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it
will enter the ‘hold acknowledge’ state at next cycle. The CPU bus interface unit is likely
to be disconnected from the local bus of the system.
3.A one clock wide pulse from the another master indicates to the 8086 that the hold
request is about to end and the 8086 may regain control of the local bus at the next clock
cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses.
There must be at least one dead clock cycle after each bus exchange.
•The request and grant pulses are active low.
•For the bus request those are received while 8086 is performing memory or I/O cycle,
the granting of the bus is governed by the rules as in case of HOLD and HLDA in
minimum mode.
General Bus Operation:
•The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus.
•The main reason behind multiplexing address and data over the same pins is the
maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP
package.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•The bus can be demultiplexed using a few latches and transreceivers, when ever
required.
•Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is
present on the bus only for one cycle.
•The negative edge of this ALE pulse is used to separate the address and the data or status
information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the
type of operation.
•Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

Memory read cycle Memory write cycle

T1 T2 T3 Tw T4 T1 T2 T3 Tw T4
CLK

ALE

S2 – S0
A19-A16 S3-S7 A19-A16 S3-S7
Add/stat
BHE Bus reserve BHE
Add/data for Data In Data Out D15 – D0
A0-A15 D15-D0 A0-A15 D15-D0
RD/INTA
Ready
READY Ready
DT/R Wait Wait

DEN

WR Memory access time

General Bus Operation Cycle in Maximum Mode

Minimum Mode 8086 System

•In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum
mode by strapping its MN/MX pin to logic 1.
•In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
•The remaining components in the system are latches, transreceivers, clock generator,
memory and I/O devices. Some type of chip selection logic may be required for selecting
memory or I/O devices, depending upon the address map of the system.
•Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are
used for separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•Transreceivers are the bidirectional buffers and some times they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals.
•They are controlled by two signals namely, DEN and DT/R.
•The DEN signal indicates the direction of data, i.e. from or to the processor. The system
contains memory for the monitor and users program storage.
•Usually, EPROM are used for monitor storage, while RAM for users program storage. A
system may contain I/O devices.
•The working of the minimum mode configuration system can be better described in
terms of the timing diagrams rather than qualitatively describing the operations.
•The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the second is
the timing diagram for write cycle.
•The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and
also M / IO signal. During the negative going edge of this signal, the valid address is
latched on the local bus.
•The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO
signal indicates a memory or I/O operation.
•At T2, the address is removed from the local bus and is sent to the output. The bus is
then tristated. The read (RD) control signal is also activated in T2.
•The read (RD) signal causes the address device to enable its data bus drivers. After RD
goes low, the valid data is available on the data bus.
•The addressed device will drive the READY line high. When the processor returns the
read signal to high level, the addressed device will again tristate its bus drivers.
•A write cycle also begins with the assertion of ALE and the emission of the address. The
M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending
the address in T1, the processor sends the data to be written to the addressed location.
•The data remains on the bus until middle of T4 state. The WR becomes active at the
beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
•The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O
word to be read or write.
•The M/IO, RD and WR signals indicate the type of data transfer as specified in table
below.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

T1 T2 T3 TW T4 T1

Clk

ALE

BHE S7 – S3
ADD / STATUS A19 – A16

ADD / DATA A15 – A0 Valid data D15 – D0

WR

DEN

DT / R

Write Cycle Timing Diagram for Minimum Mode

•Hold Response sequence: The HOLD pin is checked at leading edge of each clock
pulse. If it is received active by the processor before T4 of the previous cycle or during
T1 state of the current cycle, the CPU activates HLDA in the next clock cycle and for
succeeding bus cycles, the bus will be given to another requesting master.
•The control of the bus is not regained by the processor until the requesting master does
not drop the HOLD pin low. When the request is dropped by the requesting master, the
HLDA is dropped by the processor at the trailing edge of the next clock.

Clk

HOLD

HLDA

Bus Request and Bus Grant Timings in Minimum Mode System

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

Maximum Mode 8086 System •In the maximum mode, the 8086 is operated by
strapping the MN/MX pin to ground.
•In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
•In the maximum mode, there may be more than one microprocessor in the system
configuration.
•The components in the system are same as in the minimum mode system.
•The basic function of the bus controller chip IC8288, is to derive control signals like RD
and WR ( for memory and I/O devices), DEN, DT/R, ALE etc. using the information by
the processor on the status lines.
•The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are
driven by CPU.
•It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.
•AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance
of the MCE/PDEN output depends upon the status of the IOB pin.
•If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it
acts as peripheral data enable used in the multiple bus configurations.
•INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to
an interrupting device.
•IORC, IOWC are I/O read command and I/O write command signals respectively. These
signals enable an IO interface to read or write the data from or to the address port.
•The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used as memory read or write signals.
•All these command signals instructs the memory to accept or send data from or to the
bus.
•For both of these write command signals, the advanced signals namely AIOWC and
AMWTC are available.
•Here the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the available control and advanced
command signals.

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Clk DEN
S0 DT/ R Control bus
S1 8288 IORC
S2 IOWT
AEN MWTC
Reset Reset S0
Clk IOB
S1 CEN AL MRDC
Generator Clk
S2
RDY 8284 Ready + 5V

8086
CLK
AD6-AD15 A/D Address bus
A16-A19 Latches
A
dd
DT/R bu
BHE A0
DIR
Data CS0H CS0L RD CS WR RD
buffer WR
DEN G Memory Peripheral

Data bus

Maximum Mode 8086 System.

•R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse
as on the ALE and apply a required signal to its DT / R pin during T1.
•In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC. These signals are activated until T4. For an output, the AMWC or
AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.
•The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
•If reader input is not activated before T3, wait state will be inserted between T3 and T4.
•Timings for RQ/ GT Signals:
The request/grant response sequence contains a series of three pulses. The request/grant
pins are checked at each rising pulse of clock input.
•When a request is detected and if the condition for HOLD request are satisfied, the
processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1
(next) state.
•When the requesting master receives this pulse, it accepts the control of the bus, it sends
a release pulse to the processor using RQ/GT pin.

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One bus cycle

T1 T2 T3 T4 T1

Clk

ALE

S2 – S0 Active Inactive Active

Add/Status BHE, A19 – A16 S7 – S3

Add/Data A15 – A0 D15 – D0

MRDC

DT / R

DEN

Memory Read Timing in Maximum Mode

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

One bus cycle

T1 T2 T3 T4 T1

Clk

ALE

S2 – S0 Active Inactive Active

ADD/STATUS BHE S7 – S3

ADD/DATA A15-A0 Data out D15 – D0

AMWC or AIOWC

MWTC or IOWC

DT / R high
DEN

Memory Write Timing in Maximum mode.

Clk

RQ / GT

Another master CPU grant bus Master releases

request bus access

RQ/GT Timings in Maximum Mode.

Minimum Mode Interface
•When the Minimum mode operation is selected, the 8086 provides all control signals
needed to implement the memory and I/O interface.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•The minimum mode signal can be divided into the following basic groups: address/data
bus, status, control, interrupt and DMA.
•Address/Data Bus: these lines serve two functions. As an address bus is 20 bits long
and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A
20bit address gives the 8086 a 1Mbyte memory address space. More over it has an
independent I/O address space which is 64K bytes in length.
•The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0
through A15 respectively. By multiplexed we mean that the bus work as an address bus
during first machine cycle and as a data bus during next machine cycles. D15 is the MSB
and D0 LSB.
•When acting as a data bus, they carry read/write data for memory, input/output data for
I/O devices, and interrupt type codes from an interrupt controller.
Vcc GND

INTR
A0-A15,A16/S3 – A19/S6
INTA
Interrupt
Address / data bus
interface
TEST

D0 – D15
NMI
8086
MPU ALE
RESET
BHE / S7

M / IO Memory I/O
HOLD controls
DMA DT / R
interface
HLDA RD

WR

Vcc
DEN
Mode select
READY
MN / MX

CLK clock

Block Diagram of the Minimum Mode 8086 MPU

•Status signal:
The four most significant address lines A19 through A16 are also multiplexed but in this
case with status signals S6 through S3. These status bits are output on the bus at the same
time that data are transferred over the other bus lines.
•Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal
segment registers are used to generate the physical address that was output on the address
bus during the current bus cycle.
•Code S4S3 = 00 identifies a register known as extra segment register as the source of
the segment address.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•Status line S5 reflects the status of another internal characteristic of the 8086. It is the
logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level.

S4 S3 Segment Register

0 0 Extra

0 1 Stack

1 0 Code / none

1 1 Data

Memory segment status codes.

•Control Signals:
The control signals are provided to support the 8086 memory I/O interfaces. They
control functions such as when the bus is to carry a valid address in which direction data
are to be transferred over the bus, when valid write data are on the bus and when to put
read data on the system bus.
•ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on
the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse
at ALE.
•Another control signal that is produced during the bus cycle is BHE bank high enable.
Logic 0 on this used as a memory enable signal for the most significant byte half of the
data bus D8 through D1. These lines also serves a second function, which is as the S7
status line.
•Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress
and in which direction data are to be transferred over the bus.
•The logic level of M/IO tells external circuitry whether a memory or I/O transfer is
taking place over the bus. Logic 1 at this output signals a memory operation and logic 0
an I/O operation.
•The direction of data transfer over the bus is signaled by the logic level output at DT/R.
When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the
transmit mode. Therefore, data are either written into memory or output to an I/O device.

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This
corresponds to reading data from memory or input of data from an input port.
•The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is
in progress. The 8086 switches WR to logic 0 to signal external device that valid write or
output data are on the bus.
• On the other hand, RD indicates that the 8086 is performing a read of data of the bus.
During read operations, one other control signal is also supplied. This is DEN ( data
enable) and it signals external devices when they should put data on the bus.
•There is one other control signal that is involved with the memory and I/O interface.
This is the READY signal.
•READY signal is used to insert wait states into the bus cycle such that it is extended by
a number of clock periods. This signal is provided by an external clock generator device
and can be supplied by the memory or I/O sub-system to signal the 8086 when they are
ready to permit the data transfer to be completed.
•Interrupt signals: The key interrupt interface signals are interrupt request (INTR) and
interrupt acknowledge ( INTA).
•INTR is an input to the 8086 that can be used by an external device to signal that it need
to be serviced.
•Logic 1 at INTR represents an active interrupt request. When an interrupt request has
been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0
at the INTA output.
•The TEST input is also related to the external interrupt interface. Execution of a WAIT
instruction causes the 8086 to check the logic level at the TEST input.
•If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086
no longer executes instructions, instead it repeatedly checks the logic level of the TEST
input waiting for its transition back to logic 0.
•As TEST switches to 0, execution resume with the next instruction in the program. This
feature can be used to synchronize the operation of the 8086 to an event in external
hardware.
•There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and
the reset interrupt RESET.
•On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service
routine. The RESET input is used to provide a hardware reset for the 8086. Switching
RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service
routine.
•DMA Interface signals:The direct memory access DMA interface of the 8086
minimum mode consist of the HOLD and HLDA signals.
•When an external device wants to take control of the system bus, it signals to the 8086
by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the
8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3
through A19/S6, BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state.
The 8086 signals external device that it is in this state by switching its HLDA output to
logic 1 level.
Maximum Mode Interface
•When the 8086 is set for the maximum-mode configuration, it provides signals for
implementing a multiprocessor / coprocessor system environment.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/36

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•By multiprocessor environment we mean that one microprocessor exists in the system
and that each processor is executing its own program.
•Usually in this type of system environment, there are some system resources that are
common to all processors.
•They are called as global resources. There are also other resources that are assigned to
specific processors. These are known as local or private resources.
•Coprocessor also means that there is a second processor in the system. In this two
processor does not access the bus at the same time.
•One passes the control of the system bus to the other and then may suspend its operation.
•In the maximum-mode 8086 system, facilities are provided for implementing allocation
of global resources and passing bus control to other microprocessor or coprocessor.
INIT
Multi Bus
S0 BUSY
S1 CBRQ
S2 8289 BPRO
LOCK Bus BPRN
CRQLCK
CLK RESB BREQ
Vcc GND SYSB/RESB
ANYREQ CLK AEN IOB BCLK

INTR LOCK CLK AEN IOB

S0 MRDC
TEST CLK AEN IOB MWTC
S1 S0
NMI AMWC
S2 S1 8288 Bus IORC
RESET S2 controller IOWC
DEN AIOWC
DT/ R INTA
8086 MPU ALE MCE / PDEN
DEN
DT / R
ALE
A0-A15,
A16/S3-A19/S6
MN/MX
D0 – D15
BHE
RD
READY
QS1, QS0
Local bus control
RQ / GT1 RQ / GT0 8086 Maximum mode Block Diagram
•8288 Bus Controller – Bus Command and Control Signals:
8086 does not directly provide all the signals that are required to control the memory,
I/O and interrupt interfaces.
•Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced
by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of
each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow.
•S2S1S0 are input to the external bus controller device, the bus controller generates the
appropriately timed command and control signals.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/37

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

Status Inputs
CPU Cycles 8288
S2 S1 S0 Command
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port IOWC, AIOWC
0 1 1 Halt None
1 0 0 Instruction Fetch MRDC

1 0 1 Read Memory MRDC

1 1 0 Write Memory MWTC, AMWC

1 1 1 Passive None

Bus Status Codes

•The 8288 produces one or two of these eight command signals for each bus cycles. For
instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read
cycle is to be performed.
•In the code 111 is output by the 8086, it is signaling that no bus activity is to take place.
•The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals
provide the same functions as those described for the minimum system mode. This set of
bus commands and control signals is compatible with the Multibus and industry standard
for interfacing microprocessor systems.
•The output of 8289 are bus arbitration signals:
Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority
in (BPRN), bus request (BREQ) and bus clock (BCLK).
•They correspond to the bus exchange signals of the Multibus and are used to lock other
processor off the system bus during the execution of an instruction by the 8086.
•In this way the processor can be assured of uninterrupted access to common system
resources such as global memory.
•Queue Status Signals: Two new signals that are produced by the 8086 in the maximum-
mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue
status code, QS1QS0.
•Following table shows the four different queue status.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/38

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

QS1 QS0 Queue Status

0 (low) 0 No Operation. During the last clock cycle, nothing was

taken from the queue.
0 1 First Byte. The byte taken from the queue was the first byte
of the instruction.
1 (high) 0 Queue Empty. The queue has been reinitialized as a result
of the execution of a transfer instruction.
Subsequent Byte. The byte taken from the queue was a
1 1 subsequent byte of the instruction.

Queue status codes

•Local Bus Control Signal – Request / Grant Signals: In a maximum mode
configuration, the minimum mode HOLD, HLDA interface is also changed. These two
are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a
prioritized bus access mechanism for accessing the local bus.
Internal Registers of 8086
•The 8086 has four groups of the user accessible internal registers. They are the
instruction pointer, four data registers, four pointer and index register, four segment
registers.
•The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the
status register, with 9 of bits implemented for status and control flags.
•Most of the registers contain data/instruction offsets within 64 KB memory segment.
There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the processor
uses four segment registers:
•Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions.
•Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register
can be changed directly using POP instruction.
•Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions.
•Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX. AL in this case contains the low-
order byte of the word, and AH contains the high-order byte. Accumulator can be used
for I/O operations and string manipulation.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/39

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•Base register consists of two 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the word,
and BH contains the high-order byte. BX register usually contains a data pointer used for
based, based indexed or register indirect addressing.
•Count register consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. When combined, CL register contains the low-
order byte of the word, and CH contains the high-order byte. Count register can be used
in Loop, shift/rotate instructions and as a counter in string manipulation,.
•Data register consists of two 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains the low-
order byte of the word, and DH contains the high-order byte. Data register can be used as
a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number.
•The following registers are both general and index registers:
•Stack Pointer (SP) is a 16-bit register pointing to program stack.
•Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is
usually used for based, based indexed or register indirect addressing.
•Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
•Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string manipulation
instructions.
Other registers:
•Instruction Pointer (IP) is a 16-bit register.
•Flags is a 16-bit register containing 9 one bit flags.
•Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
•Direction Flag (DF) - if set then string manipulation instructions will auto-decrement
index registers. If cleared then the index registers will be auto-incremented.
•Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
•Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.
•Sign Flag (SF) - set if the most significant bit of the result is set.
•Zero Flag (ZF) - set if the result is zero.
•Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL
register.
•Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even.
•Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
during last result calculation.
Addressing Modes
•Implied - the data value/data address is implicitly associated with the instruction.
•Register - references the data in a register or in a register pair.
•Immediate - the data is provided in the instruction.
•Direct - the instruction operand specifies the memory address where data is located.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/40

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•Register indirect - instruction specifies a register containing an address, where data is

located. This addressing mode works with SI, DI, BX and BP registers.
•Based:- 8-bit or 16-bit instruction operand is added to the contents of a base register
(BX or BP), the resulting value is a pointer to location where data resides.
•Indexed:- 8-bit or 16-bit instruction operand is added to the contents of an index register
(SI or DI), the resulting value is a pointer to location where data resides
•Based Indexed:- the contents of a base register (BX or BP) is added to the contents of
an index register (SI or DI), the resulting value is a pointer to location where data resides.
•Based Indexed with displacement:- 8-bit or 16-bit instruction operand is added to the
contents of a base register (BX or BP) and index register (SI or DI), the resulting value is
a pointer to location where data resides.
Memory •Program, data and stack memories occupy the same memory space. As the
most of the processor instructions use 16-bit pointers the processor can effectively
address only 64 KB of memory.
•To access memory outside of 64 KB the CPU uses special segment registers to specify
where the code, stack and data 64 KB segments are positioned within 1 MB of memory
(see the "Registers" section below).
•16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
•Program memory - program can be located anywhere in memory. Jump and call
instructions can be used for short jumps within currently selected 64 KB code segment,
as well as for far jumps anywhere within 1 MB of memory.
•All conditional jump instructions can be used to jump within approximately +127 to -
127 bytes from current instruction.
•Data memory - the processor can access data in any one out of 4 available segments,
which limits the size of accessible memory to 256 KB (if all four segments point to
different 64 KB blocks).
•Accessing data from the Data, Code, Stack or Extra segments can be usually done by
prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by
default may use the ES or SS segments instead of DS segment).
•Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading word data
from even byte boundaries requires only one memory access.
•Stack memory can be placed anywhere in memory. The stack can be located at odd
memory addresses, but it is not recommended for performance reasons (see "Data
Memory" above).
Reserved locations:
•0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer
in format segment: offset.
•FFFF0h - FFFFFh - after RESET the processor always starts program execution at the
FFFF0h address.
Interrupts
The processor has the following interrupts:

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/41

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

•INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using

STI/CLI instructions or using more complicated method of updating the FLAGS register
with the help of the POPF instruction.
•When an interrupt occurs, the processor stores FLAGS register into stack, disables
further interrupts, fetches from the bus one byte representing interrupt type, and jumps to
interrupt processing routine address of which is stored in location 4 * <interrupt type>.
Interrupt processing routine should return with the IRET instruction.
•NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority then the maskable interrupt.
•Software interrupts can be caused by:
•INT instruction - breakpoint interrupt. This is a type 3 interrupt.
•INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
•INTO instruction - interrupt on overflow
•Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the
CPU processes this interrupt it clears TF flag before calling the interrupt processing
routine.
•Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape
opcode (type 7).
•Software interrupt processing is the same as for the hardware interrupts.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/42

 Unit 2

Memory Organization

The 8051 has two types of memory and these are Program Memory and Data Memory. Program
Memory (ROM) is used to permanently save the program being executed, while Data Memory (RAM)
is used for temporarily storing data and intermediate results created and used during the operation of
the microcontroller. Depending on the model in use (we are still talking about the
8051 microcontroller family in general) at most a few Kb of ROM and 128 or 256 bytes of RAM
is used. However…

All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64 kb memory.
It is neither a mistake nor a big ambition of engineers who were working on basic core development.
It is a matter of smart memory organization which makes these microcontrollers a real “programmers‟
goody“.

Program Memory

The first models of the 8051 microcontroller family did not have internal program memory. It was
added as an external separate chip. These models are recognizable by their label beginning with 803
(for example 8031 or 8032). All later models have a few Kbyte ROM embedded. Even though such an
amount of memory is sufficient for writing most of the programs, there are situations when it is
necessary to use additional memory as well. A typical example are so called lookup tables. They are
used in cases when equations describing some processes are too complicated or when there is no
time for solving them. In such cases all necessary estimates and approximates are executed in
advance and the final results are put in the tables (similar to logarithmic tables).
How does the microcontroller handle external memory depends on the EA pin logic state:

EA=0 In this case, the microcontroller completely ignores internal program memory and executes
only the program stored in external memory.

EA=1 In this case, the microcontroller executes first the program from built-in ROM, then the program
stored in external memory.

In both cases, P0 and P2 are not available for use since being used for data and address
transmission. Besides, the ALE and PSEN pins are also used.

Data Memory

As already mentioned, Data Memory is used for temporarily storing data and intermediate results
created and used during the operation of the microcontroller. Besides, RAM memory built in the
8051 family includes many registers such as hardware counters and timers, input/output ports, serial
data buffers etc. The previous models had 256 RAM locations, while for the later models this number
was incremented by additional 128 registers. However, the first 256 memory
locations (addresses 0-FFh) are the heart of memory common to all the models belonging to the
8051 family. Locations available to the user occupy memory space with addresses 0-7Fh, i.e. first
128 registers. This part of RAM is divided in several blocks.

The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to accessing
any of these registers, it is necessary to select the bank containing it. The next memory block (address
20h-2Fh) is bit- addressable, which means that each bit has its own address (0-
7Fh). Since there are 16 such registers, this block contains in total of 128 bits with separate addresses
(address of bit 0 of the 20h byte is 0, while address of bit 7 of the 2Fh byte is 7Fh). The third group
of registers occupy addresses 2Fh-7Fh, i.e. 80 locations, and does not have any special functions or
features.

Additional RAM

In order to satisfy the programmers‟ constant hunger for Data Memory, the manufacturers decided
to embed an additional memory block of 128 locations into the latest versions of the
8051 microcontrollers. However, it‟s not as simple as it seems to be… The problem is that electronics
performing addressing has 1 byte (8 bits) on disposal and is capable of reaching only
the first 256 locations, therefore. In order to keep already existing 8-bit architecture and
compatibility with other existing models a small trick was done.

What does it mean? It means that additional memory block shares the same addresses with
locations intended for the SFRs (80h- FFh). In order to differentiate between these two physically
separated memory spaces, different ways of addressing are used. The SFRs memory locations are
accessed by direct addressing, while additional RAM memory locations are accessed by indirect
addressing.
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Memory expansion

In case memory (RAM or ROM) built in the microcontroller is not sufficient, it is possible to add two
external memory chips with capacity of 64Kb each. P2 and P3 I/O ports are used for their addressing
and data transmission.

From the user‟s point of view, everything works quite simply when properly connected because most
operations are performed by the microcontroller itself. The 8051 microcontroller has two pins for data
read RD#(P3.7) and PSEN#. The first one is used for reading data from external
 data memory (RAM), while the other is used for reading data from external program memory (ROM).
Both pins are active low. A typical example of memory expansion by adding RAM and ROM chips
(Hardward architecture), is shown in figure above.

Even though additional memory is rarely used with the latest versions of the microcontrollers, we
will describe in short what happens when memory chips are connected according to the previous
schematic. The whole process described below is performed automatically.

When the program during execution encounters an instruction which resides in

external memory (ROM), the microcontroller will activate its control output ALE and set the first
8 bits of address (A0-A7) on P0. IC circuit 74HCT573 passes the first 8 bits to memory
address pins.
A signal on the ALE pin latches the IC circuit 74HCT573 and immediately afterwards 8 higher
bits of address (A8-A15) appear on the port. In this way, a desired location of additional program
memory is addressed. It is left over to read its content.
Port P0 pins are configured as inputs, the PSEN pin is activated and the
microcontroller reads from memory chip.

Similar occurs when it is necessary to read location from external RAM. Addressing is performed
in the same way, while read and write are performed via signals appearing on the control outputs RD
(is short for read) or WR (is short for write).

Interfacing External Memory with 8051 Microcontroller

We have seen that a typical 8051 Microcontroller has 4KB of ROM and 128B of RAM (most modern
8051 Microcontroller variants have 8K ROM and 256B of RAM).

The designer of an 8051 Microcontroller based system is not limited to the internal RAM and ROM
present in the 8051 Microcontroller. There is a provision of connecting both external RAM and ROM i.e.
Data Memory and Program.

The reason for interfacing external Program Memory or ROM is that complex programs written in high –
level languages often tend to be larger and occupy more memory.

Another important reason is that chips like 8031 or 8032, which doesn’t have any internal ROM, have to
be interfaced with external ROM.

A maximum of 64B of Program Memory (ROM) and Data Memory (RAM) each can be interface with the
8051 Microcontroller.

The following image shows the block diagram of interfacing 64KB of External RAM and 64KB of
External ROM with the 8051 Microcontroller.
In this tutorial, we have seen the 8051 Microcontroller Memory Organization, Internal ROM and RAM
and how to interface external ROM and RAM with 8051 Microcontroller.

Analog and digital interfacing:

Aim:
To convert an analog signal to its digital equivalent and read the digital value from one port of AT89C51, write
the same data on to other port to convert it back to analog value.
Components/Software:
1. Atmel 89C51 microcontroller
2. 8051 simulator- Win8051
3. Universal SP3 Programmer
4. Win8051 Simulator and Software to load the code into Universal SP3 Programmer
5. Computer System with Windows 98 or later operating system and RS-232 Cable
6. +5V D.C Power Supply
7. Analog to Digital converter (AD7574), Digital to Analog converter (DAC08)
8. Resistors
9. Capacitors
10. 10 MHz crystal oscillator
11. Signal Generator and CRO

Description:
An analog signal is converted to 8-bit digital value using the ADC chip AD7574. After the conversion is
complete, AD7574 will set pin to high. As (connected to P3.1) pin goes high, chip select pin and
read pin (connected to P3.0) are made low to get valid digital data on to the bus (PORT1).The digital
equivalent data is read from Port 1 and written back to Port 2. Digital data from port 2 is connected to DAC08
to convert it back to analog signal. As soon as data is read from the Port 1, P3.0 is set to start next conversion.
Since analog output of DAC08 is an inverted one, an inverting amplifier (TL081CP) is employed to invert it
back and for the gain adjustment. The details of ICs used are given below.
AD7574:
 8-bit resolution Analog to digital converter
 Employs successive approximation technique
 Microprocessor compatible
 Conversion time 15 µ sec
  Analog input can vary in between 0 to |-Vref|

DAC08:
 8-bit Digital to Analog converter
 85 nsec settling time

TL081CP:
 Operational amplifier (in present context operating as an inverting amplifier)

Procedure:
1. Write the assembly code in Win8051. Compile and simulate it.
2. Once the code is error free, run it and check output with the Simulator
3. After checking the code in the simulator, the code (file with .HEX extension) is loaded into Atmel 89C51
microcontroller using Universal SP3 Programmer.
4. Now connections are made as shown in the circuit diagram.
5. Switch on the supply and push Reset button.
6. Observe the results.
7. Switch off the supply.

Assembly Code:

Observation:
Both analog signal input and analog output are of same shape with out any distortion with a sampling period
of 15 µ sec.
Conclusion:
An analog signal is converted to digital equivalent using AD7574. Using AT89C51 the resultant digital data is
read from a port and written to other port to convert it back to analog form using DAC08.
Lecture 4

Input/Output and Interfacing

4.1 Introduction
Lectures 2 and 3 have described how a computer’s CPU and memory function indi-
vidually and interact with one another. But as yet no consideration has been given
to methods of getting information in to or out of the computer — without which the
whole exercise is pointless.
Computer Input-Output (I/O) can be described at a number of levels. Layers of soft-
ware protocols build on yet more layers of hardware definition, with the aim, of course,
of isolating those working at one level from (i) having to know detail of what happens
below and (ii) second-guess how the level above will be used. You’ve seen modularity
at work elsewhere to reduce the risk of design error.
Our first aim here is to consider I/O the lowest level in terms of register transfers. We
then move on to consider typical I/O devices in the context of microcontrollers.

4.2 Register transfers — yet again

Much of the CPU and memory is nothing more than an elaborate register transfer
machine, able to shunt Bytes from one place to another. It will then come as no
surprise that I/O, yet again, involves register transfers.
Recall that the CPU is able to output to and input from memory using

• an address bus and decoder to select a particular register in memory,

• a data bus to transfer the register’s contents in or out of the CPU, and
• a control bus to carry signals such at Read, Write, and Output Enable.

The same idea of can be exploited to select a particular device for output or input.

1
4/2 LECTURE 4. INPUT/OUTPUT AND INTERFACING

The idea is sketched in Fig. 4.1(b), which also illustrates that while reading and writing
data to memory is always performed in parallel, I/O to devices can be either parallel or
serial. The former is, of course, has higher bandwidth, but the latter is necessary if the
distance between CPU and device substantial. For many years, such serial communica-
tions were painfully slow, but fast serial links are nowadays available over the Universal
Serial Bus (USB) and IEEE 1394 Firewire.

MAR Decoder

MBR Location

CPU Memory (a)

Serial link
MAR Decoder
Serializer Parallelizer
MBR OR IO Register
Parallel link
CPU Device (b)

Figure 4.1: (a) A CPU selecting and transferring data to a particular register in memory shares much in
common with (b) a CPU doing the same with a particular device.

4.3 Buses
In a desktop PC, the bus typically consists of 50 to 100 separate lines in the three
functional groups of address, data and control, and made accessible on the computer’s
motherboard via slots. The example shown in Fig. 4.2(b) is an ISA bus (now obsolete,
but chosen for the clarity of the picture).
A microcontroller will have the same buses, but there is no equivalent motherboard —
buses, memory and i/o devices are usually held within a single IC package.
The design of buses is made awkward by the intricacies of timing. Not only do different
devices have different speeds of operation, but transport delay accumulates from
• logic or propagation delay — the time spent between input and output changes in
a gate, say 3–6 ns.
• capacitive delay√— around 0.08 ns pF−1 , with delays of 5 ns typical.
• transit time — LC where L and C are the inductance and capacitance per unit
length — is around 6 ns m−1 .
4.4. STRATEGIES FOR I/O 4/3

CPU Memory I/O I/O

Control Bus
Data Bus
Address Bus

Figure 4.2: (a) Address, Control and Data buses schematically. In many computers the buses are made
accessible using connectors into which cards are slotted.

There are two major design approaches to bus timing. Synchronous design requires
devices to respond within a specified time with no continuous checks of whether the
device did receive the data. This is fast, but not suitable when a mix of fast and slow
devices sit on the bus. In asynchronous design, devices are considered to have their
own clocks, and they a treated as separate RTL modules. The CPU and IO device then
has to negotiate transmission and receipt using two control bus signals that continually
monitor readiness to send and received data.
(It is rather dry material, but if you are interested there is a further note on the course
website.)

4.4 Strategies for I/O

There are a number of generic types of I/O. An attempt to categorize those we will
discuss is shown in in Fig. 4.3. Here we are primarily concerned with I/O that directly
involves the CPU accessing registers on a device. This is called Programmed I/O, as
opposed to Direct Memory Access and Channel I/O that will be mentioned in passing
later.
Within programmed I/O we will compare and contrast Port-mapped I/O with Memory-
mapped I/O, and will conclude that they are actually very similar, but that Port-
mapped is more suited to microcontrollers.
Last we will contrast Polled I/O with Interrupt-driven I/O, the latter being a method
of allowing devices to initiate I/O and hence avoid the waste of CPU cycles in the
former.
4/4 LECTURE 4. INPUT/OUTPUT AND INTERFACING

Programmed Direct Memory

I/O Access
Port−mapped Memory−
I/O Mapped I/O

Polled Interrupt−
I/O driven I/O

Figure 4.3: Some types of I/O, in something of a hierarchy. Don’t read this too rigidly – some might
put Interrupt-drive as a fourth branch at the top-level.

4.5 Port-mapped I/O versus Memory-mapped I/O

4.5.1 Register-based I/O

Consider the set of 8 I/O registers that sit on a special port address bus and special
port data bus, as shown in Fig. 4.4(a). Our special address bus would need just three
lines, and a 3-8 line decoder would determine which register to transfer to or from.
In practice there is no need to group the registers together physically. As illustrated in
Fig. 4.4(b), they can sit separately on the bus — here as registers belonging to three
separate devices occupying three slots.

Selection I/O registers

7
6
R/W by peripherals

3 5

Port 3
4
address 3
space

2
1 2 7
0 1 4 6
0 3 5
16 16

Data to and from registers Data to and from registers

(a) (b)

Figure 4.4: I/O registers on “special” buses.

4.5. PORT-MAPPED I/O VERSUS MEMORY-MAPPED I/O 4/5

4.5.2 Port-mapped I/O

A moment’s consideration will suggest that the arrangement in Fig. 4.4 could be much
more economically achieved by using the main data and address buses, and just con-
necting the lowest 3 address lines A0-A2 to the IO registers.
This nearly works. Unfortunately the addresses (0 to 7) of the IO registers would
overlap those of the corresponding registers in main memory. This is easily solved by
introducing a new control level to select between use of main memory and use of I/O
register — we could call this USEmem/USEport. On the CPU side, this would be
provided by a Level from the Control Unit. On the Memory/Port side, USEmem will
connect up (perhaps with some intermediate logic in a system with several memory
chips) with the memory’s ChipSelect, and we need a similar ChipSelect on each set of
IO registers.
This approach to I/O, drawn out in Fig. 4.5 is called Port-Mapped I/O.
Address Main Memory IO Registers

24 3 3 3

CS 2 7
1 1 4 6
0 0 3 5
Data 16

Data to and from registers

USEmem/USEport

Figure 4.5: Port-mapped I/O registers can sit on the main buses, but there must be a control level that
determines whether to use main memory or the ports.

A further requirement is that each IO register is readable and writeable both by the
cpu and by the external peripheral. Such devices are called “dual-ported” registers or,
when grouped in numbers, dual-ported RAM. One might imagine making a Dual-ported
RAM from a Single-ported RAM with multiplexers on both the address and data lines.
Commercial devices are much more sophisticated, allowing simultaneous reading from
the same address, and simultaneous reading and writing from different addresses.
4/6 LECTURE 4. INPUT/OUTPUT AND INTERFACING

Usually a peripheral device will require several port addresses, some for the transfer
of “proper” data, and others for the transfer of status information about the device.
Status information is used inter alia to implement another level of handshaking (see
later). In Fig. 4.6 we assume that 12 address lines (of our usual 24) are used to address
212 ≡4K I/O registers, 2 Bytes wide.

Address Address FFF

A0−A23 FFFFFF A0−A11

28F
Decoder

Decoder
DP
Main Device
IO
Memory Registers

000000 000
Data

USEmem USEport
Control
IOR
IOW

Figure 4.6: Port address space with 212 locations 0 to FFF in hex.

CPU’s that support port-mapping are equipped with IN and OUT instructions. For
example:
LDA # 0 x9A80 ;; get 9 A80 hex into accumulator
OUT 0 x28F ;; and send it to port with address 0 x28F

In Fig. 4.6, it is assumed that the IN and OUT instruction generate CS Levels IOR and
IOW, respectively, so

USEport = IOR + IOW

USEmem = USEport.

4.5.3 Memory-mapped I/O

Recall that it unlikely that the entire memory address space is filled with physical main
memory. We could do away with the need to select between USEmem or USEport if we
put the I/O Registers into available gaps in the memory address space. The scheme,
called memory-mapped I/O is sketched in Fig.4.7.
As earlier, dual-ported registers are required, but now writing and reading to a device
uses the standard instruction for loading from and storing into memory. For example:
4.5. PORT-MAPPED I/O VERSUS MEMORY-MAPPED I/O 4/7

R/W by peripherals
I/O registers

Memory
address I/O registers
space
R/W by
peripherals
Main 24 24 24
Memory Main
Memory I/O registers I/O registers

(a) (b)

Figure 4.7: Memory mapped I/O. (a) IO-memory is in the memory address space. The physical layout
in (b) indicates that io memory and main memory are physically distinct, and plug separately into the
address and data buses.

LDA # 0 x9A80 ;; get 9 A80 hex into accumulator

STA 0 x00CC00 ;; and send it to register at 00 CC00 hex (24 bit address )

4.5.4 The methods compared

Both methods have a mix of memory and I/O registers on the same bus — but port-
mapped seems to have the disadvantage of requiring extra control wires.
So why is port-mapping used, particularly in microcontrollers? There are two main
reasons.

• Microcontrollers typically have a relatively small address space (remember the 218
figure). This can rather easily be filled with physical main memory, leaving no
room for I/O registers.
• More crucial is the cost of decoding. In port-mapped I/O only the port address
lines require decoding, whereas in memory-mapped I/O all the main-memory’s
address lines require decoding.
For example, suppose we just have 8 I/O registers.
– In port-mapped I/O, each IO device only has to decode 3 lines to determine
whether it is being addressed, whereas
4/8 LECTURE 4. INPUT/OUTPUT AND INTERFACING

– In memory-mapped I/O all 24 have to be decoded. The jump from 3 to 24

does not sound much, but on the output side the difference is between 8 lines
and 16 777 216 lines and gates. Ouch! (We exaggerate a little: there are
cheaper ways of achieving the decoding, but it is a cost nonetheless.)

4.6 Scheduling I/O

4.6.1 Handshaking at different timescales
Full handshaking involve conversations between CPU and IO devices like ... CPU: “Are
you ready?” IOdev: “I’m ready” CPU: “Have you got it?” IOdev: “I’ve got it”.
We have already noted that handshaking occurs at the bus level to cope with subtle
timing uncertainties in asynchronous buses. However this type of handshaking occurs
via hardwired lines in the control bus, and at nano-second timescales.
We cannot reasonably use that fine-scale handshaking to cope with communication
between the cpu and devices which may be many orders of magnitude slower. (This
would akin to keeping a telephone open all day for a conversation that lasts 2 minutes.)

4.6.2 Buffered I/O

One approach to mitigating the mismatch in timescales and speeds is to output data
in bursts, buffering it in fast memory on the slow device, as shown in Fig. 4.8. A
First-In-First-Out (FIFO) buffer is filled quickly by the CPU, and then slowly emptied
by the peripheral device.

Peripheral
Emptied
slowly

Filled Slow
quickly part of
...

device

FIFO buffer

Figure 4.8: A fast FIFO data buffer.

Obviously, the buffer must be bigger than the volume of data that might be output in
4.6. SCHEDULING I/O 4/9

one burst, but even this is not robust. To ensure no data is lost the IOdevice must, at
very least, have a bit in its device status word that indicates to the CPU whether it is
READY or NOTREADY to receive data.
This then would seem to require handshaking at, or at least involving, the I/O software
level. We consider two ways of coordinating handshaking at this higher level, Polling
and Interrupts.

4.6.3 Polling
Polling is a simple, but often simplistic, software solution to determine whether a
device is ready to receive (or transmit) data. The CPU regularly check the status of
the device by reading the status bit (or word, if there are several bits).
As an example, the following code transfers 100 word of data from a array in memory
(starting at location 0x200) to a device whose status is checked by polling.
The output device is port-mapped at port 500 and its status bits are at location 501.
LDA #200 ; Load base address into AC
STA 22 ; Loc22 hold address of array element
LOOP : IN 501 ; read device status word
AND #1 ; is the lowest bit equal to 1?
BZ LOOP ; if not , jump to LOOP
LDA (22) ; Load contents of array location
OUT 500 ; write them to device
LDA 22 ; Load and
ADD #1 ; increment the location
STA 22 ; and store it back
SUB #300 ; Have we gone too far ?
BNZ LOOP ; If not , carry on looping

However this is obviously inefficient. Three instructions at the core of the polling loop
get executed over and over.
How wasteful could this be? Suppose the IO device handles some 1000 Bytes per
second. To handle one Byte takes 10−3 s. A 2 GHz CPU taking 4 cycles per instruction
will take (3 ∗ 4)/2 × 109 ≈ 10−8 secs to handle compute the polling loop, and so the
polling loop will execute approx 105 times while waiting for the device to be ready again!
Such inefficiency may be of no concern for an embedded microcontroller performing
the simplest of tasks. For example, no-one cares that the microcontroller in a cash-
dispenser is wasting its time waiting for your next button press — after all, what else
would it do? (No, don’t speculate.) However, if there is serious computation to be
done in a real time system, it matters a great deal.
4/10 LECTURE 4. INPUT/OUTPUT AND INTERFACING

Increment Complete n−th

n useful task

Check device Check device

status status

Ready? Ready?
No No
Yes Yes
Transfer data Transfer data
to device to device

(a) (b)

Figure 4.9: (a) Basic polling. (b) An attempt to poll while getting on with other useful tasks.

One way of mitigating the gross waste of Fig. 4.9(a) is to attempt to do something
useful between polls, as in Fig. 4.9(b). However, this relies on the program (and hence
programmer) ensuring that a device is checked sufficiently often — a miserable task
in a system where the various useful tasks take different times, and where there are
several devices with differing I/O rates.

4.6.4 Interrupt-driven I/O

If software alone cannot solve the problem, we must return to hardware. Rather than
one-to-monitoring, a better approach is to allow devices to signal in hardware to the
CPU that they require attention.
This is the basis of interrupt-driven I/O, in which the peripheral literally interrupts
the processor from its usual grind through the programmed instructions.
Elsewhere and already resident in the program memory are a set of interrupt service
subroutines, each of which contains the instructions to handle a particular sort of
interrupt. When the interrupt is detected (on the interrupt request (IRQ) control
line), the processor stops executing its currently programmed instructions, jumps to
execute the appropriate subroutine and, once completed, returns to carry on with the
programmed instructions.
There are various things that need to be done when an interrupt is received.
4.6. SCHEDULING I/O 4/11

1. Finish executing the current instruction.

2. "Recognize" the interrupt. Ie, determine which service routine is needed.
3. Save all the CPU register contents (PC, Registers, and Status Word) in memory.
The Stack memory is used for this.
4. Jump to the routine, execute it, and return.
5. Restore the PC, registers and status word from the stack.
6. Continue with original program sequence, as if nothing had happened.

So this is mostly like jumping to a standard subroutine. However, as this is a routine

which could be called at anytime and hence anywhere, there are no parameters to
be passed. In addition, notice that the registers and status word are saved. When a
programmer writes a subroutine, it is assumed that s/he will write it so that data being
worked on is not lost. However, an interrupt routine is not called by the programmer,
but by the machine, and can occur at any time.1 The machine must make sure the
CPU’s state can be fully restored after the interrupt.

IRQ=1? Jump to Int

Fetch Decode Execute Service Rtne
No Yes

Normal instruction cycle

Figure 4.10:

Care has to be taken not to get deluged by interrupts. A devices interrupts with
particular “priority” n, and when an interrupt at priority n is being dealt with, interrupts
at priority ≤ n are blocked. This doesn’t cancel the interrupt request, but simply
prevents it getting through. However, the most urgent form of interrupt is “non-
maskable”. These are usually associated with system functions affecting the machine’s
well-being. (Further reading in Clements: Principles of Computer Hardware.)

1
Nobody expects the Spanish Inquisition.
4/12 LECTURE 4. INPUT/OUTPUT AND INTERFACING

4.7 Microcontrollers
We are now in a position to appreciate the architecture of a typical microcontroller
which integrates on a single chip

• CPU,
• Memory (ROM, RAM and (E)EPROM),
• IO Ports (digital and A/D, pulse, serial/parallel comms, etc),
• IO interrupt control,
• Timers, and
• Internal buses to connect the components.

You might like to think about the changes you would need to make to our BSA to use
separate Program and Data Memories.

Hardware Interrupt Serial

Timers Controller I/O Ports
Comms

External bus

Clock

Program Data
CPU Memory Memory
(EPROM) (RAM)

Figure 4.11: A microcontroller with a Harvard architecture, where program and data memory are separate
(as used, eg, in the PIC family of micro-controllers).

Now we consider devices which might be connected to the I/O ports — not printers
and the like (most texts will discuss in some detail devices such as keyboards, printers
and disks), but devices used as part of a general engineering system for data acquisition
and control output.
4.8. INTERFACING FOR REAL-TIME CONTROL 4/13

4.8 Interfacing for Real-time Control

4.8.1 Simple Digital Input
By “simple” digital input we mean input from switches or other devices that produce a
few bits to indicate their state. For example, a car electronic managment system may
wish to monitor 10 switches indicating whether 5 seats are occupied and 5 seat-belts
buckled; or a chemical plant might wish to report whether valves are shut or not.
In Fig. 4.12 the 5 single wires are connected to the bits D[0] ... D[4] of the input
register, and bits D[7:5] are grounded. The inputs are clocked in regularly. Using an
IN portaddress instruction would transfer the register’s contents to the AC.
Suppose the port has address 0xFA. Suppose all D[4:0] are meant to be high, and alarm
is meant to be set off if any of the 5 inputs is low. The following (wasteful!) polling
code would monitor the inputs.
again : IN 0 xFA
SUB #0 x001F
BNZ alarm
JMP again
alarm : ..

Output
Plant

Sensors

Digital inputs CPU

Select
Decoder D4 3 2 1 D0
Input register

Enable
Data
Address
Control

Figure 4.12: The plant’s output is sensed and assumed to be turned into a binary (0/1) input.

In Fig. 4.12 the plant’s output is sensed and assumed to be turned into a binary (0/1)
input, which is clocked into a register. Note that as only the peripheral writes to the
register, and only the CPU reads from the register, it does not even need to be Dual
Ported! So a 74273 Octal D-type flip-flop with Clear would do. The CPU reads the
register by putting its PortAddress onto the Address Bus, and clocking its contents
into the MBR. The Enable line is derived from the IOR level mentioned earlier.
4/14 LECTURE 4. INPUT/OUTPUT AND INTERFACING

4.8.2 Simple Digital Output

In Fig. 4.13(a) the register is turned around to allow output from the AC to the output
register.
In Fig. 4.13(b) a relay for switching a large current is controlled. The relay is connected
to the msb output Q[7] of the flip-flop, but Q[6:0] are used as well.
Suppose the port is at OxFB, all output lines are uand that the current status is stored
in memory location 0x0123. We want to send the entire current status to the register,
except that we must ensure that the MSB is 1 to turn on the relay.
The code is
LDA 0 x0123 ;; get desired status from memory
OR #0 x80 ;; OR with binary 1000 0000
OUT 0 xFB ;; out to port
STA 0 x0123 ;; store status for future use

OR’ing with 0x80 ensures that bit 7 is switched ON, but leaves the other outputs
unchanged.

PLANT

Digital outputs CPU

Select
Decoder Output register

WRITE
Data
Address
Control (a)

8 Q7 +
data
Output −
Select register
Solid
Q0 state
relay
Write D−type
reset (b)

Figure 4.13: (a) Simple digital output. (b) Relay control for switching a large current.
4.8. INTERFACING FOR REAL-TIME CONTROL 4/15

4.8.3 Analogue voltage input

This would handle any analogue sensor input such as a thermistor, strain gauge, etc

Analogue Channel select

Demand Convert
Sample IO
Multiplexer and ADC CPU Plant
Interface
Hold
EofC

Sample

Analogue
Sensor

Figure 4.14:

Vref Vsh

Vin

Vsh

6
Sample

V
Vin 5 3−bit binary
output
Vsh
4
8−3
priority
encoder
3

t 1
Hold
Track 0
gnd

Figure 4.15:
4/16 LECTURE 4. INPUT/OUTPUT AND INTERFACING

4.8.4 Analogue voltage output

This of course requires a D to A converter, typically achieved using an R-2R ladder as
described in you P2 OpAmp notes.

Sample
Select

DAC ZOH Vin

CPU IO Interface Plant Vsh

DAC

Sample

DAC
VZOH
R R R 2R

Vref
10V
2R 2R 2R 2R

8 4 2 1
MSB LSB

Figure 4.16: DAC interface, and R-2R ladder for D/A conversion.

The IO interface merely allows several DACs to be handled easily. The address will
select both the Interface and the particular DAC, and the Digital o/p is written from
the AC to the output port, and thence to the DAC. Within the DAC, the Data bits set
the switches in an R-2R ladder. On the output side of the DAC is a Zero-order-hold,
which is a sample an hold device which ensures the DAC analogue output stays at a
fixed value until the next conversion.
4.9. DIGITAL CONTROL SYSTEM 4/17

4.9 Digital Control System

The devices for input and output have been introduced separately, but in closed loop
control we want both present so that the sensor measurements can affect the output.
There is an endless list of applications — active suspension, robot positioning, building
stabilization, chemical reaction control, air conditioning control, docking control for
ships, and so on.
A typical representation of such a system is shown in Fig. 4.17, where the continuous
output y (t) is sampled and held and digitized, giving discrete time samples of the input
y (kT ), where T is the sampling period and k = 0, 1, 2, . . ..
The desired value of y is r (kT ), and a key quantity to consider is the error between r
and the ouput y
e(k) = r (k) − y (k) .

r(t) S&H r(kT)

+
ADC c(kT) DAC c(t) y(t)
Plant’s
Computer then G(s)
S&H ZOH
+
y(t) ADC y(kT)
Sensing
1

Figure 4.17:

Aside from this subtraction, what computations are done in the computer box?
That is the subject of the lectures on control, but, as a foretaste of heaven to come,
consider in the time domain the commonly used (and abused) PID controller.
Its output is the sum of terms which are proportional to the error, the error’s integral
and the error’s derivative.

 Z 
1
c(t) = K e(t) + e(t)dt + Td ė(t)
Ti
Differentiate both sides to get rid of the integral
 
1
ċ(t) = K ė(t) + e(t) + Td ë(t)
Ti
4/18 LECTURE 4. INPUT/OUTPUT AND INTERFACING

Now substitute backward differences for the derivatives ...

c(k) − c(k − 1) e(k) − e(k − 1)
ċ(k) ≈ and ė(k) ≈
T T
and
ė(k) − ė(k − 1) e(k) − 2e(k − 1) + e(k − 2)
ë(k) ≈ ≈
T T2
Rearrange to obtain
   
T Td Td
c(k) = c(k − 1) + K 1 + + e(k) − 1 + 2 e(k − 1)
Ti T T

Td
+ e(k − 2)
T
= c(k − 1) + Ae(k) + Be(k − 1) + Ce(k − 2) .

The constants depend on the problem in hand (as you will learn).
The important thing here is that there is causal recipe for updating the output, using
stored values of

• the previous output c(k − 1), and

• the previous two values of the error e(k − 1), e(k − 2)

and

• the current error e(k)

It would not take much to write the instructions ...

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

Microcontroller
Contents
•Introduction
•Inside 8051
•Instructions
•Interfacing
Introduction
• Definition of a Microcontroller
• Difference with a Microprocessor
• Microcontroller is used where ever
Definition
• It is a single chip
• Consists of Cpu, Memory
• I/O ports, timers and other peripherals
Difference

MICRO CONTROLLER MICRO PROCESSER

• It is a single chip • It is a cpu
• Consists Memory, • Memory, I/O Ports to be
• I/o ports connected externally.

CPU
CPU MEMORY
MEMORY

I/O PORTS I/O PORTS

Where ever
• Small size
• Low cost
• Low power
Architecture
•Harvard university
The Architecture given by Harvard University has the following advantages:
1: Data Space and Program Space are distinct
2: There is no Data corruption or loss of data
Disadvantage is:
1: The circuitry is very complex.
Features

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/1

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

• 8 bit cpu
• 64k Program memory (4k on chip)
• 64k Data memory
• 128 Bytes on chip
• 32 I/O
• Two 16 bit timers
• Full duplex UART
• 6 Source/5 Vector interrupts with two level priority levels
• On chip clock Oscillator.
Block Diagram
External Interrupts
4k On chip
Interrupt ETC Counter inputs
flash
control
128 Bytes Timer 1
RAM Timer 0

CPU

OSC Serial Port

Bus Control 4 I/O ports

PSEN ALE TXD RXD

P0 P2 P1 P3

Memory Architecture

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/2

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

FFFFH:

EXTERNAL

EXTERNAL

INTERNAL
FFH:

EA=0 EA=1
EXTERNAL INTERNAL 0000H:
00
0000
RD WR
PSEN
SFR Map

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/3

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

Internal Memory
7FH
Scratch Pad
30H
Bit Memory
20H
Bank 3 (R0-R7)
18H
Bank 2 (R0-R7)
10H
Bank 1 (R0-R7)
08H
Bank 0 (R0-R7)
00H
Pin connections

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/4

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

Overview of 8096 16 bit microcontroller

Features
• 232 Byte Register File.
• Register to Register Architecture.
• 10 bit A/D Converter with S/H.
• Five 8 bit I/O ports.
• 20 Interrupt Sources.
• Pulse Width Modulation Output.
• High speed I/O subsystem.
• Dedicated Baud Rate Generator.
• Full Duplex Serial Port.
• 16 bit Watchdog Timer.
Introduction
• The MSC-96 family members are all high performance microcontroller with a 16
bit CPU and atleast 230 bytes of on-chip RAM.
• Intel MSC-96 family easily handles high speed calculations and fast input/out
operations.
• All of the MCS-96 components share a common instruction set and architecture.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/5

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

• However the CHMOS components have enhancements to provide higher

performance with lower power consumption.
• These microcontroller contains dedicated I/O subsystem and perform 16-bit
arithmetic instructions including multiply and divide operations.
• CPU: The major components of the MCS-96 CPU are the Register File and the
Register / Arithmetic Logic Unit (RALU).
• Location 00H through 17H are the I/O control registers or Special function
registers (SFR).
• Locations 18H and 19H contains the stack pointer, which can serve as general
purpose RAM when not performing stack operations.
• The remaining bytes of the register file serve as general purpose RAM, accessible
as bytes, words or double-words.
• Calculations performed by the CPU take place in the RALU. The RALU contains
a 17bit ALU, the program status word (PSW), the program Counter (PC), a loop
counter and three temporary registers.
• The RALU operates directly on the Register Files, thus eliminating accumulator
bottleneck and providing for direct control of I/O operations through the SFR.
Architecture
• The MCS-96 supports a complete instruction set which includes bit operations,
byte operations, word operations, double-word operations (unsigned 32 bit), long
operations (signed 32 bit), flag manipulations as well as jump and call
instructions.
• All the standard logical and arithmetic instructions function as both byte and word
operations.
• The jump bit set and jump bit clear instructions can operate on any of the SFR or
bytes in the lower register files. These fast bit manipulations allow for rapid I/O
functions.
• Byte and word operations make up the instruction set. The assembly language
ASM-96 uses a “B” suffix on a mnemonic for a byte operation or for word
operation.
• Addressing modes: This supports the following modes.
• Register-direct, indirect, indirect with auto-increment, immediate, short-indexed
and long-indexed.
• These modes increase the flexibility and overall execution speed of the MCS-96
devices.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/6

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

Clock Generator Vcc

Internal On chip ROM/ Power
Vss
RAM EPROM (optional) and
CPU Vss
Peripheral ground Vss
transaction Register RALU Control signals
server File Memory controller
(PTS) 16 Address / data bus
Prefetch Queue
16

Vref A/D Programmable

interrupt Event Processor
converter Array or HSIO
(10 bit) controller
GND
Serial I/O
(UART &
SSIO) Timer 1 & 2 I/O Ports

T R
SS SS
XX T1T1 T2T2 EPA0-3
Po Po Po Po PoPo Po
CC DD
DD C DI C DI or HSIO
rt rt rt rt rt rt rt
0 L R L R 0 1 2 3 4 5 6
KR Only K K KR
MSC 96 Block Diagram
RALU Memory Controller
Master PC 6-bit loop
counter Bus controller
CPU
Upper word 2nd operand
register Register MUX
Register
File Lower word Constants
register 4 byte Slave Addr Data
Queue PC Reg. Reg.
Program Bit select
Register status word
RAM register

MUX Instruction
reg.

A B Micro code
Code PSW Engine
SFRs Control ALU
CPU control and
Status Signals Interrupt
Controller

16
CPU Buses 8

Block Diagram of Register File, RALU, Memory Controller and Interrupt Controller

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/7

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

Mnem Dest or Src1 ; One operand direct

Mnem Dest, Src1 ; Two operand direct
Mnem Dest, Src1, Src2 ; Three operand direct
Mnem #Src1 ; One operand immediate
Mnem Dest, #Src1 ; Two operand immediate
Mnem Dest, Src1, Src2 ; Three operand immediate
Mnem [addr] ; one operand indirect
Mnem [addr] + ; one operand indirect auto-increment
Mnem Dest, [addr] ; Two operand indirect
Mnem Dest, [addr] + ; Two operand indirect auto-increment
Mnem Dest, Src1, [addr] ; Three operand indirect
Mnem Dest, Src1, [addr] + ; Three operand indirect auto-increment
Mnem Dest, offs [addr] ; Two operand indexed (short or long )
Mnem Dest, Src1, offs [addr] ; Three operand indexed (short or long )

Instruction Format
8096 Peripherals
• Standard I/O Ports – The 8096 has five 8 bit I/O ports.
• Port 0 is an input port that is also the analog input for the A/D converter.
• Port 1 is a quasi-bidirectional port.
• Port 2 contains three types of port lines.
• Quasi-Bidirectional, input and output. Other functions on the 8096 share the input
and output lines with Port 2.
• Port 3 and 4 are open-drain bidirectional ports that share their pins with the
address/data bus.
• Timers – The 8096 has two 16 bit timers. Timer 1 and Timer 2.
• An internal clock increments the Timer 1 value every 8 state times. (A state time
is 3 oscillator periods)
• An external clock increments Timer 2 on every positive and negative transition.
• Either an internal or external source can reset Timer 2.
• This two timers can generate an interrupt when crossing the 0FFFFH/0000H
boundary.
• The 8096 includes separate, dedicated timers for serial port baud rate generator
and watchdog timer.
• The watchdog Timer is an internal timer that resets the system if the software fails
to operate properly.
• High Speed Input Unit (HSI) – The 8096 HIS unit can record times of external
events with a 9 state time resolution. It can monitor four independently
configurable HSI lines and captures the value of timer 1 when events takes place.
• The four types of events that can trigger captures include: rising edge only, falling
edge only, rising or falling edges, or every eight rising edge.
• The HSI unit can store upto 8 entries (Timer 1 values ).
• Reading the HSI holding register unloads the earliest entry placed in the FIFO.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/8

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

• The HSI unit can generate an interrupt when loading an entry into the HSI
holding register or loading the sixth entry into the FIFO.
• High Speed Output Unit (HSO) – The 8096 HSO unit can trigger events at
specified times based on Timer1 or Timer2.
• These programmable events include: starting an A/D conversion, resetting
Timer2, generating upto four software time delays, and setting or clearing one or
more of the six HSO output lines.
• The HSO unit stores pending event and specified times in a Content Addressable
Memory (CAM) file. This file stores upto 8 commands.
• Each command specifies the action time, the nature of the action, whether an
interrupt is to occur, and whether Timer1 or Timer2 is the reference timer.
• Every 8 state times the HSO compares the CAM locations for time matches. The
HSO unit triggers the specified event when it finds a time match.
• A command is cleared from the CAM as soon as it executes.
• Serial Port – The serial port on the 8096 has one synchronous (Mode 0) and
three asynchronous modes (Modes 1, 2 and 3).
• The asynchronous modes are full duplex.
• Mode 0, the synchronous mode, is to expand the I/O capability of the 8096 using
shift register.
• Mode 1 is the standard asynchronous mode used for normal serial
communication.
• Modes 2, 3 are 9-bit modes commonly used for multiprocessor communications.
• Pulse Width Modulator (PWM) – The PWM output waveform is a variable
duty cycle pulse that repeats every 256 state times.
• The PWM output can perform digital to analog conversions and drive several
types of motors that require a PWM waveform for more efficient operation.
• A/D Converter – The 8096 A/D converts an analog input to a 10 bit digital
equivalent.
• The main components of the A/D Converter are: 8 analog inputs, an 8 to 1
multiplexer, a sample and hold capacitor and resistor ladder.
• The A/D Converter can start a conversion immediately or the High Speed Output
unit can trigger a conversion at a preprogrammed time.
• The A/D converter performs a conversion in 88 state times. Upon completion of
each conversion the converter can generate a conversion complete interrupt.
• The 8X9X provides separate VREF and ANGND supply pins to isolate noise on
the Vcc or Vss lines.
• Interrupts – There are 21 interrupts sources and 8 interrupt vector on the 8096.
• When the interrupt controller detects one of the 8 interrupts it sets the
corresponding bit in the interrupt pending register. Individual interrupts are
enabled or disabled by setting or clearing bits in the interrupt mask register.
• When the interrupt controller decides to process an interrupt, it executes a “call”
to an interrupt service routine ISR. The corresponding interrupt vector contains
the address of the ISR. The interrupt controller then clears the associated pending
bit.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/9

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

7 6 5 4 3 2 1 0
0 0 1 1 Chip configuration byte
CCB (2018H) (ROM or EPROM)
Set to 1 for compatibility with future parts.
Bus width select
If set, then BUSWIDTH pin determines the bus
width. If cleared, then external 8-bit data bus is
selected.
Write strobe mode select
If set, then WRH# / BHE# becomes BHE# and WRL# /
WR# becomes WR#.
If cleared, then WRH# / BHE# becomes WRH# and
WRL# / WR# becomes WRL#.
Address valid strobe select
If set, then ALE / ADV# becomes ALE
If cleared , then ALE / ADV# becomes ADV#
IRC1 IRC0 Internal ready control mode
0 0 Limit to 1 wait state
0 1 Limit to 2 wait state
1 0 Limit to 3 wait state
1 1 Disable internal ready control
LOC1 LOC0 Internal ROM / EPROM lock modes
0 0 Read protected ; EPROM is also write protected.
0 1 Read protected
1 0 EPROM part is write protected
1 1 No operation
Chip configuration byte (CCB)
Configuring the 8096
• The 8096 can be operated in either the single-chip mode, or two of its ports can be
redefined to bring out the internal address bus and data bus.
• For the single chip mode, the internal ROM and EPROM must be accessed. This
choice is made by tying the EA# pin high.
• When EA pin is tied high, the internal ROM or EPROM is accessed during
instruction and data fetches from addresses 2080 to 3FFFH and for interrupt
vectors located at addresses 2000 to 2011H.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/10

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

8096BH

+5V EA

Single chip mode

READY Memory read EA: Tie to +5V to

8096BH use internal ROM
INST Instruction fetch
+5V BUSWIDTH ADV Address valid or EPROM
RD Read control
+5V or EA WRH Write high control EA: Tie to GND to
GND WRL Write low control disable internal
AD15 – AD0 Multiplexed bus
CCB (2018H) 16 ROM or EPROM
0 01

Expanded mode with 16 bit multiplexed bus

Modes of Intel 8096 operation.
READY Memory read EA: Tie to +5V to
8096BH use internal ROM
INST Instruction fetch
BUSWIDTH ADV Address valid or EPROM
RD Read control
EA WR Write control EA: Tie to GND to
+5V or A15 – A8 8 Write low control disable internal
GND AD7 – AD0 8 Multiplexed bus ROM or EPROM
CCB (2018H)
0 01

Expanded mode with 8 bit multiplexed bus

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/11

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

+ 5V
8096BH READY

CCB (No wait state)

x x

(a ) Avoiding wait states entirely, for use with fast external parts.

GND
8096BH READY

CCB (One, two or three wait states)

0 0 One wait state = 250 extra nanoseconds

0 1 Two wait state = 500 extra nanoseconds
1 0 Three wait state = 750 extra nanoseconds
(b ) Use with slower external parts.
Alternative use of the READY input.
8096BH READY
+5V AD15 A15
(16 bit BUSWIDTH
CCB
multiplexed
bus) 0 0 (Address-dependent wait state)

8096BH READY
BUSWIDTH A15 A15
(8 bit CCB (Address-dependent wait state)
multiplexed 0 0
bus)

(c ) external accesses to address below 8000H get an extra wait state, where as accesses
above 8000H get no extra wait state.
• When operated in the expanded mode the internal ROM or EPROM can still be
used by tying EA# high.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/12

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

• Accesses to the addresses 2000 to 2011H and 2080 to 3FFFH can be made to
access off-chip memory by tying the EA# pin low.
• If the EA pin is high, then we have the option of using the internal ROM or
EPROM together with external memory and devices.
• One of the options made available by the BH series over the original 8096 family
is the option to deal with either a 16 bit external data bus or else an 8 bit external
data bus.
• The latter options permits expanding the 8096 with a single byte wide static RAM
chip or with a single byte wide EPROM chip for program memory.
• The latter is particularly convenient for users who can either put their application
program into a single EPROM or who do not have the EPROM programming
capability to separate their object code into even addresses and odd addresses as
required for the two byte wide EPROM used with a 16 bit data bus.
• The choice of bus width is made in two places. When the 8096 comes out of reset,
it reads the content of address 2018H of our ROM or EPROM. This is called the
chip configuration CCB.
• The 8096 stores this byte in a chip configuration register which is unaccessable by
our software.
• Bit 1 works together with the external BUSWIDTH pin to determine the data bus
width (when the EA pin is tied low).
• While the BUSWIDTH pin is tied either high or low, it can actually be changed
during each bus cycle of normal operation.
• If it is tied to the A15 address lines, then accesses to external addresses 8000 to
FFFFH would use a 16-bit data bus while accesses to external addresses below
this would use an 8-bit data bus. In either case, the full 16 bit address bus is
brought out.
• When an 8-bit data bus is brought out, the lines which bring out the upper half of
the address bus do not have to be multiplexed.
• In this case, the designers of the chip have saved users the need for an external
latch for the upper half of the address bus by latching the address internally.
• The original 8096 parts gave the user of the expanded chip an ALE output. This
was used to latch the address. The new option is selected with a 0 in bit 3 of CCB.
The ADV# line remains high during any machine cycles which are not accessing
external memory, but goes low during external accesses. Because of this ADV#
can be used to simplify the decoding to enable external devices.
• In addition to the external access, ADV# drop low at precisely the current time to
latch the multiplexed address. Consequently, it can serve double duty, both
helping with decoding and also latching the multiplexed address.
• Another feature of the original 8096 parts operating in the expanded mode was
the need to decode a BHE# signal.
• This was used during writes to a byte at an odd address so that the lower byte on
the 16-bit data bus could be left unchanged.
• Users of the original 8096 parts had to gate BHE# together with a WR# signal to
generate two write signals.
• One for chips connected to the upper half of the data bus and one for chip
connected to the lower half of the data bus.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/13

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

• This option is selected with 0 bit 2 of CCB.

• INST output is a signal which takes on when the RD# line is active, signaling that
a read from an external device is taking place. If the read is an instruction fetch,
then INST will be high. Otherwise it will be low during the read cycle.
• Users of logia analyzers and designers of 8096 emulators can use this signal to
help sort out the activity on external bus.
• The READY control line permits the 8096 to run at full speed for its internal
accesses and yet to slow down for some of its external accesses.
• It is used in conjunction with bits 4 and 5 of CCB to introduce extra 250ns
(assuming a 12 MHz crystal) wait states into external read and write cycles.
• If the READY line is tied high then the CCB bits do not matter and no external
wait states are introduced into external read or writes.
• If the READY line is tied low (signifying that external devices are not ready),
then this READY signal can be overridden by the CCB bits.
• Thus 00 in bits 4 and 5 of CCB will now limit the delay to a signal wait state.
• READY line can be changed by dynamically from cycle to cycle. If it is tied to
the upper address lines, then we can position external devices which can run at
full speed in the 8000 to FFFF address range and slower external device needing
an extra wait state at lower addresses.
• The lock mode is selected by the coding of bit 6 and 7. Whether the software is in
on-chip manage to get the chip to execute code from external memory and then
have that external program dump the internal memory to the serial port.
• In a read-protected mode, only code executing from internal memory can read
from memory addresses between 2020 to 3FFFH.
• In a write-protected mode, no code can write to memory address between 2000
and 3FFFH.
• One problem arises with a memory protection scheme such as, if we purchase
ROM-protected parts from Intel, then before we use them, we would like to test
them.
• We can drive the EA# line low and use our own program to test all the resource
on the chip. This does not test the ROM contents.
• Intel supports the verification of ROM by including a 16byte security key, located
at address 2020 to 202FH. Before protected memory can read, the chip must read
external memory locations 4020 to 402FH and compare the contents with the
internal security key.
• Access to protected memory will only be allowed if a match I found for all 16
bytes.
• The first 26 addresses from the register file, used to set up and access almost all of
the on-chip resources. The rest of the page 0 is dedicated to internal RAM, for a
total of 230 bytes of RAM.
• While the ROM or EPROM extends from 2000 to 3FFFH, Intel reserves address
2012 to 2017H.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/14

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

Neither external read

External read cycle External write cycle
XATL nor external write cycle

(12 MHZ)
250 ns
CLK OUT

(4 MHz)

ADV#

RD#

WRH#

WRL#

Address out Data in Address Data out

AD15 – AD0 out
Timing for expand mode with 16 bit multiplexed bus
Neither external read
External read cycle External write cycle
XATL nor external write cycle

(12 MHZ)
250 ns
CLK OUT

(12 MHz)

ADV#

RD#

WRH#

Address out Address out

A15 –
A0

Address out Data in Address Data out

AD15 – AD0 out
Timing for expand mode with 8 bit multiplexed bus

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/15

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

REGISTERS EQU 0000H ; Registers extend upto 0019H

RAM EQU 001AH ; RAM extend upto 00FFH
EXTERNAL 1 EQU 0100H ; External memory space (upto 1FFDH)
PORT3 EQU 1FFEH
PORT4 EQU 1FFFH
ROM EQU 2000H ;ROM or EPROM, extends up to 3FFFH
INTERRUPT EQU 2000H ;Vector extends up to 2011H
- VECTORS
RESERVED EQU 2012H ;ROM up to 207FH is reserved for factory
;test code (except for CCB)
CCB EQU 2018H ;Chip configuration byte
START EQU 2080H ;User program or data up to 3FFFH

EXTERNAL2 EQU 4000H ;External memory space (upto FFFFH)

Intel 8096 memory space allocation.

SYMBOLIC NAMES FOR THE I/O REGISTERS OF THE 8096

R0 EQU 00H:WORD ;R Zero register (reads as 0000H)

AD_COMMAND EQU 02H:BYTE ; W A/D command register
AD_RESULT_LO EQU 02H:BYTE ;R A/D result, lo byte (byte read only )
AD_RESULT_HI EQU 03H:BYTE ;R A/D result, hi byte (byte read only )
HSI_MODE EQU 03H:BYTE ; W HSI mode register
HS0_TIME EQU 04H:WORD ; W HS0 time hi/lo (word write only)
HSI_TIME EQU 04H:WORD ;R HSI time hi/lo (word read only)
HS0_COMMAND EQU 06H:BYTE ; W HS0 command register
HSI_STATUS EQU 06H:BYTE ;R HSI status register
SBUF EQU 07H:BYTE ;R/W Receive buffer (read), Transmit buffer (write)
INST_MASK EQU 08H:BYTE ;R/W Interrupt mask register
INT_PENDING EQU 09H:BYTE ;R/W Interrupt pending register
WATCHDOG EQU 0AH:BYTE ; W Watchdog timer register
TIMER 1 EQU 0AH:WORD ;R Timer 1 hi/lo (word read only )
TIMER 2 EQU 0CH:WORD ;R Timer 2 hi/lo (word read only )
BAUD_RATE EQU 0EH:BYTE ; W Baud rate control register
PORT 0 EQU 0EH:BYTE ;R Port 0
PORT 1 EQU 0FH:BYTE ;R/W Port 1
PORT 2 EQU 10H:BYTE ;R /W Port 2
SP_CON EQU 11H:BYTE ; W Serial port control register
SP_STAT EQU 11H:BYTE ;R Serial port status register
SP EQU 18H:BYTE ;R /W Stack pointer

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/16

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

0000 On-chip registers 0000 - 0019

On-chip RAM 000A – 00FF

2000 On-chip ROM :

Interrupt vectors 2000 - 2011
Factory test code 2012 – 207F
User program 2080 – 3FFF
3FFF

* Off chip accessible address

*
* Intel 8096 cannot use direct (page 0) addressing for the off-
chip addresses.

FFFF
Intel 8096 expanded memory map
General Purpose I/O Ports
• Port 0 whose lines can serve as either general purpose inputs or alternatively as
input to the analog-to-digital converter family.
• Port 1 is a quasi-bidirectional I/O port.
• Port 2 includes four input lines, two output lines, and two quasi-bidirectional I/O
lines.
• Port 3 and 4 when used as ports, they have open drain outputs.
• By writing anything but a 1 to a line, it can serve as an input even as other lines
serve as outputs.
• Each output line needs the addition of a pullup resistor having a value of 15kΩ.
• In the expanded mode the bus lines gain the ability to drive both high and low,
forming the expansion bus without the need of pullup resistors.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/17

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

8096 A/D PORT 0

Converter (000E)
ACH7 7
ACH6 6
ACH5 5
ACH4 4
ACH3 3
ACH2 2 Not available with 48 pin
ACH1 1 DIP package.
ACH0 0
Vref +5v
0.1µF
Angnd

Port 0
8096 PORT 1
(000F)
7
6
5
4 Not available with 48 pin
3 DIP package.
2
1
0

Port 1 use as a quasi-bidirectional I/O port.

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/18

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

8096 PORT 2
(0010H)
7
6
Pulse width mode. 5
Out. PWM
T2RST 4
Inputs to timer 2 T2CLK 3
External interrupt EXTINT 2
RXD 1
Serial Port TXD 0

Not available with 48

pin DIP package.
Bit 6 and 7 are quasi bidirectional I/O lines with same
behavior and drive characteristic as port 1 lines.

Port 2
Expansion PORT 4 + 5V
8096 15KΩ
bus (1FFF)
AD15 7
AD14 6
AD13 5
AD12 4
AD11 3
AD10 2
AD9 1
AD8 0
Expansion PORT 3 (1FFE)
bus AD7 7
AD6 6
AD5 5
AD4 4
AD3 3
AD2 2
AD1 1
AD0 0
Pullup resistors are only needed on lines to
be used as output port lines

M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/19

 AP-248
APPLICATION
NOTE

Using The 8096

IRA HORDEN
MCO APPLICATIONS ENGINEER

September 1987

Order Number: 270061-002

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoev-
er, including infringement of any patent or copyright, for sale and use of Intel products except as provided in
Intel’s Terms and Conditions of Sale for such products.

Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer
Products may have minor variations to this specification known as errata.

*Other brands and names are the property of their respective owners.

² Since publication of documents referenced in this document, registration of the Pentium, OverDrive and
iCOMP trademarks has been issued to Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your
product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:

Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
Using The 8096 CONTENTS PAGE

1.0 INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1

2.0 8096 OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1
2.1. General Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1
2.1.1. CPU Section ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2
2.1.2. I/O Features ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
2.2. The Processor Section ÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
2.2.1. Operations and Addressing
Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
2.2.2. Assembly Language ÀÀÀÀÀÀÀÀÀ 7
2.2.3. Interrupts ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
2.3. On-Chip I/O Section ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
2.3.1. Timer/Counters ÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
2.3.2. HSI ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
2.3.3. HSO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
2.3.4. Serial Port ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
2.3.5. A to D Converter ÀÀÀÀÀÀÀÀÀÀÀÀ 16
2.3.6. PWM Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
3.0 BASIC SOFTWARE EXAMPLES ÀÀÀÀÀÀ 19
3.1. Using the 8096’s Processing
Section ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19
3.1.1. Table Interpolation ÀÀÀÀÀÀÀÀÀÀ 19
3.1.2. PL/M-96 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
3.2. Using the I/O Section ÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
3.2.1. Using the HSI Unit ÀÀÀÀÀÀÀÀÀÀ 24
3.2.2. Using the HSO Unit ÀÀÀÀÀÀÀÀÀ 25
3.2.3. Using the Serial Port in
Mode 1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29
3.2.4. Using the A to D ÀÀÀÀÀÀÀÀÀÀÀÀ 31
4.0 ADVANCED SOFTWARE
EXAMPLES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31
4.1. Simultaneous I/O Routines under
Interrupt Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31
4.2. Software Serial Port Using the
HSIO Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34
4.3. Interfacing an Optical Encoder to
the HSI Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
5.0 HARDWARE EXAMPLE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51
5.1. EPROM Only Minimum
System ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51
5.2. Port Reconstruction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53
6.0 CONCLUSION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 54
7.0 BIBLIOGRAPHY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 54
CONTENTS PAGE CONTENTS PAGE

APPENDICES
A.6. PWM Using the HSO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-15
Appendix A. Basic Software
Examples ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-1 A.7. Serial Port ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-19
A.1. Table Lookup 1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-1 A.8. A to D Converter ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-21
A.2. Table Lookup 2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-3 Appendix B. HSO and A to D Under
A.3. PLM-96 Code with Expansion ÀÀÀÀÀÀÀÀ A-5 Interrupt Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ B-1
A.4. Pulse Measurement ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-11
Appendix C. Software Serial Port ÀÀÀÀÀÀ C-1
A.5. Enchanced Pulse Measurement ÀÀÀÀ A-13
Appendix D. Motor Control Program ÀÀÀ D-1
Figures Listings
2-1. 8096 Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1 3-1. Include File DEMO96.INC ÀÀÀÀÀÀÀÀÀÀÀ 19
2-2. Memory Map ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2 3-2. ASM-96 Code for Table Lookup
2-3. SFR Layout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3 Routine 1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20
2-4. Major I/O Functions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 3-3. ASM-96 Code for Table Lookup
Routine 1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
2-5. Instruction Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
3-4. PLM-96 Code for Table Lookup
2-6. Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Routine 1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
2-7. Interrupt Sources ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 3-5. 32-Bit Result Multiply Procedure for
2-8. Interrupt Vectors and Priorities ÀÀÀÀÀÀÀ 8 PLM-96 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
2-9. Interrupt Structure Block 3-6. Measuring Pulses Using the HSI
Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
2-10. The PSW Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10 3-7. Enhanced HSI Pulse Measurement
Routine ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
2-11. HSI Unit Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
3-8. Generating a PWM with the HSO ÀÀÀÀ 26
2-12. HSI Mode Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
3-9. Changes to Declarations for HSO
2-13. HSO Command Register ÀÀÀÀÀÀÀÀÀÀÀÀ 12 Routine ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
2-14. HSO Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12 3-10. Driver Module for HSO PWM
2-15. Serial Port Control/Status Program ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13 3-11. Using the Serial Port in Mode 1 ÀÀÀÀÀÀ 29
2-16. Baud Rate Formulas ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 3-12. Scanning the A to D Channels ÀÀÀÀÀÀÀ 31
2-17. Baud Rate Values for 10, 11, 12 4-1. Using Multiple I/O Devices ÀÀÀÀÀÀÀÀÀÀ 32
MHz ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
4-2. Software Serial Port
2-18. Multiprocessor Communication ÀÀÀÀÀÀ 16 Declarations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35
2-19. A to D Result/Command 4-3. Software Serial Port Interface
Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17 Routines ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
2-20. PWM Output Waveforms ÀÀÀÀÀÀÀÀÀÀÀÀ 18 4-4. Software Serial Port Initialization
2-21. PWM to Analog Conversion Routine ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
Circuitry ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 4-5. Software Serial Port Transmit
3-1. Using the HSIO to Monitor Rotating Process ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
Machinery ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28 4-6. Receive Process ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
3-2. Serial Port Level Conversion ÀÀÀÀÀÀÀÀ 30 4-7. Motor Control HSO.0 Timer
4-1. 10-Bit Asynchronous Frame ÀÀÀÀÀÀÀÀÀ 35 Routine ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
4-2. Optical Encoder and Waveforms ÀÀÀÀ 39 4-8. Motor Control HSI Data Available
Routine ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
4-3. Filtered Encoder Waveforms ÀÀÀÀÀÀÀÀ 40
4-9. Motor Control Mode 1 Routines ÀÀÀÀÀ 45
4-4. Schematic of Optical Encoder to
8096 Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 4-10. Motor Control Mode 0 Routines ÀÀÀÀÀ 46
4-5. Motor Driver Circuitry ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 4-11. Motor Control Software Timer 1
Routine ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 47
4-6. Mode State Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
4-12. Motor Control Next Position
4-7. Motor Control Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49 Lookup ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49
5-1. Minimum System Configuration ÀÀÀÀÀ 52 4-13. Motor Control Timer Interrupt
Routine ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50
4-14. Motor Control Software Timer
Interrupt Handler ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50
4-15. Motor Control Software Timer 2
Routine ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51
 AP-248

1.0 INTRODUCTION 2.0 8096 OVERVIEW

High speed digital signals are frequently encountered in
modern control applications. In addition, there is often 2.1. General Description
a requirement for high speed 16-bit and 32-bit precision
in calculations. The MCSÉ-96 product line, generically Unlike microprocessors, microcontrollers are generally
referred to as the 8096, is designed to be used in appli- optimized for specific applications. Intel’s 8048 was op-
cations which require high speed calculations and fast timized for general control tasks while the 8051 was
I/O operations. optimized for 8-bit math and single bit boolean opera-
tions. The 8096 has been designed for high speed/high
The 8096 is a 16-bit microcontroller with dedicated performance control applications. Because it has been
I/O subsystems and a complete set of 16-bit arithmetic designed for these applications the 8096 architecture is
instructions including multiply and divide operations. different from that of the 8048 or 8051.
This Ap-note will briefly describe the 8096 in section 2,
and then give short examples of how to use each of its There are two major sections of the 8096; the CPU
key features in section 3. The concluding sections fea- section and the I/O section. Each of these sections can
ture a few examples which make use of several chip be subdivided into functional blocks as shown in Figure
features simultaneously and some hardware connection 2-1.
suggestions. Further information on the 8096 and its
use is available from the sources listed in the bibliogra-
phy.

270061 – 1

Figure 2-1. 8096 Block Diagram

1
AP-248

2.1.1. CPU SECTION In the lower 24 bytes of the register file are the register-
mapped I/O control locations, also called Special
The CPU of the 8096 uses a 16-bit ALU which operates Function Registers or SFRs. These registers are used to
on a 256-byte register file instead of an accumulator. control the on-chip I/O features. The remaining 232
Any of the locations in the register file can be used for bytes are general purpose RAM, the upper 16 of which
sources or destinations for most of the instructions. can be kept alive using a low current power-down
This is called a register to register architecture. Many mode.
of the instructions can also use bytes or words from
anywhere in the 64K byte address space as operands. A
memory map is shown in Figure 2-2.

270061 – 2

Figure 2-2. Memory Map

2
 AP-248

Figure 2-3 shows the layout of the register mapped to. More information about the use of these registers is
I/O. Some of these registers serve two functions, one if included in the description of the features which they
they are read from and another if they are written control.

270061 – 3

Figure 2-3: SFR Layout

3
AP-248

2.1.2. I/O FEATURES A symmetric set of byte and word operations make up
the majority of the 8096 instruction set. The assembly
Many of the I/O features on the 8096 are designed to language for the 8096 (ASM-96) uses a ‘‘B’’ suffix on a
operate with little CPU intervention. A list of the major mnemonic to indicate a byte operation, without this
I/O functions is shown in Figure 2-4. The Watchdog suffix a word operation is indicated. Many of these op-
Timer is an internal timer which can be used to reset erations can have one, two or three operands. An exam-
the system if the software fails to operate properly. The ple of a one operand instruction would be:
Pulse-Width-Modulation (PWM) output can be used as
a rough D to A, a motor driver, or for many other NOT Value1 ; Value1 : e 1’s complement (Value1)
purposes. The A to D converter (ADC) has 8 multi-
plexed inputs and 10-bit resolution. The serial port has A two operand instruction would have the form:
several modes and its own baud rate generator. The
High Speed I/O section includes a 16-bit timer, a 16-bit ADD Value2,Value1 ; Value2 : e Value2 a Value1
counter, a 4-input programmable edge detector, 4 soft-
ware timers, and a 6-output programmable event gener- A three operand instruction might look like:
ator. All of these features will be described in section
2.3. MUL Value3,Value2,Value1 ;
Value3 : e Value2* Value1

The three operand instructions combined with the reg-

2.2. The Processor Section ister to register architecture almost eliminate the neces-
sity of using temporary registers. This results in a faster
2.2.1. OPERATIONS AND ADDRESSING MODES processing time than machines that have equivalent in-
struction execution times, but use a standard architec-
The 8096 has 100 instructions, some of which operate ture.
on bits, some on bytes, some on words and some on
longs (double words). All of the standard logical and Long (32-bit) operations include shifts, normalize, and
arithmetic functions are available for both byte and multiply and divide. The word divide is a 32-bit by 16-
word operations. Bit operations and long operations are bit operation with a 16-bit quotient and 16-bit remain-
provided for some instructions. There are also flag ma- der. The word multiply is a word by word multiply
nipulation instructions as well as jump and call instruc- with a long result. Both of these operations can be done
tions. A full set of conditional jumps has been included in either the signed or unsigned mode. The direct un-
to speed up testing for various conditions. signed modes of these instructions take only 6.5 micro-
seconds. A normalize instruction and sticky bit flag
Bit operations are provided by the Jump Bit and Jump have been included in the instruction set to provide
Not Bit instructions, as well as by immediate masking hardware support for the software floating point pack-
of bytes. These bit operations can be performed on any age (FPAL-96).
of the bytes in the register file or on any of the special
function registers. The fast bit manipulation of the
SFRs can provide rapid I/O operations.

Major I/O Functions

High Speed Input Unit Provides Automatic Recording of Events
High Speed Output Unit Provides Automatic Triggering of Events and Real-Time Interrupts
Pulse Width Modulation Output to Drive Motors or Analog Circuits
A to D Converter Provides Analog Input
Watchdog Timer Resets 8096 if a Malfunction Occurs
Serial Port Provides Synchronous or Asynchronous Link
Standard I/O Lines Provide Interface to the External World when other Special Features
are not needed
Figure 2-4. Major I/O Functions

4
 AP-248

Oper- Flags
Mnemonic Operation (Note 1) Notes
ands Z N C V VT ST
ADD/ADDB 2 D wDaA & & & & u Ð
ADD/ADDB 3 D wBaA & & & & u Ð
ADDC/ADDCB 2 D w D a A aC v & & & u Ð
SUB/SUBB 2 DwDbA & & & & u Ð
SUB/SUBB 3 DwBbA & & & & u Ð
SUBC/SUBCB 2 DwDbAaCb1 v & & & u Ð
CMP/CMPB 2 DbA & & & & u Ð
MUL/MULU 2 D, D a 2 wD*A Ð Ð Ð Ð Ð ? 2
MUL/MULU 3 D, D a 2 w B * A Ð Ð Ð Ð Ð ? 2
MULB/MULUB 2 D, D a 1 w D * A Ð Ð Ð Ð Ð ? 3
MULB/MULUB 3 D, D a 1 w B * A Ð Ð Ð Ð Ð ? 3
DIVU 2 D w (D, D a 2)/A, D a 2 w remainder Ð Ð Ð & u Ð 2
DIVUB 2 D w (D, D a 1)/A, D a 1 w remainder Ð Ð Ð & u Ð 3
DIV 2 D w (D, D a 2)/A, D a 2 w remainder Ð Ð Ð ? u Ð 2
DIVB 2 D w (D, D a 1)/A, D a 1 w remainder Ð Ð Ð ? u Ð 3
AND/ANDB 2 D w D and A & & 0 0 Ð Ð
AND/ANDB 3 D w B and A & & 0 0 Ð Ð
OR/ORB 2 D w D or A & & 0 0 Ð Ð
XOR/XORB 2 D w D (excl. or) A & & 0 0 Ð Ð
LD/LDB 2 DwA Ð Ð Ð Ð Ð Ð
ST/STB 2 AwD Ð Ð Ð Ð Ð Ð
LDBSE 2 D w A; D a 1 w SIGN(A) Ð Ð Ð Ð Ð Ð 3, 4
LDBZE 2 D w A; D a 1 w 0 Ð Ð Ð Ð Ð Ð 3, 4
PUSH 1 SP w SP b 2; (SP) w A Ð Ð Ð Ð Ð Ð
POP 1 A w (SP); SP w SP a 2 Ð Ð Ð Ð Ð Ð
PUSHF 0 SP w SP b 2; (SP) w PSW; 0 0 0 0 0 0
PSW w 0000H Iw0
POPF 0 PSW w (SP); SP w SP a 2; I w & & & & & & &

SJMP 1 PC w PC a 11-bit offset Ð Ð Ð Ð Ð Ð 5

LJMP 1 PC w PC a 16-bit offset Ð Ð Ð Ð Ð Ð 5
BR (indirect) 1 PC w (A) Ð Ð Ð Ð Ð Ð
SCALL 1 SP w SP b 2; (SP) w PC; Ð Ð Ð Ð Ð Ð 5
PC w PC a 11-bit offset
LCALL 1 SP w SP b 2; (SP) w PC; Ð Ð Ð Ð Ð Ð 5
PC w PC a 16-bit offset
RET 0 PC w (SP); SP w SP a 2 Ð Ð Ð Ð Ð Ð
J (conditional) 1 PC w PC a 8-bit offset (if taken) Ð Ð Ð Ð Ð Ð 5
JC 1 Jump if C e 1 Ð Ð Ð Ð Ð Ð 5
JNC 1 Jump if C e 0 Ð Ð Ð Ð Ð Ð 5
JE 1 Jump if Z e 1 Ð Ð Ð Ð Ð Ð 5
Figure 2-5. Instruction Summary
NOTES:
1. If the mnemonic ends in ‘‘B’’, a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the register file; A can be
located anywhere in memory.
2. D, D a 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D, D a 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to a word.
5. Offset is a 2’s complement number.

5
AP-248

Oper- Flags
Mnemonic Operation (Note 1) Notes
ands Z N C V VT ST
JNE 1 Jump if Z e 0 Ð Ð Ð Ð Ð Ð 5
JGE 1 Jump if N e 0 Ð Ð Ð Ð Ð Ð 5
JLT 1 Jump if N e 1 Ð Ð Ð Ð Ð Ð 5
JGT 1 Jump if N e 0 and Z e 0 Ð Ð Ð Ð Ð Ð 5
JLE 1 Jump if N e 1 or Z e 1 Ð Ð Ð Ð Ð Ð 5
JH 1 Jump if C e 1 and Z e 0 Ð Ð Ð Ð Ð Ð 5
JNH 1 Jump if C e 0 or Z e 1 Ð Ð Ð Ð Ð Ð 5
JV 1 Jump if V e 1 Ð Ð Ð Ð Ð Ð 5
JNV 1 Jump if V e 0 Ð Ð Ð Ð Ð Ð 5
JVT 1 Jump if VT e 1; Clear VT Ð Ð Ð Ð 0 Ð 5
JNVT 1 Jump if VT e 0; Clear VT Ð Ð Ð Ð 0 Ð 5
JST 1 Jump if ST e 1 Ð Ð Ð Ð Ð Ð 5
JNST 1 Jump if ST e 0 Ð Ð Ð Ð Ð Ð 5
JBS 3 Jump if Specified Bit e 1 Ð Ð Ð Ð Ð Ð 5, 6
JBC 3 Jump if Specified Bit e 0 Ð Ð Ð Ð Ð Ð 5, 6
DJNZ 1 D w D b 1; if D i 0 then
PC w PC a 8-bit offset Ð Ð Ð Ð Ð Ð 5
DEC/DECB 1 D wDb1 & & & & u Ð
NEG/NEGB 1 Dw0bD & & & & u Ð
INC/INCB 1 DwDa1 & & & & u Ð
EXT 1 D w D; D a 2 w Sign (D) & & 0 0 Ð Ð 2
EXTB 1 D w D; D a 1 w Sign (D) & & 0 0 Ð Ð 3
NOT/NOTB 1 D w Logical Not (D) & & 0 0 Ð Ð
CLR/CLRB 1 Dw0 1 0 0 0 Ð Ð
SHL/SHLB/SHLL 2 C w msb Ð Ð Ð Ð Ð Isb w 0 & ? & & u Ð 7
SHR/SHRB/SHRL 2 0 x msb Ð Ð Ð Ð Ð Isb x C & ? & 0 Ð & 7
SHRA/SHRAB/SHRAL 2 msb x msb Ð Ð Ð Ð Ð Isb x C & & & 0 Ð & 7
SETC 0 Cw1 Ð Ð 1 Ð Ð Ð
CLRC 0 Cw0 Ð Ð 0 Ð Ð Ð
CLRVT 0 VT w 0 Ð Ð Ð Ð 0 Ð
RST 0 PC w 2080H 0 0 0 0 0 0 8
DI 0 Disable All Interrupts (I w 0) Ð Ð Ð Ð Ð Ð
EI 0 Enable All Interrupts (I w 1) Ð Ð Ð Ð Ð Ð
NOP 0 PC w PC a 1 Ð Ð Ð Ð Ð Ð
SKIP 0 PC w PC a 2 Ð Ð Ð Ð Ð Ð
NORML 2 Left Shift Till msb e 1; D w shift count & ? 0 Ð Ð Ð 7
TRAP 0 SP w SP b 2; (SP) w PC
PC w (2010H) Ð Ð Ð Ð Ð Ð 9
Figure 2-5. Instruction Summary (Continued)
NOTES:
1. If the mnemonic ends in ‘‘B’’, a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the register file; A can be
located anywhere in memory.
5. Offset is a 2’s complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The ‘‘L’’ (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.

6
 AP-248

One operand of most of the instructions can be used mode. In this mode a 16-bit 2’s complement value is
with any one of six addressing modes. These modes added to the contents of a word register to form the
increase the flexibility and overall execution speed of address of the operand. By using the zero register as the
the 8096. The addressing modes are: register-direct, im- index, ASM96 (the assembler) can accept ‘‘direct’’ ad-
mediate, indirect, indirect with auto-increment, and dressing to any location. The zero register is located at
long and short indexed. 0000H and always has a value of zero. A short indexed
mode is also available to save some time and code. This
The fastest instruction execution is gained by using ei- mode uses an 8-bit 2’s complement number as the offset
ther register direct or immediate addressing. Register- instead of a 16-bit number.
direct addressing is similar to normal direct addressing,
except that only addresses in the register file or SFRs
can be addressed. The indexed mode is used to directly 2.2.2. ASSEMBLY LANGUAGE
address the remainder of the 64K address space. Imme-
The multiple addressing modes of the 8096 make it easy
diate addressing operates as would be expected, using
to program in assembly language and provide an excel-
the data following the opcode as the operand.
lent interface to high level languages. The instructions
accepted by the assembler consist of mnemonics fol-
Both of the indirect addressing modes use the value in a
lowed by either addresses or data. A list of the mne-
word register as the address of the operand. If the indi-
monics and their functions are shown in Figure 2-5.
rect auto-increment mode is used then the word register
The addresses or data are given in different formats
is incremented by one after a byte access or by two after
depending on the addressing mode. These modes and
a word access. This mode is particularly useful for ac- formats are shown in Figure 2-6.
cessing lookup tables.
Additional information on 8096 assembly language is
Access to any of the locations in the 64K address space
available in the MCS-96 Macro Assembler Users
can be obtained by using the long indexed addressing Guide, listed in the bibliography.

270061 – B3

Figure 2-6. Instruction Format

7
AP-248

270061 – 4

Figure 2-7. Interrupt Sources

2.2.3. INTERRUPTS Vector

Location
The flexibility of the instruction set is carried through Source Priority
into the interrupt system. There are 20 different inter- (High (Low
rupt sources that can be used on the 8096. The 20 Byte) Byte)
sources vector through 8 locations or interrupt vectors. Software 2011H 2010H Not Applicable
The vector names and their sources are shown in Fig- Extint 200FH 200EH 7 (Highest)
ure 2-7, with their locations listed in Figure 2-8. Con- Serial Port 200DH 200CH 6
trol of the interrupts is handled through the Interrupt Software Timers 200BH 200AH 5
Pending Register (INTÐPENDING), the Interrupt HSI.0 2009H 2008H 4
Mask Register (INTÐMASK), and the I bit in the High Speed 2007H 2006H 3
PSW (PSW.9). Figure 2-9 shows a block diagram of the Outputs
interrupt structure. The INTÐPENDING register HSI Data 2005H 2004H 2
contains bits which get set by hardware when an inter- Available
rupt occurs. If the interrupt mask register bit for that A/D Conversion 2003H 2002H 1
source is a 1 and PSW.9 e 1, a vector will be taken to Complete
the address listed in the interrupt vector table for that Timer Overflow 2001H 2000H 0 (Lowest)
Figure 2-8. Interrupt Vectors and Priorities

8
 AP-248

source. When the vector is taken the INTÐPENDING The software can make the hardware interrupts work in
bit is cleared. If more than one bit is set in the INTÐ almost any fashion desired by having each routine run
PENDING register with the corresponding bit set in with its own setup in the INTÐMASK register. This
the INTÐMASK register, the Interrupt with the high- will be clearly seen in the examples in section 4 which
est priority shown in Figure 2-8 will be executed. change the priority of the vectors in software. The

270061 – 5

Figure 2-9. Interrupt Structure Block Diagram

9
AP-248

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Z N V VT C Ð I ST INTÐMASK
WHERE:
Z is the zero flag. It is set when the result of an operation is zero.
N is the negative flag. It is set to the algebraically correct sign of the result regardless of overflows.
V is the overflow flag. It is set if an overflow occurs.
VT is the overflow trap flag. It is set when the VT flag is set and cleared by JVT, JNVT, or CLRVT.
C is the carry flag. It is set if a carry was generated by the prior operation.
I is the global interrupt enable bit.
ST is the sticky bit. It is set during a right shift if a one was shifted into and then out of the carry flag.
INTÐMASK is the interrupt mask register and contains bits which individually enable the 8 interrupt vectors.

Figure 2-10. The PSW Register

PSW (shown in Figure 2-10), stores the INTÐMASK struction is executed to restore the old PSW. The RET
register in its lower byte so that the mask register can instruction is executed and the code returns to the de-
be pushed and popped along with the machine status sired location. Although the POPF instruction can en-
when moving in and out of routines. The action of able the interrupts the next instruction will always exe-
pushing flags clears the PSW which includes PSW.9, cute. This prevents unnecessary building of the stack by
the interrupt enable bit. Therefore, after a PUSHF in- ensuring that the RET always executes before another
struction interrupts are disabled. In most cases an inter- interrupt vector is taken.
rupt service routine will have the basic structure shown
below.
2.3. On-Chip I/O Section
INT VECTOR:
All of the on-chip I/O features of the 8096 can be ac-
PUSHF cessed through the special function registers, as shown
LDB INT MASK, #xxxxxxxxB in Figure 2-3. The advantage of using register-mapped
EI I/O is that these registers can be used as the sources or
- destinations of CPU operations. There are seven major
- ;Insert service routine here I/O functions. Each one of these will be considered
- with a section of code to exemplify its usage. The first
POPF section covered will be the High Speed I/O, (HSIO),
RET subsystem. This section includes the High Speed Input
(HSI) unit, High Speed Output (HSO) unit, and the
The PUSHF instruction saves the PSW including the Timer/Counter section.
old INTÐMASK register. The PSW, including the in-
terrupt enable bit are left cleared. If some interrupts
2.3.1. TIMER/COUNTERS
need to be enabled while the service routine runs, the
INTÐMASK is loaded with a new value and inter- The 8096 has two time bases, Timer 1 and Timer 2.
rupts are globally enabled before the service routine Timer 1 is a 16-bit free running timer which is incre-
continues. At the end of the service routine a POPF in- mented every 8 state times. (A state time is 3 oscillator
periods, or 0.25 microseconds with a 12 MHz crystal.)

10
 AP-248

270061 – 6
# Pulse measurement with 2.0 msec resolution
# Input transitions trigger the recording of the reference
Timer (16-bit) and triggered input(s) (4-bit)

Figure 2-11. HSI Unit Block Diagram

Its value can be read at any time and used as a refer- 2.3.2. HSI
ence for both the HSI section and the HSO section.
Timer 1 can cause an interrupt when it overflows, and The HSI unit can be thought of as a message taker
cannot be modified or stopped without resetting the which records the line which had an event and the time
entire chip. Timer 2 is really an event counter since it at which the event occurred. Four types of events can
uses an external clock source. Like Timer 1, it is 16-bits trigger the HSI unit, as shown in the HSI block dia-
wide, can be read at any time, can be used with the gram in Figure 2-11. The HSI unit can measure pulse
HSO section, and can generate an interrupt when it widths and record times of events with a 2
overflows. Control of Timer 2 is limited to increment-
ing it and resetting it. Specific values can not be written
to it.

Although the 8096 has only two timers, the timer flexi-
bility is equal to a unit with many timers thanks to the
HSIO unit. The HSI enables one to measure times of
external events on up to four lines using Timer 1 as a
timer base. The HSO unit can schedule and execute
internal events and up to six external events based on 270061 – 7
the values in either Timer 1 or Timer 2. The 8096 also Where each 2-bit mode control field
includes separate, dedicated timers for the baud rate defines one of 4 possible modes:
generator and watchdog timer. 00 8 positive transitions
01 Each positive transition
10 Each negative transition
11 Every transition (positive and negative)

Figure 2-12. HSI Mode Register

11
AP-248

microsecond resolution. It can look for one of four holding register is loaded or when the FIFO has six or
events on each of four lines simultaneously, based on more entries.
the information in the HSI Mode register, shown in
Figure 2-12. The information is then stored in a seven
level FIFO for later retrieval. Whenever the FIFO con- 2.3.3. HSO
tains information, the earliest entry is placed in the
Just as the HSI can be thought of as a message taker,
holding register. When the holding register is read, the
the HSO can be thought of as a message sender. At
next valid piece of information is loaded into it. Inter-
times determined by the software, the HSO sends mes-
rupts can be generated by the HSI unit at the time the

270061 – 8

Figure 2-13. HSO Command Register

270061 – 9

Figure 2-14. HSO Block Diagram

12
 AP-248

sages to various devices to have them turn on, turn off, A CAM (Content Addressable Memory) file is the
start processing, or reset. Since the programmed times main component of the HSO. This file stores up to
can be referenced to either Timer 1 or Timer 2, the eight events which are pending to occur. Every state
HSO makes the two timers look like many. For exam- time one location of the CAM is compared with the
ple, if several events have to occur at specific times, the two timers. After 8 state times, (two microseconds with
HSO unit can schedule all of the events based on a a 12 MHz clock), the entire CAM has been searched
single timer. The events that can be scheduled to occur for time matches. If a match occurs the specified event
and the format of the command written to the HSO will be triggered and that location of the CAM will be
Command register are shown in Figure 2-13. made available for another pending event. A block dia-
gram of the HSO unit is shown in Figure 2-14.
The software timers listed in the figure are actually 4
software flags in I/O Status Register 1 (IOS1). These
flags can be set, and optionally cause an interrupt, at 2.3.4. Serial Port
any time based on Timer 1 or Timer 2. In most cases
Controlling a device from a remote location is a simple
these timers are used to trigger interrupt routines which
task that frequently requires additional hardware with
must occur at regular intervals. A multitask process
many processors. The 8096 has an on-chip serial port to
can easily be set up using the software timers.
reduce the total number of chips required in the system.

270061 – 10

NOTE:
TI and RI are cleared when SPÐCON is read.

Figure 2-15. Serial Port Control/Status Register

13
AP-248

The serial port is similar to that on the MCS-51 prod- Baud rates for all of the modes are controlled through
uct line. It has one synchronous and three asynchro- the Baud Rate register. This is a byte wide register
nous modes. In the asynchronous modes baud rates of which is loaded sequentially with two bytes, and inter-
up to 187.5 Kbaud can be used, while in the synchro- nally stores the value as a word. The least significant
nous mode rates up to 1.5 Mbaud are available. The byte is loaded to the register followed by the most sig-
chip has a baud rate generator which is independent of nificant. The most significant bit of the baud value de-
Timer 1 and Timer 2, so using the serial port does not termines the clock source for the baud rate generator. If
take away any of the HSI, HSO or timer flexibility or the bit is a one, the XTAL1 pin is used as the source, if
functionality. it is a zero, the T2 CLK pin is used. The formulas
shown in Figure 2-16 can be used to calculate the baud
Control of the serial port is provided through the rates. The variable ‘‘B’’ is used to represent the least
SPCON/SPSTAT (Serial Port CONtrol/Serial Port significant 15 bits of the value loaded into the baud rate
STATus) register. This register, shown in Figure 2-15, register.
has some bits which are read only and others which are
write only. Although the functionality of the port is The baud rate register values for common baud rates
similar to that of the 8051, the names of some of the are shown in Figure 2-17. These values can be used
modes and control bits are different. The way in which when XTAL1 is selected as the clock source for serial
the port is used from a software standpoint is also modes other than Mode 0. The percentage deviation
slightly different since RI and TI are cleared after each from theoretical is listed to help assess the reliability of
read of the register. a given setup. In most cases a serial link will work if
there is less than a 2.5% difference between the baud
The four modes of the serial port are referred to as rates of the two systems. This is based on the assump-
modes 0, 1, 2 and 3. Mode 0 is the synchronous mode, tion that 10 bits are transmitted per frame and the last
and is commonly used to interface to shift registers for bit of the frame must be valid for at least six-eights of
I/O expansion. In this mode the port outputs a pulse the bit time. If the two systems deviate from theoretical
train on the TXD pin and either transmits or receives by 1.25% in opposite directions the maximum toler-
data on the RXD pin. Mode 1 is the standard asyn- ance of 2.5% will be reached. Therefore, caution must
chronous mode, 8 bits plus a stop and start bit are sent be used when the baud rate deviation approaches
or received. Modes 2 and 3 handle 9 bits plus a stop and 1.25% from theoretical. Note that an XTAL1 frequen-
start bit. The difference between the two is, that in cy of 11.0592 MHz can be used with the table values
Mode 2 the serial port interrupt will not be activated for 11 MHz to provide baud rates that have 0.0 percent
unless the ninth data bit is a one; in Mode 3 the inter- deviation from theoretical. In most applications, how-
rupt is activated whenever a byte is received. These two ever, the accuracy available when using an 11 MHz
modes are commonly used for interprocessor communi- input frequency is sufficient.
cation.
Serial port Mode 1 is the easiest mode to use as there is
little to worry about except initialization and loading
Using XTAL1:
and unloading SBUF, the Serial port BUFfer. If parity
XTAL1 frequency
Mode 0: Baud e ;B i 0 is enabled, (i.e., PEN e 1), 7 bits plus even parity are
Rate 4*(B a 1)
used instead of 8 data bits. The parity calculation is
Baud XTAL1 frequency done in hardware for even parity. Modes 2 and 3 are
Others: Rate e
64*(B a 1) similar to Mode 1, except that the ninth bit needs to be
Using T2CLK: controlled and read. It is also not possible to enable
T2CLK frequency parity in Mode 2. When parity is enabled in Mode 3 the
Mode 0: Baud
Rate
e ;B i 0 ninth bit becomes the parity bit. If parity is not enabled,
B
(i.e., PEN e 0), the TB8 bit controls the state of the
T2CLK frequency
Others: Baud
Rate
e ;B i 0 ninth transmitted bit. This bit must be set prior to each
16*B transmission. On reception, if PEN e 0, the RB8 bit
Note that B cannot equal 0, except when using indicates the state of the ninth received bit. If parity is
XTAL1 in other than mode 0. enabled, (i.e., PEN e 1), the same bit is called RPE
Figure 2-16. Baud Rate Formulas (Receive Parity Error), and is used to indicate a parity
error.

14
 AP-248

XTAL1 Frequency e 12.0 MHz

Baud Rate Baud Register Value Percent Error
19.2K 8009H a 2.40
9600 8013H a 2.40
4800 8026H b 0.16
2400 804DH b 0.16
1200 809BH b 0.16
300 8270H 0.00
XTAL1 Frequency e 11.0 MHz
19.2K 8008H a 0.54
9600 8011H a 0.54
4800 8023H a 0.54
2400 8047H a 0.54
1200 808EH b 0.16
300 823CH a 0.01
XTAL1 Frequency e 10.0 MHz
19.2K 8007H b 1.70
9600 800FH b 1.70
4800 8020H a 1.38
2400 8040H b 0.16
1200 8081H b 0.16
300 8208H a 0.03
Figure 2-17. Baud Rate Values for 10, 11, 12 MHz

The software used to communicate between processors receive the message switches to Mode 3 and receives
is simplified by making use of Modes 2 and 3. In a basic the information. Since this information is sent with the
protocol the ninth bit is called the address bit. If it is set ninth bit set to zero, none of the processors set to Mode
high then the information in that byte is either the ad- 2 will be interrupted. By using this scheme the overall
dress of one of the processors on the link, or a com- CPU time required for the serial port is minimized.
mand for all the processors. If the bit is a zero, the byte
contains information for the processor or processors A typical connection diagram for the multi-processor
previously addressed. In standby mode all processors mode is shown in Figure 2-18. This type of communica-
wait in Mode 2 for a byte with the address bit set. ton can be used to connect peripherals to a desk top
When they receive that byte, the software determines if computer, the axis of a multi-axis machine, or any oth-
the next message is for them. The processor that is to er group of microcontrollers jointly performing a task.

15
AP-248

270061 – 11

Figure 2-18. Multiprocessor Communication

Mode 0, the synchronous mode, is typically used for input. When doing process control algorithms, it is fre-
interfacing to shift registers for I/O expansion. The quently the changes in inputs that are required, not the
software to control this mode involves the REN (Re- absolute accuracy of the value. For this reason, even if
ceiver ENable) bit, the clearing of the RI bit, and writ- the absolute accuracy of a 10-bit converter is the same
ing to SBUF. To transmit to a shift register, REN is set as that of an 8-bit converter, the 10-bit monotonic con-
to zero and SBUF is loaded with the information. The verter is much more useful.
information will be sent and then the TI flag will be set.
There are two ways to cause a reception to begin. The Since most of the analog inputs which are monitored by
first is by causing a rising edge to occur on the REN a microcontroller change very slowly relative to the 42
bit, the second is by clearing RI with REN e 1. In microsecond conversion time, it is acceptable to use a
either case, RI is set again when the received byte is capacitive filter on each input instead of a sample and
available in SBUF. hold. The 8097 does not have an internal sample and
hold, so it is necessary to ensure that the input signal
does not change during the conversion time. The input
2.3.5. A to D CONVERTER to the A/D must be between ANGND and VREF.
ANGND must be within a few millivolts of VSS and
Analog inputs are frequently required in a microcon-
troller application. The 8097 has a 10-bit A to D con- VREF must be within a few tenths of a volt of VCC.
verter that can use any one of eight input channels. The
conversions are done using the successive approxima- Using the A to D converter on the 8097 can be a very
low software overhead task because of the interrupt and
tion method, and require 168 state times (42 microsec-
HSO unit structure. The A to D can be started by the
onds with a 12 MHz clock.)
HSO unit at a preset time. When the conversion is com-
The results are guaranteed monotonic by design of the plete it is possible to generate an interrupt. By using
these features the A to D can be run under complete
converter. This means that if the analog input voltage
interrupt control. The A to D can also be directly
changes, even slightly, the digital value will either stay
the same or change in the same direction as the analog

16
 AP-248

A/D Command Register

270061 – 12

A/D Result Register

270061 – 13

Figure 2-19. A to D Result/Command Register

controlled by software flags which are located in the takes up much less silicon area than a true D to A. The
ADÐRESULT/ADÐCOMMAND Register, shown signal is a variable duty cycle, fixed frequency wave-
in Figure 2-19. form that can be integrated to provide an approxima-
tion to an analog output. The frequency is fixed at a
period of 64 microseconds for a 12 MHz clock speed.
2.3.6. PWM REGISTER Controlling the PWM simply requires writing the de-
Analog outputs are just as important as analog inputs sired duty cycle value (an 8-bit value) to the PWM
Register. Some typical output waveforms that can be
when connecting to a piece of equipment. True digital
to analog converters are difficult to make on a micro- generated are shown in Figure 2-20.
processor because of all of the digital noise and the
necessity of providing an on chip, relatively high cur- Converting the PWM signal to an analog signal varies
in difficulty, depending upon the requirements of the
rent, rail to rail driver. They also take up a fair amount
system. Some systems, such as motors or switching
of silicon area which can be better used for other fea-
power supplies actually require a PWM signal, not a
tures. The A to D converter does use a D to A, but the
true analog one. For many other cases it is necessary
currents involved are very small.
only to amplify the signal so that it switches rail-to-rail,
and then filter it. Switching rail-to-rail means that the
For many applications an analog output signal can be
output of the amplifier will be a reference value when
replaced by a Pulse Width Modulated (PWM) signal.
the input is a logical one, and the output will
This signal can be easily generated in hardware, and

17
AP-248

be zero when the input is a logical zero. The filter can The RC network determines how quiet the output is,
be a simple RC network or an active filter. If a large but the quieter the output, the slower it can change.
amount of current is needed a buffer is also required. The design of high accuracy voltage followers and ac-
For low output currents, (less than 100 microamps or tive filters is beyond the scope of this paper, however
so), the circuit shown in Figure 2-21 can be used. many books on the subject are available.

270061 – 14

Figure 2-20. PWM Output Waveforms

270061 – 15
*This resistor limits Rise Time to reduce spikes and high frequency noise.

Figure 2-21. PWM to Analog Conversion Circuitry

18
 AP-248

3.0 BASIC SOFTWARE EXAMPLES els in this file are different from those in the file
8096.INC that is provided in the ASM-96 package.
The examples in this section show how to use each I/O
feature individually. Examples of using more than one
feature at a time are described in section 4. All of the 3.1. Using the 8096’s Processing
examples in this ap-note are set up to be used as listed. Section
If run through ASM96 they will load and run on an
SBE-96. In order to insure that the programs work, the
stack pointer is initialized at the beginning of each pro- 3.1.1. TABLE INTERPOLATION
gram. If the programs are going to be used as modules A good way of increasing speed for many processing
of other programs, the stack pointer initialization tasks is to use table lookup with interpolation. This can
should only be used at the beginning of the main pro- eliminate lengthy calculations in many algorithms. Fre-
gram. quently it is used in programs that generate sine wave-
forms, use exponents in calculations, or require some
To avoid repetitive declarations the ‘‘include’’ file ‘‘DE- non-linear function of a given input variable. Table
MO96.INC’’, shown in Listing 3-1, is used. ASM-96 lookup can also be used without interpolation to deter-
will insert this file into the code file whenever the direc- mine the output state of I/O devices for a given state of
tive ‘‘INCLUDE DEMO96.INC’’ is used. The file con- a set of input devices. The procedure is also a good
tains the definitions for the SFRs and other variables. example of 8096 code as it uses many of the software
The include statement has been placed in all of the ex- features. Two ways of making a lookup table are de-
amples. It should be noted that some of the lab- scribed, one way uses more calculation time, the second
way uses more table space.

270061 – 16

Listing 3-1. Include File DEMO.96.INC

19
AP-248

In both methods the procedure is similar. Values of a To make the algorithm easier, (and therefore faster), it
function are stored in memory for specific input values. is appropriate to limit the range and accuracy of the
To compute the output function for an input that is not function to only what is needed. It is also advantageous
listed, a linear approximation is made based on the to make the input step (Upper Input-Lower Input)
nearest inputs and nearest outputs. As an example, con- equal to a power of 2. This allows the substitution of
sider the table below. multiple right shifts for a divide operation, thus speed-
ing up throughput. The 8096 allows multiple arithmetic
If the input value was one of those listed then there right shifts with a single instruction providing a very
would be no problem. Unfortunately the real world is fast divide if the divisor is a power of two.
never so kind. The input number will probably be 259
or something similar. If this is the case linear interpola- For the purpose of an example, a program with a 12-bit
tion would provide a reasonable result. The formula is: output and an 8-bit input has been written. An input
step of 16 (2**4) was selected. To cover the input range
UpperOutput-Lower Output
Delta Out e *(Actual Input-Lower Input) 17 words are needed, 255/16 a 1 word to handle val-
Upper Input-Lower Input
ues in the last 15 bytes of input range. Although only
Actual Output e Lower Output a Delta Out
12 bits are required for the output, the 16-bit architec-
For the value of 259 the solution is:
ture offers no penalty for using 16 instead of 12 bits.
900-400 500
Delta Out e *(259-200) e *59 e 5 * 59 e 295
300-200 100 The program for this example, shown in Listing 3-2,
Actual Output e 400 a 295 e 695
uses the definitions and equates from Listing 3-1, only
the additional equates and definitions are shown in the
code.

Input Value Relative Table Address Table Value

100 0001H 100
200 0002H 400
300 0003H 900
400 0004H 1600

270061 – 17

Listing 3-2. ASM-96 Code for Table Lookup Routine 1

20
 AP-248

270061 – 18

Listing 3-2. ASM-96 Code for Table Lookup Routine 1 (Continued)

If the function is known at the time of writing the soft- lookup table. There are many applications where time
ware it is also possible to calculate in advance the is critical and code space is overly abundant. In these
change in the output function for a given change in the cases the code in Listing 3-3 will work to the same
input. This method can save a divide and a few other specifications as the previous example.
instructions at the expense of doubling the size of the

270061 – 19

Listing 3-3. ASM-96 Code For Table Lookup Routine 2

21
AP-248

270061 – 20

Listing 3-3. ASM-96 Code for Table Lookup Routine 2 (Continued)

By making use of the second lookup table, one word of lines of assembly code. This is advantageous to the pro-
RAM was saved and 16 state times. In most cases this grammer, since code can usually be written at a set
time savings would not make much of a difference, but number of lines per hour, so the less lines of code that
when pushing the processor to the limit, microseconds need to be written, the faster the task can be completed.
can make or break a design.
If the first example of interpolation is considered, the
PLM-96 code would be written as shown in Listing 3-4.
3.1.2. PL/M-96 Note that version 1.0 of PLM-96 does not support 32-
bit results of 16 by 16 multiplies, so the ASM-96 proce-
Intel provides high level language support for most of
dure ‘‘DMPY’’ is used. Procedure DMPY, shown in
its micro processors and microcontrollers in the form of
PL/M. Specifically, PL/M refers to a family of lan- Listing 3-5, must be assembled and linked with the
compiled PLM-96 program using RL-96, the relocator
guages, each similar in syntax, but specialized for the
and linker. The command line to be used is:
device for which it generates code. The PL/M syntax is
similar to PL/1, and is easy to learn. PLM-96 is the
RL96 PLMEX1.OBJ, DMPY.OBJ, PLM96.LIB &
version of PL/M used for the 8096. It is very code
to PLMOUT.OBJ ROM (2080H-3FFFH)
efficient as it was written specifically for the MCS-96
family. PLM-96 most closely resembles PLM-86, al-
though it has bit and I/O functions similar to PLM-51.
One line of PL/M-code can take the place of many

22
 AP-248

270061 – 21

Listing 3-4. PLM-96 Code For Table Lookup Routine 1

270061 – 22

Listing 3-5. 32-Bit Result Multiply Procedure For PLM-96

23
AP-248

Using PLM, code requires less lines, is much faster to Frequently it is also desired to keep track of the num-
write, and easier to maintain, but may take slightly ber of events which have occurred, as well as how often
longer to run. For this example, the assembly code gen- they are occurring. By using a software counter this
erated by the PLM-96 compiler takes 56.75 microsec- feature can be added to the above code. This code de-
onds to run instead of 30.75 microseconds. If PLM-96 pends on the software responding to the change in line
performed the 32-bit result multiply instead of using state before the line changes again. If this cannot be
the ASM-96 routine the PLM code would take 41.5 guaranteed then it may be necessary to use 2 HSI lines
microseconds to run. The actual code listings are for each incoming line. In this case one HSI line would
shown in Appendix A. look for falling edges while the other looks for rising
edges. The code in Listing 3-7 includes both the counter
feature and the edge detect feature.
3.2. Using the I/O Section
The uses for this type of routine are almost endless. In
instrumentation it can be used to determine frequency
3.2.1. USING THE HSI UNIT
on input lines, or perhaps baud rate for a self adjusting
One of the most frequent uses of the HSI is to measure serial port. Section 4.2 contains an example of making a
the time between events. This can be used for frequency software serial port using the HSI unit. Interfacing to
determination in lab instruments, or speed/acceleration some form of mechanically generated position informa-
information when connected to pulse type encoders. tion is a very frequent use of the HSI. The applications
The code in Listing 3-6 can be used to determine the in this category include motor control, precise position-
high and low times of the signals on two lines. This ing (print heads, disk drives, etc.), engine control and
code can be easily expanded to 4 lines and can also be
modified to work as an interrupt routine.

270061 – 23

Listing 3-6. Measuring Pulses Using The HSI Unit

24
 AP-248

transmission control. The HSI unit is used extensively HSO line not change so quickly that it changes twice
in the example in section 4.3. between consecutive reads of I/O Status Register 0,
(IOS0).
3.2.2. USING THE HSO UNIT A very eye catching example can be made by having the
program output waveforms that vary over time. The
Although the HSO has many uses, the best example is
driver routine in Listing 3-10 can be linked to the above
that of a multiple PWM output. This program, shown
program to provide this function. Linking is accom-
in Listing 3-8, is simple enough to be easily understood,
plished using RL96, the relocatable linker for the 8096.
yet it shows how to use the HSO for a task which can
Information for using RL96 can be found in the
be complex. In order for this program to operate, an-
‘‘MCS-96 Utilities Users Guide’’, listed in the bibliogra-
other program needs to set up the on and off time vari-
phy. In order for the program to link, the register dec-
ables for each line. The program also requires that a

270061 – 24

Listing 3-7. Enhanced HSI Pulse Measurement Routine

25
AP-248

270061 – 25

Listing 3-8. Generating a PWM with the HSO

26
 AP-248

laration section (i.e., the section between ‘‘RSEG’’ and quency twice that of the first one. A slightly different
‘‘CSEG’’) in Listing 3-8 must be changed to that in driver routine could easily be the basis for a switching
Listing 3-9. power supply or a variable frequency/variable voltage
motor driver. The listing of the driver routine is shown
The driver routine simply changes the duty cycle of the in Listing 3-10.
waveform and sets the second HSO output to a fre-

270061 – 26

Listing 3-9. Changes to Declarations for HSO Routine

270061 – 27

Listing 3-10. Driver Module for HSO PWM Program

27
AP-248

270061 – 28

Listing 3-10. Driver Module for HSO PWM Program (Continued)

Since the 8096 needs to keep track of events which of- Another option available is to use the HSI.1 pin to
ten repeat at set intervals it is convenient to be able to clock Timer 2. By using this approach it is possible to
have Timer 2 act as a programmable modulo counter. use the HSI to measure the period of events on the
There are several ways of doing this. The first is to input to Timer 2. If both of the HSI pins are used
program the HSO to reset Timer 2 when Timer 2 instead of the T2RST and T2CLK pins the HSIO unit
equals a set value. A software timer set to interrupt at can keep track of speed and position of the rotating
Timer 2 equals zero could be used to reload the CAM. device with very little software overhead. This type of
This software method takes up two locations in the setup is ideal for a system like the one shown in Figure
CAM and does not synchronize Timer 2 to the external 3-1, and similar to the one used in section 4.3.
world.
In this system a sequence of events is required based on
To synchronize Timer 2 externally the T2 RST (Timer the position of the gear which represents any piece of
2 ReSeT) pin can be used. In this way Timer 2 will get rotating machinery. Timer 2 holds the count of the
reset on each rising edge of T2 RST. If it is desired to number of tooth edges passed since the index mark. By
have an interrupt generated and time recorded when using HSI.1 as the input to Timer 2, instead of T2
Timer 2 gets reset, the signal for its reset can be taken CLK, it is possible to determine tooth count and time
from HSI.0 instead of T2RST. The HSI.0 pin has its information through the HSI. From this information
own interrupt vector which functions independently of instantaneous velocity and acceleration can be calculat-
the HSI unit. ed. Having the tooth edge count in Timer 2 means

270061 – 29

Figure 3-1. Using the HSIO to Monitor Rotating Machinery

28
 AP-248

that the HSO unit can be used to initiate the desired transmits the same character. The code is set up so that
tasks at the appropriate tooth count. The interrupt rou- minor modifications could make it run on an interrupt
tine initiated by HSI.0 can be used to perform any soft- basis. Note that it is necessary to set up some flags as
ware task required every revolution. In this system, the initial conditions to get the routine to run properly. If it
overhead which would normally require extensive soft- was desired to send 7 bits of data plus parity instead of
ware has been done with the hardware on the 8096, 8 bits of data the PEN bit would be set to a one. Inter-
thus making more software time available for control processor communication, as described in section 2.3.4,
programs. can be set up by simply adding code to change RB8 and
the port mode to the listing below. The hardware
shown in Figure 3-2 can be used to convert the logic
3.2.3. USING THE SERIAL PORT IN MODE 1 level output of the 8096 to g 12 or 15 volt levels to
Mode 1 of the serial port supports the basic asynchro- connect to a CRT. This circuit has been found to work
nous 8-bit protocol and is used to interface to most with most RS-232 devices, although it does not con-
CRTs and printers. The example in Listing 3-11 shows form to strict RS-232 specifications. If true RS-232
a simple routine which receives a character and then conformance is required then any standard RS-232
driver can be used.

270061 – 30

Listing 3-11. Using the Serial Port in Mode 1

29
AP-248

270061 – 31

Listing 3-11. Using the Serial Port in Mode 1 (Continued)

270061 – 32

Figure 3-2. Serial Port Level Conversion

30
 AP-248

3.2.4. USING THE A TO D really make use of its full capabilities. The following
examples use some of the code blocks from the previous
The code in Listing 3-12 makes use of the software flags section to show how several I/O features can be used
to implement a non-interrupt driven routine which together to accomplish a practical task. Three examples
scans A to D channels 0 through 3 and stores them as will be shown. The first is simply a combination of sev-
words in RAM. An interrupt driven routine is shown in eral of the section 3 examples run under an interrupt
section 4.1. When using the A to D it is important to system. Next, a software serial port using the HSIO
always read the value using the byte read commands, unit is described. The concluding example is one of in-
and to give the converter 8 state times to start convert- terfacing the HSI unit to an optical encoder to control a
ing before reading the status bit. motor.

Since there is no sample and hold on the A to D con-

verter it may be desirable to use an RC filter on each 4.1. Simultaneous I/O Routines under
input. A 100X resistor in series with a 0.22 uf capacitor Interrupt Control
to ground has been used successfully in the lab. This
circuit gives a time constant of around 22 microseconds A four channel analog to PWM converter can easily be
which should be long enough to get rid of most noise, made using the 8096. In the example in Listing 4 ana-
without overly slowing the A to D response time. log channels are read and 3 PWM waveforms are gen-
erated on the HSO lines and one on the PWM pin.
Each analog channel is used to set the duty cycle of its
4.0 ADVANCED SOFTWARE associated output pin. The interrupt system keeps the
EXAMPLES whole program humming, providing time for a back-
ground task which is simply a 32 bit software counter.
Using the 8096 for applications which consist only of To show which routines are executing and in which
the brief examples in the previous section does not

270061 – 33

Listing 3-12. Scanning the A to D Channels

31
AP-248

order, Port 1 output pins are used to indicate the cur- be waited between consecutive loads of the HSO. If this
rent status of each task. The actual code listing is in- is not done it is possible to overwrite the contents of the
cluded in Appendix B. CAM holding register. An A/D interrupt is forced by
setting the bit in the Interrupt Pending register. This
The initialization section, shown in Listing 4-1a, clears causes the first A/D interrupt to occur just after the
a few variables and then loads the first set of on and off Interrupt Mask register is set and interrupts are en-
times to the HSO unit. Note that 8 state times must abled.

Listing 4-1. Using Multiple I/O Devices

270061 – 34

Listing 4-1a. Initializing the A to D to PWM Program

32
 AP-248

270061 – 35

Listing 4-1a. Initializing the A to D to PWM program (Continued)

270061 – 36

Listing 4-1b. Interrupt Driven HSO Routine

33
AP-248

270061 – 37

Listing 4-1c. Interrupt Driven A to D Routine

The HSO routine shown in Listing 4-1b is slightly dif- has a ten bit output, the most significant 8 bits are
ferent than the one in section 3. All of the HSO lines rounded up or down based on the least significant two
turn on at the same time, only the turn-off-time is var- bits.
ied between lines. This action is what is most common-
ly required for multiple PWM outputs and simplifies
the software. A comparison is made between Timer1 4.2. Software Serial Port Using the
and the next HSO turn on time at the beginning of the HSIO Unit
routine. If the next turn on time has passed, then the
on-times are loaded into the CAM, otherwise the off There are many systems which require more than one
times are loaded. serial port, an example is a system which must commu-
nicate with other computers and have an additional
The maximum number of events in the CAM at any port for a local console. If the on-board UART is being
given time is 7. This occurs when the first line to turn used as an inter-processor link, the HSIO unit can be
off does so, causing the off-times for all of the lines to used to interface the 8096 to an additional asynchro-
be loaded. For two of the lines there will be an offtime, nous line.
an on-time, and the just loaded off-time. The other line
(the one that just turned off) will have only the on-time Figure 4-1 shows the format of a standard 10-bit asyn-
and the just loaded off-time. chronous frame. The start bit is used to synchronize the
receiver to the transmitter; at the leading edge of the
A/D conversions are performed by the code in Listing START bit the receiver must set up its timing logic to
4-1c about every 60 microseconds, 42 for the conver- sample the incoming line in the center of each bit. Fol-
sion, the rest for overhead. The A/D routine sets up the lowing the start bit are the eight data bits which are
HSO and PWM on and off times. Since the A/D transmitted least significant bit first. The STOP bit is
set to the opposite state of the START bit to guar-

34
 AP-248

270061 – 38

Figure 4-1. 10-bit Asynchronous Frame

antee that the leading edge of the START bit will cause 3. Transmit ISR. This routine runs as an ISR (interrupt
a transition on the line; it also provides for a dead time service routine) in response to an HSO interrupt in-
on the line so that the receiver can maintain its syn- terrupt. Its function is to serialize the data passed to
chronization. it by the interface routines.
4. Receive ISRs. There are two ISRs involved in the
The remainder of this section will show how a full-du- receive process. One of them runs in response to an
plex asynchronous port can be built from the HSIO HSI interrupt and is used to synchronize the receive
unit. There are four sections to this code: process at the leading edge of the start bit. The sec-
1. Interface routines. These routines provide a proce- ond receive ISR runs in response to an HSO generat-
dural interface between the interrupt driven core of ed software timer interrupt, this routine is scheduled
the software serial port and the remainder of the ap- to run at the center of each bit and is used to deseri-
plication software. alize the incoming data.
2. Initialization routine. This routine is called during
the initialization of the overall system and sets up the The routines share the set of variables that are shown in
various variables used by the software port. Listing 4-2. These variables should be accessed only by
the routines which make up the software serial port.

270061 – 39

Listing 4-2. Software Serial Port Declarations

35
AP-248

The table also shows the declarations for the com- stored the START and STOP bits are added to the data
mands issued to the HSO unit. In this example HSI.2 is bits. The routine charÐin is called when the applica-
used for receive data and HSO.5 is used for transmit tion software requires a character from the port. The
data, although other HSI and HSO lines could have data is returned in the ax register in conformance to
been used. PLM 96 calling conventions. The routine csts can be
called to determine if a character is available at the port
The interface routines are shown in Listing 4-3. Data is before calling charÐin. (If no character is available
passed to the port by pushing the eight-bit character charÐin will wait indefinitely).
into the stack and calling charÐout, which waits for
any in-process transmission to complete and stores the The initialization routine is shown in Listing 4-4. This
character into the variable serialÐout. As the data is routine is called with the required baud rate in the

270061 – 40

Listing 4-3. Software Serial Port Interface Routines

270061 – 41

Listing 4-4. Software Serial Port Initialization Routine

36
 AP-248

stack; it calculates the bit time from the baud rate and nificant bit is output and the register shifted right one
stores it in the variable baudÐcount in units of TIM- place. The framing information (START and STOP
ER1 ticks. An HSO command is issued which will initi- bits) are appended to the actual data by the interface
ate the transmit process and then the remainder of the routines. Note that this routine will be executed once
variables owned by the port are initialized. The routine per bit time whether or not data is being transmitted. It
initÐreceive is called to setup the HSI unit to look for would be possible to use this routine for additional low
the leading edge of the START bit. resolution timing functions with minimal overhead.

The transmit process is shown in Listing 4-5. The HSO The receive process consists of an initialization routine
unit is used to generate an output command to the and two interrupt service routines, hsiÐisr and soft-
transmit pin once per bit time. If the serialÐout regis- wareÐtimerÐisr. The listings of these routines are
ter is zero a MARK (idle condition) is output. If the shown in Listings 4-6a,4-6b, and 4-6c respectively. The
serialÐout register contains data then the least sig-

270061 – 42

Listing 4-5. Software Serial Port Transmit Process

Listing 4-6. Receive Process

270061 – 43

Listing 4-6a. Software Serial Port Receive Initialization

37
AP-248

270061 – 44

Listing 4-6b. Software Serial Port Start Bit Detect

270061 – 45

Listing 4-6c. Software Serial Port Data Reception

38
 AP-248

start is detected by the hsiÐisr which schedules a soft- Frequently there is a third line which generates one
ware timer interrupt in one-half of a bit time. This first pulse per revolution for indexing purposes. Figure 4-2
sample is used to verify that the START bit has not shows a six line encoder and typical waveforms. As can
ended prematurely (a protection against a noisy line). be seen, the two waveforms provide the ability to deter-
The software timer service routine uses the variable mine both position and direction. Since a microcontrol-
rcveÐstate to determine whether it should check for a ler can perform real time calculations it is possible to
valid START bit, deserialize data, or check for a valid determine velocity and acceleration from the position
STOP bit. When a complete character has been re- and time information.
ceived it is moved to the receive buffer and initÐreceive
is called to set up the receive process for the next char- Interfacing to the encoder can be an interesting prob-
acter. This routine is also called when an error (e.g., lem, as it requires connecting mechanically generated
invalid START bit) is detected. electrical signals to the HSI unit. The problems arise
because it is difficult to obtain the exact nature of the
Appendix C contains the complete listing of the rou- signals under all conditions.
tines and the simple loop which was used to initialize
them and verify their operation. The test was run for The equipment used in the lab was a Pittman 9400 se-
several hours at 9600 baud with no apparent malfunc- ries gearmotor with a 600 line optical encoder from
tion of the port. Vernitech. The encoder has to be carefully attached to
the shaft to minimize any runout or endplay. Fortu-
nately, Pitmann has started marketing their motors
4.3. Interfacing an Optical Encoder to with ball bearings and optical encoders already in-
the HSI Unit stalled. It is recommended that the encoder be mounted
to the motor using the exact specifications of the encod-
Optical encoders are among one of the more popular er manufacturer and/or a good machine shop.
devices used to determine position of rotating equip-
ment. These devices output two pulse trains with edges
that occur from 2 to 4000 times a revolution.

270061 – 46
Inside track generates Phase A. Outside track generates Phase B.

Figure 4-2. Optical Encoder and Waveforms

39
AP-248

Digital filtering external to the 8096 is used on the en- If it is desired to determine when each edge occurs be-
coder signals. The idealized signals coming from the fore filtering, the encoder outputs can be attached di-
encoder and after the digital filter are shown in Figure rectly to the 8096. As these would be input signals, Port
4-3. The circuitry connecting the encoder to the 8096 0 is the most likely choice for connection. It would not
requires only two chips. A one-shot constructed of be required to connect these lines to the HSI unit, as
XOR gates generates pulses on each edge of each sig- the information on them would only be needed when
nal. The pulses generated by Phase A are used to clock the motor is going very slowly.
the signal from Phase B and vice versa. The hardware is
shown in Figure 4-4. CMOS parts are used to reduce The motor is driven using the PWM output pin for
loading on the encoder so that buffers are not needed. power control and a port pin for direction control. The
Note that T2CLK is clocked on both edges of both 8096 drives a 7438 which drives 2 opto-isolators. These
filtered phases. in turn drive two VFETs. A MOV (Metal Oxide Varis-
tor, a type of transient absorber) is used to protect the
By using this method repetitive edges on a single phase VFETs, and a capacitor filters the PWM to get the best
without an edge on the other phase will not be passed motor performance. Figure 4-5 shows the driver cir-
on to the 8096. Repetitive edges on a phase can occur cuitry. To avoid noise getting into the 8096 system, the
when the motor is stopped and vibrates or when it is g 15 volt power supply is isolated from the 8096 logic
changing direction. The digital filtering technique caus- power supply.
es a little more delay in the signal at slow speeds than
an analog filter would, but the simplicity trade off is This is the extent of the external circuitry required for
worthwhile. The net effect of digital filtering is losing this example. All of the counting and direction detec-
the ability to determine the first edge after a direction tion are done by the 8096. There are two sections to the
change. This does not affect the count since the first example: driving the motor and interfacing to the en-
edge in both directions is lost. coder. The motor driver uses proportional control with

270061 – 47

NOTES:
Phase AÊ is Phase A clocked by Phase B
Phase BÊ is Phase B clocked by Phase A

Figure 4-3. Filtered Encoder Waveforms

40
 AP-248

some modifications and a braking algorithm. Since the In order to interface to the encoder it is necessary to
main point of this example is I/O interfacing, the mo- know the types of waveforms that can be expected. The
tor driver will be briefly described at the end of this motor was accelerated and decelerated many times us-
section. ing different maximum voltages. It was found that the

270061 – 48

Figure 4-4. Schematic of Optical Encoder to 8096 Interface

270061 – 49

Figure 4-5. Motor Driver Circuitry

41
AP-248

motor would decelerate smoothly until the time be- mode is indicated by the lower 2 bits of Port 1, with the
tween encoder edges was around 100 microseconds. At following coding:
this point the motor would either continue to decelerate
slowly, or would suddenly stop and reverse. The latter P1.0 P1.1 Mode Description
case is the one that was most problematic.
0 0 0 HSI looks at every edge
After a brief overview, each section of the program will 1 0 1 HSI looks at Phase A edges only
be described separately, with the complete listing in- 0 1 2 Timer 2 used instead of HSI
cluded in the Appendix D. In order to make debugging 1 1 2 (alternate form of above)
easier, as well as to provide insight into how the pro-
gram is working, I/O port 1 is used to indicate the The example is easiest to see if mode 2 is described first,
program status. This information consists of which rou- followed by mode 1 then mode 0. In mode 2 Timer 2 is
tine the program is in and under which mode it is oper- used to count edges on the incoming signal. A software
ating. The main program sections are: Main loop, HSI timer routine, which is actually run using HSO.0, uses
interrupt, Timer 2 check, and Motor drive. There are the Timer 2 value to update a LONG (32-bit) software
also minor sections such as initialization, timer over- counter labeled POSITION. The HSO routine runs ev-
flow handling, and software timer handling. Tying ev- ery 260 microseconds. The HSO.0 interrupt is used in-
erything together is some overhead and glue. Where the stead of an actual software timer because of the ability
glue is not obvious it will be discussed, otherwise it can to easily unmask it while other software timer routines
be derived from the listings. are running.

The program is a main loop which does nothing except In the code in Listing 4-7, the mode is first determined.
serve as a place for the program to go when none of the For the first pass ignore the code starting with the label
interrupt routines are being run. All of the processing is inÐmodeÐ1. Starting with inÐmodeÐ2 the counter is
done on an interrupt basis. incremented or decremented based on bit zero of DI-
RECT. If DIRECT.0 e 0 the motor is going back-
There are three basic software modes which are in- ward, if it is a 1 the motor is going forward. Next the
voked depending on the speed of the motor. The modes count difference is checked to see if it is slow enough to
referred to as 0, 1 and 2, in order from slowest to fastest go into mode 1. If not the routine returns to the code it
operation. When the program is running the operating was running when the interrupt occurred.

270061 – 50

Listing 4-7. Motor Control HSO.0 Timer Routine

42
 AP-248

270061 – 51

Listing 4-7. Motor Control HSO.0 Timer Routine (Continued)

If the pulse rate is slow enough to go to mode 1, the enable mode 0 after an edge is received. This could
transition is made by enabling HSI.0 and HSI.1. Both cause a problem if the last 2 edges on Phase A before
of these lines are connected to the same encoder line, the encoder stops were too close to enable mode 0. If
with HSI.0 looking for rising edges and HSI.1 looking this happened, mode 0 would not be enabled until after
for falling edges. The HSIÐTIME register is read to the encoder started again, resulting in missed edges on
speed up clearing the HSI FIFO and the LAST1Ð Phase B. Using the HSO routine to switch from mode 1
TIME value is set up so the mode 1 routine does not to mode 0 eliminates this problem.
immediately put the program into another mode. The
HSI FIFO is then cleared, the Timer 2 value used Figure 4-6 shows a state diagram of how the mode
throughout this routine is saved, and the routine re- switching is done. As can be seen, there are two sources
turns. for most of the mode decisions. This helps avoid prob-
lems such as the one mentioned above.
This routine still runs in modes 0 and 1, but in an
abbreviated form. The section of code starting with the When either Mode 1 or Mode 0 is enabled the HSI
label inÐmode1 checks to see if the pulses are coming interrupt routine performs the counting of edges, while
in so slowly that both HSI lines can be checked. If this the HSO routine only ensures that the correct mode is
is the case then all of the HSIs are enabled and the running. The routines for modes 0 and 1 share the same
program returns. This routine is the secondary method initialization and completion sections, with the main
for going from mode 1 to mode 0, the primary method body of code being different.
is by checking the time between edges during the HSI
routine, which will be described later. The initialization routine is similar to many HSI rou-
tines. The flags are checked to ensure that the HSI
The HSO routine will enable mode 0 from mode 1 if FIFO data is valid, and then the FIFO is read. Next,
two edges are not received every 260 microseconds. The the main body of code (for either mode 0 or mode 1) is
primary method, (under the HSI routine), can only

43
AP-248

270061 – 52

NOTES:
Mode 0: HSI Examines edges on Phase A and B
Mode 1: HSI Examines edges on Phase A only
Mode 2: TIMER 2 stores edgecount

Figure 4-6. Mode State Diagram

270061 – 53

Listing 4-8. Motor Control HSI Data Available Routine

44
 AP-248

run. At the end time and count values are saved and the POSITION. The program then returns to the comple-
holding register is checked for another event. Listing 4- tion section of the routine.
8 contains the initialization and completion sections of
the HSI routine. There is a lot more code used in Mode 0 than in Mode
1, most of which is due to the multiple jump statements
Listing 4-9 is the main body of the Mode 1 routine. that determine the current and previous state of the
Before any calculations are done in Mode 1, the incom- HSI pins. In order to save execution time several blocks
ing pulse period is measured to see if it is too fast or too of code are repeated as can be seen in Listing 4-10. The
slow for mode 1. The time period between two edges is first determination is that of which edge had occurred.
used so that the duty cycle of the waveform will not If a Phase A edge was detected the LAST1ÐTIME and
affect mode switching. If it is determined that Mode 2 LAST2ÐTIME variables are updated so a reference to
should be set, Port 1.1 is set, all of the HSI lines are the pulse frequency will be available. These are the
disabled, and the HSI fifo is cleared. If Mode 0 is to be same variables used under Mode 1. A test is also made
set all of the HSI lines are enabled and the variable to see if the edges are coming fast enough to warrant
LASTÐSTAT is cleared. LASTÐSTAT e 0 is used as being in Mode 1, if they are, the switch is made. If the
a flag to indicate the first HSI interrupt in Mode 0 after last edge detected was on Phase B, the information is
Mode 1. After the mode checking and setting are com- used only to determine direction.
plete the incremental value in Timer 2 is used to update

270061 – 54

Listing 4-9. Motor Control Mode 1 Routines

45
AP-248

270061 – 55

Listing 4-10. Motor Control Mode 0 Routines

46
 AP-248

After mode correctness is confirmed and the LASTxÐ is close enough to the desired location that the power to
TIME values are updated the LASTÐSTAT (Last it should be reversed, (i.e., enter the Braking mode). If
Status) variable is used to determine the current direc- the motor is very close to the position or has slowed to
tion of travel. The POSITION value is then updated in the point that is likely to turn around, the HoldÐPosi-
the direction specified by the last two edges and the tion mode is entered.
status is stored. Note that the first time in Mode 0 after
being in Mode 1, the Mode 1 doneÐchk routine is used The determination of which modes are selected under
to update POSITION, instead of the routines goingÐ what conditions was done empirically. All of the pa-
fwd and goingÐrev from the Mode 0 section of code. rameters used to determine the mode are kept in RAM
The completion section of code is then executed. so they can be easily changed on the fly instead of by
re-assembling the program. The parameters in the list-
Providing the PWM value to drive the motor is done by ing have been selected to make the motor run, but have
a routine running under Software Timer 1. The first not been optimized for speed or stability. A diagram of
section of code, shown in Listing 4-11a, has to do with the modes is shown in Figure 4-7.
calculating the position and timer errors. Listing 4-11b
shows the next section of code where the power to be In the HoldÐPosition mode power is eased onto the
supplied to the motor is calculated. First the direction motor to lock it into position. Since the motor could be
is checked and if the direction is reverse the absolute stopped in this mode, some integral control is needed,
value of the error is taken. If the error is greater than as proportional control alone does not work well when
64K counts, the PWM routine is loaded with the maxi- the error is small and the load is large. The BOOST
mum value. The next check is made to see if the motor variable provides this integral control by increasing the
output a fixed amount every time period in which the

Listing 4-11. Motor Control Software Timer 1 Routine

270061 – 56

Listing 4-11a. Motor Control Software Position Counter

47
AP-248

270061 – 57

Listing 4-11b: Motor Control Power Algorithm

48
 AP-248

270061 – 58

Figure 4-7. Motor Control Modes

error does not get smaller. Once the error does get A sanity check can be performed at this point to double
smaller, usually because the motor starts moving, check that the 8096 has proper control of the motor. In
BOOST is cleared. the example the worst that can happen is the proto-

270061 – 59

Listing 4-12. Motor Control Next Position Lookup

49
AP-248

type will need to be reset, so the sanity check was not The remaining sections of the program are relatively
used. If one were desired, it could be as simple as simple, but worth discussing briefly. The initialization
checking a hardware generated direction indicator, or routine initializes the I/O features and places several
as complex as checking motor condition and other en- variables from ROM into RAM. Having these variables
vironmental factors. in RAM makes it easier to tweak the algorithm. Timer
1 is expanded into a 32-bit timer by the interrupt rou-
After all checks have been made, the power value is tine shown in Listing 4-13.
loaded to the RPWR register using a software inversion
to compensate for the hardware inversion. Direction is Software timer overhead is handled by the routine
determined next and the power and direction are shown in Listing 4-14. In this routine the status of each
changed in adjacent instructions with interrupts dis- timer bit is checked in a shadow register. If any of the
abled to prevent changing power without direction and timers have expired the appropriate routine is called.
vice versa.

To exercise the program logic the desired position is

changed based on the time value using the code and
lookup table shown in Listing 4-12.

270061 – 60

Listing 4-13. Motor Control Timer Interrupt Routine

270061 – B2

Listing 4-14. Motor Control Software Timer Interrupt Handler

50
 AP-248

270061 – 61

Listing 4-15: Motor Control Software Timer 2 Routine

The last routine, shown in Listing 4-15, is the Software always operates smoothly and provides at least 200 mi-
Timer 2 routine which outputs some variables to exter- croseconds between the last several edges of Phase A
nal RAM. It also keeps LAST1ÐTime within 1800H before reversing. This idea was originally tried because
of Timer1 to prevent overflows from occurring when the motor was not characterized thoroughly at first,
the Mode 0 and Mode 1 software check this variable. and caused problems because of the motors tendency to
stop suddenly when its speed was low.
A complete listing of the program as it is used in our
lab can be found in Appendix D. For a given motor or If an encoder has a lower line count and therefore more
encoder it will probably be necessary to change some of time between output pulses the two mode solution can
the time constants on the first page of the listing. With be used. The software for the two mode version can be
the motor used in our experimentation, pulses are easily extracted form the three mode version, so it will
missed from time to time when direction changes not be presented.
quickly. If the motor were not as fast to turn around or
the encoder were mounted better these problems should
disappear. The missing pulses occur when switching 5.0 HARDWARE EXAMPLE
from Mode 1 to Mode 0, other than that no anomalies
were found in the lab.
5.1. EPROM Only Minimum System
Prior to the version of code just discussed, several at-
tempts were made, one of which could be used under The diagram in Figure 5-1 illustrates how to connect an
certain constraints. It is possible to use only modes 2 8096 in a minimum configuration system. Either 2764s
and 0 to monitor the encoder, provided the encoder or 27128s can be used in the system. Note that the
lower EPROM contains the even bytes while the upper

51
AP-248

270061 – 62

Figure 5-1 (1 of 2).

one contains the odd bytes, and the addressing is not 4K is mapped at 2000H. If the program being loaded is
fully decoded. This means that the addressing on a 16 Kbytes long the first half is loaded into the second
2764 will be such that the lower 4K of each EPROM is half of the 2764s and vice versa. A similar situation
mapped at 0000H and 4000H while the upper exists when using 27128s.

52
 AP-248

270061 – 63

Figure 5-1 (2 of 2).

This circuit will allow most of the software presented in the usage of the lines can be restricted to inputs or
this ap-note to be run. In a system designed for proto- outputs on a port by port rather than line by line basis.
typing in the lab it may be desirable to buffer the I/O The ports are reconstructed by using standard memory-
ports to reduce the risk of burning out the chip during mapped I/O techniques, (i.e., address decoders and
experimentation. One may also want to enhance the latches), at the appropriate addresses. If no external
system by providing RC filters on the A to D inputs, a RAM is being used in the system then the address de-
precision VREF power supply, and additional RAM. coding can be partial, resulting in less complex logic.

The reconstructed I/O ports will work with the same

5.2. Port Reconstruction code as the on chip ports. The only difference will be
the propagation delay in the external circuitry.
If it is desired to fully emulate a 8396 then I/O ports 3
and 4 must be reconstructed. It is easiest to do this if

53
AP-248

6.0 CONCLUSION 7.0 BIBLOGRAPHY

1. MSC-96 Macro Assembler User’s Guide, Intel Cor-
An overview of the MCS-96 family has been presented poration, 1983.
along with several simple examples and a few more
complex ones. The source code for all of these pro- Order number 122048-001.
grams are available in the Insite Users Library using 2. Microcontroller Handbook (1985), Intel Corpora-
order code AE-16. Additional information on the 8096 tion, 1984.
can be found in the Microcontroller Handbook and it is Order number 210918-002.
recommended that this book be in your possession be-
fore attempting any work with the MCS-96 family of 3. MSC-96 Utilities User’s Guide, Intel Corporation,
products. Your local Intel sales office can assist you in 1983.
getting more information on the 8096 and its hardware Order number 122049-001.
and software development tools. 4. PL/M-96 User’s Guide, Intel Corporation, 1983.
Order number 122134-001.

54
 AP-248

APPENDIX A
BASIC SOFTWARE EXAMPLES

270061– 64

A.1. Table Lookup 1

A-1
AP-248

270061– 65

A.1. Table Lookup 1 (Continued)

A-2
 AP-248

270061– 66

A.2. Table Lookup 2

A-3
AP-248

270061– 67

A.2. Table Lookup 2 (Continued)

A-4
AP-248

270061– 69

270061– 70

A.3. PLM-96 Code with Expansion (Continued)

A-6
 AP-248

270061– 71

A.3. PLM-96 Code with Expansion (Continued)

A-7
AP-248

270061– 72

A.3. PLM-96 Code with Expansion (Continued)

A-8
 AP-248

270061– 73

A.3. PLM-96 Code with Expansion (Continued)

A-9
AP-248

270061– 74

A.3. PLM-96 Code with Expansion (Continued)

A-10
 AP-248

270061– 75

A.4. Pulse Measurement

A-11
AP-248

270061– 76

A.4. Pulse Measurement (Continued)

A-12
 AP-248

270061– 77

A.5. Enhanced Pulse Measurement

A-13
AP-248

270061– 78

A.5. Enhanced Pulse Measurement (Continued)

A-14
 AP-248

270061– 79

A.6. PWM Using the HSO

A-15
AP-248

270061– 80

A.6. PWM Using the HSO (Continued)

A-16
 AP-248

270061– 81

A.6. PWM Using the HSO (Continued)

A-17
AP-248

270061– 82

A.6. PWM Using the HSO (Continued)

A-18
 AP-248

270061– 83

A.7. Serial Port

A-19
AP-248

270061– 84

A.7. Serial Port (Continued)

A-20
 AP-248

270061– 85

A.8. A to D Converter

A-21
AP-248

270061– 86

A.8. A to D Converter (Continued)

A-22
 AP-248

APPENDIX B
HSO AND A TO D UNDER INTERRUPT CONTROL

270061– 87

B-1
B-2
AP-248

270061– 88
 270061– 89

B-3
AP-248
B-4
AP-248

270061– 90
 AP-248

APPENDIX C
SOFTWARE SERIAL PORT

270061– 91

C-1
C-2
AP-248

270061– 92
 270061– 93

C-3
AP-248
C-4
AP-248

270061– 94
 270061– 95

C-5
AP-248
C-6
AP-248

270061– 96
 AP-248

APPENDIX D
MOTOR CONTROL PROGRAM

270061– 97

D-1
D-2
AP-248

270061– 98
 270061– 99

D-3
AP-248
D-4
AP-248

270061– A0
 270061– A1

D-5
AP-248
D-6
AP-248

270061– A2
 270061– A3

D-7
AP-248
D-8
AP-248

270061– A4
 270061– A5

D-9
AP-248
AP-248

270061– A6

D-10
AP-248

270061– A7

D-11
AP-248

270061– A8

D-12
AP-248

270061– A9

D-13
AP-248

270061– B0

D-14
 AP-248

270061– B1

D-15
INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080

INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000

INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511

Microcontroller Operation
Printed in U.S.A./xxxx/0296/B10M/RP SM
UNIT V Case Study for 8051 and 8096

Real Time clock

A real-time clock (RTC) is a computer clock (most often in the form of an integrated circuit) that keeps
track of the current time.
Although the term often refers to the devices in personal computers, servers and embedded systems,
RTCs are present in almost any electronic device, which needs to keep accurate time. A common
RTC used in single-board computers is the DS1307.
The term real-time clock is used to avoid confusion with ordinary hardware clocks which are only
signals that govern digital electronics, and do not count time in human units. RTC should not be
confused with real-time computing, which shares its three-letter acronym but does not directly relate
to time of day.
The term real-time clock is used to avoid confusion with ordinary hardware clocks which are only
signals that govern digital electronics, and do not count time in human units. RTC should not be
confused with real-time computing, which shares its three-letter acronym but does not directly relate
to time of day.

Purpose
Although keeping time can be done without an RTC, using one has benefits:

 Low power consumption (important when running from alternate power)

 Frees the main system for time-critical tasks
 Sometimes more accurate than other methods
A GPS receiver can shorten its startup time by comparing the current time, according to its RTC, with
the time at which it last had a valid signal. If it has been less than a few hours, then the
previous ephemeris is still usable.

Power Source
RTCs often have an alternate source of power, so they can continue to keep time while the primary
source of power is off or unavailable. This alternate source of power is normally a lithium battery in
older systems, but some newer systems use a super capacitor, because they are rechargeable and
can be soldered. The alternate power source can also supply power to battery backed RAM.

Timing
Most RTCs use a crystal oscillator, but some use the power line frequency. In many cases, the
oscillator's frequency is 32.768 kHz. This is the same frequency used in quartz clocks and watches,
and for the same reasons, namely that the frequency is exactly 215 cycles per second, is a
convenient rate to use with simple binary counter circuits.
Many commercial RTC ICs are accurate to less than 5 parts per million. In practical terms, this is
good enough to perform celestial navigation, the classic task of a chronometer. In 2011, Chip-scale
atomic clocks were invented. Although more expensive, they keep time within 100 nanoseconds.

Generation of Gating Signals:

Objectives

1. To study about different types of gate pulses.

2. To study the architecture of Microcontroller PIC16f72 and its application as a programmable
gate pulse generator.
3. To study the architecture of comparator LM 324 for using as sensing device for the triggering
point of three phase sine wave.
4. Generation of programmable gate pulses for driving a three phase IGBT module.
5. Generation of programmable gate pulses for driving a typical SCR module.

Advantages of Programmable Gate Pulse

1. The main advantage of programmable gate pulses is the opportunity to change program
according to the requirements.
2. Same device can be used for different types of gate pulses.
3. Controlling the abnormality of the power devices using feedback.
4. Wide range of control over frequency.

Microcontroller
A microcontroller typically includes-

1. CPU (Central Processing Unit or the microprocessor)

2. EEPROM / EPROM / PROM / ROM (Read Only Memory for the program code)
3. RAM (Random, Access Memory for the program code)
4. I /O (Input / Output) devices (serial, parallel, ADC, DAC etc.)
5. Timers
6. Interrupt controller
7. Embedded Controller
8. ADC
9. Calculator
10. PWM function generator
Pin Diagram

Application of Microcontroller
• Building control

- Access control
- Temperature sensing
- lighting
• Industrial control

- Process control
• Instrumentation

- Industrial instrumentation
• Metering

- Handheld metering systems

• Motor speed control

- AC motor control
- DC motors
- Steppers
• Automotive

- LIN slave nodes

- Body and convenience electronics
Op-Amp LM324
These circuits consist of four independent, high gain, internally frequency compensated operational
amplifiers.They operate from a single power supply over a wide range of voltages. Operation from
split power supplies is also possible and the low power supply current drain is independent of the
magnitude of the power supply voltage.
Pin Diagram
IGBT Gate Pulse Calculation

Solving equation above we get the value of t1 = 800.8429071 us

Logic States of PWM for Positive Half Cycle
Three Phase Representation in terms of Six Gate Signals

Sample Logic States with Duration for First 5 Conditions

Sample Program For First Two Durations

void main()
{
trisa = 0b00000000; // defining all the pins of port A are output pins //
trisb = 0b00000000; // defining all the pins of port B are output pins //
while(1) // infinite loop creation //
{
portb=0b00000001; // changing the states of RB0, RB1 and RB2 to 1, 0 and 0 respectively //
porta=0b00000010; // changing the states of RA0, RA1 and RA2 to 0, 1 and 0 respectively //
delay_us(405); // holding the above states of the pins for 405 microsecond //
portb=0b00000001; // changing the states of RB0, RB1 and RB2 to 1, 0 and 0 respectively //
porta=0b00000000; // changing the states of RA0, RA1 and RA2 to 0, 0 and 0 respectively //
delay_us(396); // holding the above states of the pins for 396 microsecond //
}
}
Block Diagram for IGBT Inverter

Connection Diagram for IGBT Inverter

Output Gate Pulses of Phase 2 and Phase 2΄

Combined Set of Wave Shapes

Gate pulses with rearranged sequence

mikroC Instruction for Controlled Rectifier
void main()
{
trisb=0b00000000; // Defining port B as output //
trisc=0b10000000; // Defining pin no. 7 of port C as input //
portb=0; // Initially hold the port B to idle //
check:
if(portc.f7==0) // Condition check for entering at ready state //
{
goto run; // Jump to ready state defined by run //
}
if(portc.f7==1) // Avoiding the initial high state //
{
portb=0; // Keeping the port B in idle for port C7 in high //
goto check;
}
run:
while(portc.f7==0)
{
asm nop;
}
if(portc.f7==1) // After the initial low and than high, entering the loop //
{
delay_ms(4); // Defined delay for the controlled rectifier //
while(1) // Infinite loop instruction //
{
portb=0b00000001; // Starts the logic conditions according to figure 5.8 //
delay_ms(1);
portb=0b00000000;
delay_us(2333);
portb=0b00100000;
delay_ms(1);
portb=0b00000000;
delay_us(2334);
portb=0b00000010;
delay_ms(1);
portb=0b00000000;
delay_us(2333);
portb=0b00001000;
delay_ms(1);
portb=0b00000000;
delay_us(2333);
portb=0b00000100;
delay_ms(1);
portb=0b00000000;
delay_us(2334);
portb=0b00010000;
delay_ms(1);
portb=0b00000000;
delay_us(2333);
}
}
}
Flow Chart for Controlled Rectifier

Connection Diagram for Controlled Rectifier

Thyristor 1 and Thyristor 6 gate pulses

Recommended Further Extension

In the case of IGBT inverter the durations for each logic states can be multiplied by a factor affecting
the frequency. This can be programmed to sense an input pin for ADC or for only sensing a binary
one which will decrease the value of the factor to increase the frequency of the inverter output.
In case of controlled rectifier if we avoid the infinite loop defined by while(1) to enter the program after
sensing the comparator's high output and sense the comparator output after every loop
accomplishment and than define the delay angle in terms of time delay determined by other input pins
sensing as ADC input or for only sensing a binary one/zero which will increase or decrease the delay
angle, we can get the control over 0˚ to 180 ˚ of the sine wave.

Frequency Measurement using Microcontrollers

A frequency counter is a useful addition to an engineer's toolbox and you can create the design
described on this page for free. All you need is a PIC microcontroller (or any microcontroller that has a
high speed timer input module) and a 2 line LCD display (the standard HD44780 one is the one used
here).

This PIC frequency counter project uses an LCD to display the frequency and PIC timer 1 to measure
the input signal and Timer0 to measure the timing period.

It uses Timer 1 in 16 bit counter mode to count the input signal edges and overflows of the counter
are accumulated to give the total count in multiples of 65536.Adding the current value of the counter
at the end gives the total count.

The crystal oscillator is chosen to be 4MHz (Fosc) so that the processor internal clock is 1MHz
(Fosc/4). All you do is count 1e6 processor clocks (Timer0) to give a 1second count period.

Since the measurement time is 1 second the final count is actually the frequency of the input signal
i.e. number of input periods counted in 1 second is the frequency in Hz.

Using the 1 second measurement time also gives a frequency resolution of 1 Hz.

Specification: LCD frequency counter circuit

Min frequency 1Hz

~50MHz (limited by input pin characteristics).
Max frequency
(Tested using TTL oscillator at 20MHz).

Input signal level TTL

Pic frequency counter Hardware

The hardware is simple and the main blocks are shown in the diagram below.

The LCD is used in 4 bit mode interface so you only need 4 data lines and three control lines and it
then fits into a single 8 bit port.

The crystal oscillator is simply a crystal and two capacitors connected to the PIC oscillator port at
OSC1 and OSC2. The capacitors can both be fixed at the same value unless you want to tune it using
a frequency reference. If you don't have an accurate reference then use fixed capacitors.

The PIC micro can be any type that has Timer 0 and Timer 1 hardware modules and and has enough
memory to hold the program ~1.6k words.

The LED is toggled to indicate that the processor is alive - so if there is no input signal you can tell
that the software is working. Also if there is no input signal the the LCD displays a flashing zero.

You can program the PIC in circuit through the ICSP connector in circuit.

Description

To time a 1 second count Timer0 is used. Since the main clock is running at 4MHz then the processor
clock (Fosc/4) is 1MHz which is the rate that Timer0 is set-up to use i.e. the internal clock. Therefore
we need to get a 1 second count using that timer. Since the timer is only 8 bits long you can use the
fact that an interrupt is generated when it overflows - you can then count these overflows to get near
to 1e6 counts.

Since the overflow occurs every time that the counter passes 256 we need to count 1e6/256
overflows

1e6/256 = 3906.25

We can only count integer overflows so must manipulate the last count to get the exact time. So we
need the modulus of 1e6 and 256:

1e6 % 256 is 64 (0.25*256 is 64).

The interrupt routine starts off after being zeroed by counting 3906 overflows, it then controls a flag
variable (do_TMR0_end_count) that indicates this is the last overflow for which the Timer0 value is
set to overflow after 64 Fosc/4 cycles:

TMR0 = 256-64+2; // 2 cycles lost when writing to TMR0 so add 2.

At the end of the last overflow the values of Timer1 are captured to:

st_TMR1L

st_TMR1H

st_TMR1_ovfl

An LCD update request is sent from the interrupt routine to the main routine by setting a flag
(update_LCD) and the main routine then uses ltoa to calculate and output the frequency
measurement to then display on LCD.

PIC frequency counter Software

Project files for the PIC frequency counter

Compiler project files

frequency_counter_4MHz_LCD_TMR1.mcppi

This is the main project file.

There are other files since MikroC version 6.0.4 seems to need a lot more than V5! just keep them in
your project folder.

C Source files.
Frequency_counter_4MHz_LCD_TMR1.c
ltoa.c

Header files.
bit.h
ltoa.h

Output files
Frequency_counter_4MHz_LCD_TMR1.hex

For a tutorial on compiling these files click here.

You only need to recompile the pic frequency counter files if you want to change the source code or
examine how the code works using the built in simulator since the hex file to program the chip is
included in the download.

Brief description

 frequency_counter...c : contains the code start point (in routine 'main') and the interrupt
routine.
 ltoa.c contains a long to ascii converter used for display of the frequency count.
 bit.h : contains macros for bit manipulation.

All other header files contain prototypes.

PIC frequency counter code operation.

The code uses the built in LCD driver routines which are automatically included by the compiler. Note
automatic include is unusual but it seems to work well in mikroC.

Interrupts are not used only the flags that can be polled (timer overflow) are activated.

frequency_counter_4MHz_LCD_TMR1.c

This file contains the port initialization, interrupt and main routine.

After initialization the code enters an endless loop where it continuously performs a measurement and
display operation. After an accurate 1 second delay the counter result is processed and displayed on
the LCD.

The main operation of this code is within the interrupt routine that both counts the input edges and
obtains an accurate 1s time by counting the edges of the internal oscillator clock (Fosc/4).

Interrupts

The most important part of this counter is the interrupt() routine. This is where all the action and
decisions are made.

The interrupt code for Timer1 is very simple and all it does is increment a long variable for counting
multiple input events.

The more tricky interrupt code, for Timer 0, counts time as described above. It counts 3906 overflows
followed by a single 64 cycle count to reach a time of 1 second after which it captures the event count
and then triggers an update to the LCD to calculate and display the frequency. The update triggers
the actions in main().

bit.h

This contains macros for bit manipulation which should be compiler independent.

Automatic Temperature Controller

Automatic Temperature controller: This embedded system project is about automatic temperature
controller using pic microcontroller. Automatic temperature control is a microcontroller based circuit
which is used to maintain a temperature specified by the user. The user enters the reference
temperature by keypad and then the microcontroller turn on and off the heater or cooler when the
temperature is too hot or too cold. PIC 18F45K22 is the brain of this automatic temperature controller
system. It uses LM35 temperature sensor to measure temperature.
Use of Automatic Temperature Controller
 Server Rooms.
 Poultry Control Sheds.
 Central Air Conditions System.
 Storage Houses.
 Home automations.
 Food Factories
 Hospitals
 Industries
Components of automatic temperature controller system
 PIC 18F45K22: PIC 18F45K22 has 40 pins. It has voltages operating range between 1.8v to 5.5v.
It has low power consumption. It CPU Speed is 16 MIPS. It has 1536bytes RAM. It is best for such
projects.
 Keypad: In this project I you 3×4 keypad to enter the reference voltage.
 16×2 LCD: LCD is used to show alpha numeric characters. In this project LCD we use is 16×2
which means we can display 16 characters in two lines. LCD is used to show the reference
temperature and actual temperature.
 Relays 5v: Relay is an electromagnetic device used to switch on and off devices which used high
voltages. In our project relay is used to switch on and off the heater and the cooler.
 BC108: TheBC108 is low power Silicon NPN bipolar junction transistors found very common in
electronics In our project it is used to switch the relays on and off.
 LM35: LM35 is precision integrated-circuit temperature devices with an output voltage linearly-
proportional to the Centigrade temperature. It is small in size and very cheap as compare to other
temperature sensors. Its range of measuring lies between -55 to 150 degree centigrade.
 Bulb as heater: It is used to produce heat as a result it rises the temperature to our desire
temperature.
 Motor as Cooler: It is used to reduce temperature to our desire temperature.
 Crystal: It is used as oscillator. In the project I use 8 MHz crystal.
 Resistors: It is used as pull down resistors with keypad and as a base resister with transistors. The
resistors used in this project are mostly of 10KΩ. Potentiometer of 10KΩ is used to set contrast of
the LCD.
 Connection: PORT A is used as analog input. So LM35 is connected on PORT A. PORT C is used
as digital PORT and 16×2 LCD is connected on PORT C. PORT D is connected with heater and
cooler as it is used as digital output. 3×4 keypad is connected on PORT B as it is used as digital
port. Base of the both transistor is connected with PORT D, emitter are grounded, collectors are
connected with the one terminal of relays coil. Heater and the Cooler is connected on normally
open terminal of relays.

Circuit diagram of automatic temperature controller

When the circuit starts it demands to put a reference voltage which in our case lies between 0’C to
150’C. The reference value is entered using the keypad. After entering the reference value # is press
to proceed. If you enter a wrong value you can remove it by pressing ‘*’.The PIC microcontroller
measure temperature using LM35 which is an analog temperature sensor every 10 second and
compares it with the reference value enters by the user. When the reference value is higher than the
measured value, then the heater is turned ON to heat the area. The heater is switched OFF once the
reference temperature is reached. When the measured value is higher than the reference value, then
the cooler is switched ON to cool off the area until the required temperature is reached. An LCD
display shows the measured temperature continuously.

ARM 32 Bit Processor

An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set computer)
architecture developed by Advanced RISC Machines (ARM). ARM makes 32-bit and 64-bit RISC
multi-core processors. ... An orthogonal instruction set.
ARM, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced
instruction set computing (RISC) architectures for computer processors, configured for various
environments. British company ARM Holdings develops the architecture and licenses it to other
companies, who design their own products that implement one of those architectures—including
systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate memory, interfaces, radios,
etc. It also designs cores that implement this instruction set and licenses these designs to a number
of companies that incorporate those core designs into their own products.
Processors that have a RISC architecture typically require fewer transistors than those with a complex
instruction set computing (CISC) architecture (such as the x86 processors found in most personal
computers), which improves cost, power consumption, and heat dissipation. These characteristics are
desirable for light, portable, battery-powered devices—including smartphones, laptops and tablet
computers, and other embedded systems. For supercomputers, which consume large amounts of
electricity, ARM could also be a power-efficient solution.

ARM Architecture
The 32-bit ARM architecture, such as ARMv7-A, was the most widely used architecture in mobile
devices as of 2011.

Since 1995, the ARM Architecture Reference Manual has been the primary source of documentation
on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM
processors are required to support (such as instruction semantics) from implementation details that
may vary. The architecture has evolved over time, and version seven of the architecture, ARMv7,
defines three architecture "profiles":

A-profile, the "Application" profile, implemented by 32-bit cores in the Cortex-A series and by some
non-ARM cores
R-profile, the "Real-time" profile, implemented by cores in the Cortex-R series
M-profile, the "Microcontroller" profile, implemented by most cores in the Cortex-M series
Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the
ARMv6-M architecture (used by the Cortex M0/M0+/M1) as a subset of the ARMv7-M profile with
fewer instructions.

Instruction Set
The original (and subsequent) ARM implementation was hardwired without microcode, like the much
simpler 8-bit 6502 processor used in prior Acorn microcomputers.
The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC
features:

 Load/store architecture.
 No support for unaligned memory accesses in the original version of the architecture. ARMv6 and
later, except some microcontroller versions, support unaligned accesses for half-word and single-
word load/store instructions with some limitations, such as no guaranteed atomicity.
 Uniform 16× 32-bit register file (including the program counter, stack pointer and the link register).
 Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code
density. Later, the Thumb instruction set added 16-bit instructions and increased code density.
 Mostly single clock-cycle execution.
To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola
68020, some additional design features were used:

 Conditional execution of most instructions reduces branch overhead and compensates for the
lack of a branch predictor.
 Arithmetic instructions alter condition codes only when desired.
 32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and
address calculations.
 Has powerful indexed addressing modes.
 A link register supports fast leaf function calls.
 A simple, but fast, 2-priority-level interrupt subsystem has switched register banks.

ARM Cortex M

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. The
cores are intended for microcontroller use. The cores consist of the Cortex-M0, Cortex-M0+, Cortex-
M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33. The Cortex-M4 / M7 / M33 cores
have an FPU option, and these cores are known as "Cortex-Mx with FPU" or Cortex-MxF, where 'x' is
the core number. ARM Cortex-M cores have been shipped in tens of billions of devices.

The ARM Cortex-M family are ARM microprocessor cores which are designed for use in
microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Cortex-M cores are commonly used as
dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management
controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, and
sensors controllers.

Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping away
at the 8-bit market as the prices of low-end Cortex-M chips have moved downward. Cortex-M have
become a popular replacements for 8-bit chips in applications that benefit from 32-bit math
operations, and replacing older legacy ARM cores such as ARM7 and ARM9.
Arm Cortex-M processors provide:

 High performance and efficiency

 Easy software development, as all Cortex-M processors are fully C programmable
 Compact data footprint, with support for 8-bit, 16-bit and 32-bit data transfers
 Fast and power-efficient algorithm processing with DSP extensions in Cortex-M4, Cortex-M7 and
Cortex-M33
The Armv8-M based Cortex-M processors also include TrustZone technology. TrustZone has
been proven as a security foundation in billions of devices. TrustZone for the Cortex-M profile
has been optimized for microcontroller class devices offering deterministic real -time interrupt
response, low power and a small area with fast cross-domain calls.
 ISSN (Print) : 2320 – 3765
ISSN (Online): 2278 – 8875

International Journal of Advanced Research in Electrical,

Electronics and Instrumentation Engineering
(An ISO 3297: 2007 Certified Organization)

Vol. 5, Issue 4, April 2016

A Study on DC Motor Operations and Speed

Control Using Microcontroller
Anjaly Divakar1, Jibin Joseph2, Jinu T George3, Nandakumar N Prabhu4, Absal Nabi5
B.Tech Student, Dept. of EEE, Ilahia College of Engineering and Technology, Ernakulam, Kerala, India1
B.Tech Student, Dept. of EEE, Ilahia College of Engineering and Technology, Ernakulam, Kerala, India2
B.Tech Student, Dept. of EEE, Ilahia College of Engineering and Technology, Ernakulam, Kerala, India3
B.Tech Student, Dept. of EEE, Ilahia College of Engineering and Technology, Ernakulam, Kerala, India4
HOD, Dept. of EEE, Ilahia College of Engineering and Technology, Ernakulam, Kerala, India5

ABSTRACT: The project is proposed to develop a four quadrant speed control system for a DC motor with Pulse
width modulation (PWM). The motor is operated in four quadrants i.e. clockwise, anti clock-wise, forward braking and
reverse braking. Four quadrant operations are suited for industrial applications. DC motor can rotate in clockwise, anti-
clockwise directions. Also we can apply braking for instantaneous stop in both the directions. In case of urgent
operation in industrial field the motor may needs to be stopped immediately. In such a case these systems is very useful
for forward braking and reverse braking. As the reverse voltage is used for running DC motor the braking in both
directions is possible for a small period. PWM pulses generated by microcontroller also control the speed of the motor
Microcontroller used in this project is from the 8051 family. A motor driver IC is provided here for motor speed control
also seven push buttons are interfaced with microcontroller for giving input signal as well as to operate the motor. This
project features the speed control by the push button operation. To operate high capacity DC motors this project can be
enhanced by using high power electronic devices.

KEYWORDS: Four quadrant operation, Pulse width modulation, Hardware model and Softwares, Working

I.INTRODUCTION
DC machines play a very important role in industries and in our daily life as they offer easily controllable
characteristics. This paper is designed to develop a four quadrant speed control system for a DC motor using
microcontroller. The DC motor is operated in four quadrants i.e. clockwise, anti-clockwise, forward braking and
reverses braking. Also it features speed control. There are four possible modes or quadrants of operation [3] using a DC
Motor .When DC motor is operating in the first and third quadrant, the supplied voltage is greater than the back emf
which is forward motoring and reverse motoring flow differs. When the motor operates in the second and fourth
quadrant the value of the back emf generated by the motor should be greater than the supplied voltage which are the
forward braking and reverse braking [4] modes of operation respectively, here again the direction of current flow is
reversed flow differs. When the motor operates in the second and fourth quadrant the value of the back emf generated
by the motor should be greater than the supplied voltage which are the forward braking and reverse braking modes of
operation respectively, here again the direction of current flow is reversed modes respectively, but the direction of
current flow is reversed.

Copyright to IJAREEIE DOI:10.15662/IJAREEIE.2016.0504038 2460

 ISSN (Print) : 2320 – 3765
ISSN (Online): 2278 – 8875

International Journal of Advanced Research in Electrical,

Electronics and Instrumentation Engineering
(An ISO 3297: 2007 Certified Organization)

Vol. 5, Issue 4, April 2016

Fig .1 Four Quadrant operations

Fig 1 shows the four possible modes or quadrants of operation [3] using a DC Motor. The four operations named as
forward motoring, forward braking, reverse motoring, and reverse braking in the 1st, 2nd, 3rd and 4th quadrants
respectively.
II. PULSE WIDTH MODULATION
Pulse-width modulation (PWM) [2] is a commonly used technique for controlling power to an electrical device, made
practical by modern electronic power switches. The average value of voltage (and current) fed to the load is controlled
by turning the switch between supply and load on and off at a fast pace. The longer the switch is on compared to the off
periods, the higher the power supplied to the load is. The term duty cycle describes the proportion of on time to the
regular interval or period of time; a low duty cycle corresponds to low power, because the power is off for most of the
time. Duty cycle is expressed in percent, 100% being fully on. The main advantage of PWM is that power loss in the
switching devices is very low. When a switch is off there is practically no current, and when it is on, there is almost no
voltage drop across the switch. Power loss, being the product of voltage and current, is thus in both cases close to zero.
PWM works also well with digital controls, which, because of their on/off nature, can easily set the needed duty cycle.
PWM has also been used in certain communication systems where its duty cycle has been used to convey information
over a communications channel. The duty cycle determines the speed of the motor. The desired speed can be obtained
by changing the duty cycle. The PWM in microcontroller is used to control the duty cycle of DC motor. The PWM
pulses generated from the microcontroller are viewed for various duty cycles in the simulation done in proteous
software.
III. BLOCK DIAGRAM
Fig 2 shows the main block diagram of the project. It includes a Transformer, Bridge rectifier, Voltage regulator,
Switch array, Microcontroller, Motor driver IC and DC motor.
TRANSFORMER: The power supply for the circuit is given through step down transformer, which converts from
230V to 12V.
BRIDGE RECTIFIER: The output of transformer is given to bridge rectifier, consist of four diodes that delivers
pulsating dc which is unregulated is regulated to constant 5V dc with the help of regulator.

Copyright to IJAREEIE DOI:10.15662/IJAREEIE.2016.0504038 2461

 ISSN (Print) : 2320 – 3765
ISSN (Online): 2278 – 8875

International Journal of Advanced Research in Electrical,

Electronics and Instrumentation Engineering
(An ISO 3297: 2007 Certified Organization)

Vol. 5, Issue 4, April 2016

REGULATOR: The output of the bridge rectifier is connected to the regulator [8] which regulates the 12 volt
unregulated dc to regulated 5V supply.
SWITCH ARRAY: Switch array consist of 7 push button switches. Each switch is assigned specific functions,
accordingly control pulses is given to motor driver IC for controlling Motor.

Fig. 2 Block diagram

MICROCONTROLLER: The microcontroller [5] used is AT89C51.It is 40 pin ic which operates using 5V dc.
MOTOR DRIVER IC: The IC used is L293D.It is a dual H-bridge motor driver integrated circuit (IC).It works based
on the signal from the microcontroller.
MOTOR: The motor used is 12V DC motor, which performs all the 4 quadrant operations.
IV. WORKING
The circuit uses standard power supply comprising of a step down transformer from 230V to 12V and the four diodes
forming a bridge rectifier that delivers pulsating dc which is unregulated is regulated to constant 5V dc. The output of
the power supply which is 5V is connected to the microcontroller. Here seven switches are interfaced to MC to control
the speed of motor in four quadrants [6]. When start switch is pressed the motor starts rotating in full speed being
driven by a motor driver IC L293D [7] that receives control signal continuously from the MC. When clockwise switch
is pressed the motor rotates in forward direction as per the logic provided by the program from the MC to the motor
driver IC. While forward brake is pressed a reverse voltage is applied to the motor by the motor driver IC by sensing
reverse logic sent by the MC for a short time period due to which instantaneous brake situation is applied to the motor.
Similarly when motor is rotating in anti-clockwise direction by appropriate logic from the MC to the motor driver IC
and reverse brake switch is pressed the MC delivers a logic to the motor driver IC that develops for very small time a
reverse voltage across the running motor due to which instantaneous brake situation happens to the motor.
PWM switch is used to rotate the motor at varying speed by delivering from the MC a varying duty cycle to the enable
pin of the motor driver IC. It starts from 100% duty cycle and reduces in steps of 10% when it is pressed again and
finally reaches to 10% duty cycle and the process repeats. Stop button is used to switch OFF the motor by driving the
enable pin to ground from the MC command accordingly.

Copyright to IJAREEIE DOI:10.15662/IJAREEIE.2016.0504038 2462

 ISSN (Print) : 2320 – 3765
ISSN (Online): 2278 – 8875

International Journal of Advanced Research in Electrical,

Electronics and Instrumentation Engineering
(An ISO 3297: 2007 Certified Organization)

Vol. 5, Issue 4, April 2016

Fig. 3 Hardware model

Fig 2 shows the hardware model of the project. It includes a Transformer, Bridge rectifier, Voltage regulator, Switch
array, Microcontroller, Motor driver IC and DC motor. When the switches are pressed and released the respective
operations are performed by the DC motor as assigned. Start, stop, Forward motoring, Reverse motoring, Forward
braking, Reverse braking, PWM speed control and Stop are the functions assigned to 1st,2nd,3rd,4th,5th,6th and 7th
pushbuttons respectively.
V. ALGORITHEM
1. Start
2. Initialize variables and functions
3. Check the inputs from the push bottom
Start=P1*0
Clock=P1*1
Anti_clock=P1*2
F_break=P1*3
4. If start=0; EN1=1, IN1=1, IN2=0.Motor is on.
5. If clock=0; EN1=1, IN1=1, IN2=0.Motor runs in clockwise direction.
6. If a_clock=0; EN1=1, IN1=0, IN2=1. Motor runs in anti-clockwise direction.
7. If f_break=0; Stops motor immediately in the forward direction.
8. If a_break=0; Stops motor immediately in the reverse direction.
9. If stop=0; Stops motor.
10. Stop.

VI. SOFTWARE USED

Kiel: Support every level of software developer from the professional applications engineer to student in learning about
embedded software development. When starting a new project, simply select the microcontroller and µvision IDE sets
all compiler, assembler, linker, and memory options.
Proteus 8 professional: It has been used to simulate the result in software. It is software used for simulation of
electronic circuits as well as PCB designing.

Copyright to IJAREEIE DOI:10.15662/IJAREEIE.2016.0504038 2463

 ISSN (Print) : 2320 – 3765
ISSN (Online): 2278 – 8875

International Journal of Advanced Research in Electrical,

Electronics and Instrumentation Engineering
(An ISO 3297: 2007 Certified Organization)

Vol. 5, Issue 4, April 2016

VII. RESULT

Fig. 4 PWM output waveform

Fig 4 shows the simulated PWM output waveform obtained in Proteus software. It indicates 10% duty cycle. For each
further pressing of PWM button the speed of the motor decreases by 10%.Corresponding change in duty cycle can be
observed in the above simulation diagram.
VIII. CONCLUSION
The proposed research work will make a prototype hardware model where the PWM technique has been used to control
the speed of dc motor. By variation in duty cycle, applied voltage varies therefore speed of dc motor can be
controlled.PWM duty cycle control techniques enable greater efficiency of the DC motor.
IX. ACKNOWLEDGEMENT
First and foremost I take this opportunity to express my deepest sense of gratitude to my guide Mr. Absal Nabi for his
able guidance during my project work. This project would not have been possible without his help and the valuable
time that he has given me at his busy schedule. I would also like to extend my gratitude to my friends and senior
students of this department who have always encouraged and supported me in doing my work. Last but not the least I
would like to thank all the staff members of Department of Electrical Engineering who have been very cooperative with
us.
REFERENCES
[1] H. Chen; J. Zhang,”Study of embedded system experimental platform”Consumer Electronics, Communications and Networks (CECNet), 2012
2nd International Conference on 2012 Pages: 1317 – 1320,2012.
[2] J. Holtz, “Pulsewidth modulation-a survey,” IEEE Trans. on Industry Electronics, Vol. 39, No. 5, 1992
[3] Devika R. Yengalwar, Samiksha S. Zade, Dinesh L. Mute “Four Quadrant Speed Control Of Dc Motor Using Chopper” International Journal
Of Engineering Sciences & Research Technology,vol. 4 issue 2, ISSN: 2277-9655,pp 401-406,February, 2015
[4] M. K. Yoong, Y. H. Gan, G. D. Gan, C. K. Leong, Z. Y. Phuan, B.K. Cheah, and K. W. Chew, “Studies of regenerative braking in elec-tric
vehicle,” in.Proc. IEEE Conf. Sustainable Utilization DevelopmentEng. Technol.,Malaysia, , pp. 40–45, Nov. 2010.
[5] Y. S. E. Ali, S. B. M. Noor, S. M. Uashi and M. K Hassan” MicrocontrollerPerformance for DC Motor Speed Control” O-7803-8208,2003
IEEE.
[6] R. Krishnan, S.-Y. Park, and K. Ha, “Theory and operation of a four-quadrant switched reluctance motor drive with a single
controllableswitch—the lowest cost four-quadrant brushless motor drive,”IEEETrans. Ind. Appl., vol. 41, no. 4, pp. 1047–1055, 2005.

Copyright to IJAREEIE DOI:10.15662/IJAREEIE.2016.0504038 2464

 Case Study
Amiko’s Respiro smart inhaler helps
asthma sufferers breathe easier

Goal health, and analyzing the data we collect, we can help

millions of asthma sufferers effectively control their
Amiko develops artificial intelligence (AI)-powered sensors disease.”
as add-ons to standard inhalers to improve asthma
treatment. These smart sensors must be low-powered,
scalable, and cost-efficient to work with a patient-facing
app on a connected platform.

Solution

At the core of Amiko’s Respiro sensor module is the Arm

Cortex-M processor, chosen for its low-power processing,
machine learning capabilities, and cost efficiency.

Benefits

• Processing takes place securely on the device.

• No need to connect to the cloud.
• Low-powered Bluetooth connectivity to Optimal Power Consumption
smartphone app.
• Processor efficiency helps extend battery life. Respiro uses smart add-on sensors in modules designed to
fit standard inhalers. Since these modules use ML to track
AI-Based Technology Added to Traditional and report on inhalation technique, flow rate, volume and
Devices for Improved Respiratory Care other parameters, Amiko needed a processor that would
allow intelligence and connectivity in the sensor.
Asthma affects millions of people around the world,
“We chose the Arm Cortex-M processor because of its low-
causing about 250,000 deaths each year, according to the
power processing and machine learning capabilities,”
World Health Organization. Treatment using traditional
Macchi explains. “We needed a cost-efficient and scalable
inhalers helps patients immensely, but no matter how easy
design that doesn’t rely on a connection to the cloud. Plus,
inhalers are to use, it’s almost impossible to tell for sure
the low power consumption of the Cortex-M helps extend
whether they’re being used properly, or whether one
the sensor battery life. These are extremely important
prescription works better than another.
features in a real-world patient setting.”
Amiko is developing innovative asthma management tools
The Respiro uses ML to interpret vibration data from the
to help patients better manage the disease, and potentially
inhaler. The sensor is trained to recognize the patient’s
save lives. Its flagship product, Respiro, is a system that
breathing pattern and inhalation time, and can calculate
uses artificial intelligence and machine learning (ML) in
important parameters such as lung capacity and inhalation
medical sensors connected to other health tools and
technique.
technologies to track key respiratory data.

“The processing power of the Arm Cortex-M processor

“Our mission is to transform respiratory care through
allows us to run real-time machine learning algorithms that
advanced AI sensor technologies,” says Duilio Macchi,
recognize behavior patterns and interpret data in the
Amiko CEO. “By monitoring medication use and patient
sensor module itself,” Macchi says. “There’s no need to
wait on backend infrastructure to process detailed sensor
data. When the user presses the trigger, the breath data
pattern is instantly recognized, and the module provides
low-latency, private user feedback.”

Flexibility to Scale

The Respiro sensor is bundled with an app that the patient

installs on their smartphone. The sensor collects inhaler
use data without disrupting the medication delivery
pathway, and sends data and private user feedback to the
app via Bluetooth Low Energy.

Where required, a professional dashboard offers clinicians

a suite of applications, remote monitoring tools, artificial
intelligence-enabled therapy suggestions, and data
analytics. This information helps them coach patients and
offer support, while direct care givers can see the actual
dose and its efficacy.

With rapid access to all information related to the asthma

and its treatment, healthcare professionals can make
accurate, smart decisions and personalize regimens to the
needs of their patients.

“These powerful machine learning algorithms, deployed on

energy-efficient, low-cost, Arm microcontrollers, let us
develop respiratory care technologies that allow doctors to
effectively treat asthma and improve the quality of their
patients’ lives,” Macchi says. “We also have the flexibility to
add new features, and are already looking at ways to
deliver even more innovative connected healthcare
solutions.”

www.arm.com/markets/artificial-intelligence

All brand names or product names are the property of their respective holders. Neither the whole nor any part of the information contained in, or the product described in,
this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document
is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given in good faith. All warranties implied
or expressed, including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded. This document is intended only to provide information
to the reader about the product. To the extent permitted by local laws Arm shall not be liable for any loss or damage arising from the use of any information in this document
or any error or omission in such information.

© Arm Ltd.2018
 Case Study:
Industrial Process Controller
MCU and RTC Power Backup

Case Study Background

One of Cymbet’s Industrial Process Controls customers is designing a new embedded

systems–based control system for a manufacturing assembly line and needs power
holdover for MCU and RTC data retention. The Industrial controller is using a Texas
Instruments MSP430x22x4 microcontroller with an on-board supply supervisor
capability. This MSP430 MCU has ultralow power Standby Mode of 700 nanoamps and
Off Mode RAM Retention of 100 nanoamps. This MCU also has a very low power LF
Oscillator and an ultrafast wake-up from Standby Mode in less than 1 microsecond.
They are using the 38 pin DA package. The data sheet for this MSP430 can be found
at www.ti.com/lit/ds/symlink/msp430f2274.pdf.

Figure 1: Industrial Controller Embedded System requiring Time Retention

Project Design Requirements

The Industrial Process Control embedded system design team requirements were:

1. Need to provide power back-up for an MSP430 microcontroller in the event of a main
power failure
2. Need to back-up the MCU RAM memory for 10 days
3. Need to back-up the MCU in Standby Mode (VLO) for 7 days
4. Need to back up the MCU Real-time clock operation for 3 days
5. Battery must be rechargeable
6. Battery must have less than 2% self discharge per year,
7. Must never have to change the battery
8. Control system product with integrated battery must be able to be shipped via air
9. Battery must be RoHS and WEEE compliant
10. Must have a small device footprint
11. Must use surface mount technology and reflow solder for assembly.

©2011 Cymbet Corporation www.cymbet .com Page 1

CS-72-03.1
 Case Study:
Industrial Process Controller MCU Backup
Design Solution

The Industrial Process Controls design team implemented the EnerChip™ CC

CBC3150 solid state battery with integrated power management to meet their design
requirements for power back-up of the real time clock function in the MCU.

Many systems utilizing microcontrollers and/or real time clock chips require non-
volatile date retention and/or real-time clock operation in the event of main power
interruption. Normally, this is accomplished with the use of a supply supervisory
circuit coupled with a backup power source such as a coin cell or supercapacitor.
When main power is interrupted - as during line power outages or when the main
battery is removed for recharging or replacement - the backup power source provides
enough energy to maintain the data in the embedded SRAM or keep the internal real-
time clock operational. Many MCUs have an internal supply supervisor circuit that can
be used to control the switchover function from main power to auxiliary power. When
the supply voltage threshold level is reached during power droop or complete power
loss, the MCU can be programmed to generate an internal interrupt that places the
MCU into a low power state for maximum run time from the backup power source.

The EnerChip CC is a surface mount device that co-packages a rechargeable solid

state battery with integrated battery management. The EnerChip CC performs the
charge control, discharge control, threshold voltage detection, and supply supervisory
functions all in one low profile package. It operates over the range of 2.5V to 5.5V.

Using the EnerChip CC to provide power back-up to the Microcontroller is a very

simple circuit as is shown in the following schematic diagram example:

Figure2: Microcontroller RTC power backup example using EnerChip CC CBC3150

©2011 Cymbet Corporation www.cymbet.com Page 2

CS-72-03.1
 Case Study:
Industrial Process Controller MCU Backup
Technical design information for applications such as the Industrial Process Controls
embedded system can be found in the following Cymbet.com Design Center website
pages:

• Application Notes for Power Backup of several different Microcontrollers are at

http://www.cymbet.com/design-center/microcontroller-back-up.php

 TI MSP430
 Freescale HC
 Atmel PicoPower AVR
 Microchip PIC
 ST Micro ST62
 EM Microelectronics EM

• Application Notes for Real Time Clocks are at http://www.cymbet.com/design-

center/rtc-backup.php

 TI BQ32000
 Epson RX-8564
 Dallas-Maxim DS1340
 Dallas-Maxim DS1390
 Micro Crystal RV-2123
 Microchip MDP79410
 NXP PCF8523

Evaluating Cymbet EnerChip Solutions for Your Next Project

This Case Study demonstrates how the design team in this industrial process controls
company used EnerChip Solid State Batteries to improve the capabilities and
competitiveness of their new assembly system. You can use EnerChip devices to
reduce costs and improve the functionality of your products as well. Cymbet provides
a set of evaluation kits that can be utilized to accelerate new product development
schedules. For Power Back-up designs an ideal evaluation kit is the EnerChip CC RTC
Power Back-up CBC-EVAL-06 kit. This easy to use USB based stick as shown in
Figure 3, has a Micro Crystal RV-2123 Real Time Clock chip and an EnerChip CC
CBC3112 solid state battery.

For additional information call Cymbet Applications Engineering at +1-763-633-1780

or use the Support form on Cymbet.com.

©2011 Cymbet Corporation www.cymbet.com Page 3

CS-72-03.1