DSD Book

Unit-9 Digital Design
Unit 11 Some VHDL Programs

Example 11.1
For 2-to-4 Decoder write down :
(a) Behavior Model
(b) Dataflow Model
(c) Structural Model
Solution :
Circuit diagram of 2-to-4 Decoder is shown in figures 11.1, waveforms
are shown in figure 11.2 and truth table is shown in Table 11.1.
S0 S1
I0 I1
EN
A0 Z(0)
A1 Z(1)
A2 Z(2)
A3 Z(3)
Figure 11.1 Circuit Diagram of 2-of-4 Decoder.
Input’s Output’s
EN S1 S0 Z(0) Z(1) Z(2) Z(3)
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
Table 11.1 Truth table of 2-to-4 Decoder
226
(a) Behavior model of 2-to-4 Decoder

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY decoder_2_to_4 IS
port(s0,s1,en:in bit; z:out bit_vector(0 to 3));
END decoder_2_to_4;
ARCHITECTURE decoder_2_to_4_behaviour OF decoder_2_to_4 IS

BEGIN
process(s0,s1,en)
variable s0bar,s1bar:bit;
begin
s0bar:=not s0;
s1bar:=not s1;
if en='1'then
z(0)<=s0bar and s1bar;
z(1)<=s0 and s1bar;
z(2)<=s0bar and s1;
z(3)<=s0 and s1;
else
z<="0000";
end if;
end process;
END decoder_2_to_4_behaviour;
(b) Dataflow model of 2-to-4 Decoder
LIBRARY ieee;
END decoder_2_to_4;
ARCHITECTURE decoder_2_to_4_dataflow OF decoder_2_to_4 IS

signal s0bar,s1bar:bit;
BEGIN
s0bar<=not s0;
s1bar<=not s1;
227
z(0)<=s0bar and s1bar and en;

z(1)<=s0 and s1bar and en;
z(2)<=s0bar and s1 and en;
z(3)<=s0 and s1 and en;
END decoder_2_to_4_dataflow;
(c) Structural model of 2-to-4 Decoder
LIBRARY ieee;
END decoder_2_to_4;
--
ARCHITECTURE decoder_2_to_4_structural OF decoder_2_to_4 IS
component and3
port(in1,in2,in3:in bit; out1:out bit);
end component;
component inv
port(in4:in bit; out2:out bit);
end component;
signal s0bar,s1bar:bit;
BEGIN
a0:and3 port map(s0bar,s1bar,en,z(0));

a1:and3 port map(s0,s1bar,en,z(1));
a2:and3 port map(s0bar,s1,en,z(2));
a3:and3 port map(s0,s1,en,z(3));
inv0:inv port map(s0,s0bar);
inv1:inv port map(s1,s1bar);
END decoder_2_to_4_structural;
Example 11.2
For a Full Adder write down
(a) Behavior Model
228
(b) Dataflow Model

Solution :
Circuit diagram of Full Adder is shown in figures 11.3, waveforms are
shown in figure 11.4 and truth table is shown in Table 11.2.
A
B X0 S
Cin
A0
A1 O0 C
A2
Figure 11.3 Circuit Diagram of Full Adder
Input’s Output’s
A B Cin S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 11.2 Truth table of Full Adder
229
(a) Behavior model of Full Adder
LIBRARY ieee;
ENTITY full_adder IS
port(a,b,cin:in bit; s,c:out bit);
END full_adder;
ARCHITECTURE full_adder_behaviour OF full_adder IS

BEGIN
process(a,b,cin)
begin
s<=a xor b xor cin;
c<=(a and b)or(a and cin)or(b and cin);
end process;
END full_adder_behaviour;
(b) Dataflow model of Full Adder
LIBRARY ieee;
END full_adder;
--
ARCHITECTURE full_adder_dataflow OF full_adder IS
BEGIN
s<=a xor b xor cin;
c<=(a and b)or(a and cin)or(b and cin);
END full_adder_dataflow;
(c) Structural model of Full Adder
LIBRARY ieee;
230
END full_adder;
--
ARCHITECTURE full_adder_structure OF full_adder IS
component xor3
end component;
component and2
port(in4,in5:in bit; out2:out bit);
end component;
component or3
end component;
signal x,y,z:bit;
begin
x0:xor3 port map(a,b,cin,s);
a0:and2 port map(a,b,x);
a1:and2 port map(b,cin,y);
a2:and2 port map(a,cin,z);
o0:or3 port map(x,y,z,c);
END full_adder_structure;
Example 11.3
For a Multiplexer of size 4-to-1 write down
(a) Behavior Model
(b) Dataflow Model
Solution :
Circuit diagram of 4-to-1 Multiplexer is shown in figures 11.5,
waveforms are shown in figure 11.6 and truth table is shown in Table
11.3.
231
S0 S1
I0 I1
S0 BAR S1 BAR
10 U
A0
11 A1 V
O0
12 A2 W
13 X
A3
Figure 11.5 Circuit Diagram of 4-to-1 Multiplexer
Select Input’s Output

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Table 11.3 Truth table of 4-to-1 Multiplexer
(a) Behavior model of 4-to-1 Multiplexer
LIBRARY ieee;
ENTITY mux_4to1 IS
port(i0,i1,i2,i3,s0,s1:in bit; y:out bit);
END mux_4to1;
232
ARCHITECTURE mux_behaviour OF mux_4to1 IS

BEGIN
PROCESS(i0,i1,i2,i3,s0,s1)
BEGIN
IF (s1=’0’ and s0=’0’) THEN
y<= i0;
ELSIF (s1=’0’ and s0=’1’) THEN
y<= i1;
y<= i2;
y<= i3;
END IF;
END PROCESS;
END mux_behaviour;
(b) Dataflow model of 4-to-1 Multiplexer
LIBRARY ieee;
ENTITY mux_4to1 IS
END mux_4to1;
ARCHITECTURE mux_dataflow OF mux_4to1 IS

BEGIN
Y<=i0 when s1=’0’ and s0=’0’ else
i1 when s1=’0’ and s0=’1’ else
i2 when s1=’1’ and s0=’0’ else
i3;
END mux_dataflow;
(c) Structural model of 4-to-1 Multiplexer
LIBRARY ieee;
ENTITY mux IS
233
END mux;
ARCHITECTURE mux_structure OF mux IS

component and3
end component;
component or4
port(in4,in5,in6,in7:in bit; out2:out bit);
end component;
signal s0bar,s1bar,u,v,w,x:bit;
BEGIN
a0:and3 port map(i0,s1bar,s0bar,u);

a1:and3 port map(i1,s1bar,s0,v);
a2:and3 port map(i2,s1,s0bar,w);
a3:and3 port map(i3,s1,s0,x);
or0:or4 port map(u,v,w,x,y);
END mux_structure;
Example 11.4
For a BCD-to-Seven Segment Decoder write down
(a) Behavior Model
(b) Dataflow Model
Solution :
Circuit diagram of BCD-to-Seven Segment Decoder is shown in figures
11.7, waveforms are shown in figure 11.8 and truth table is shown in
Table 11.4.
234
a
A
b
B c
a
d
BCD-to-Seven
C Segment Decoder f b
e
f g
D e c
g
d
Figure 11.7 Circuit Diagram of BCD-to-Seven Segment Decoder
BCD Input’s Output’s

ABCD a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 0
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
Table 11.4 Truth table of BCD-to-Seven Segment Decoder
(a) Behavior model of BCD-to-Seven Segment Decoder
LIBRARY ieee;
235
ENTITY seven_seg_decoder IS
port(bcd:in bit_vector(0 to 3); led:out bit_vector(0 to 6));
END seven_seg_decoder;
ARCHITECTURE seven_behaviour OF seven_seg_decoder IS

BEGIN
process(bcd)
begin
case bcd is
when"0000"=>
led<="1111110";
when"0001"=>
led<="0110000";
when"0010"=>
led<="1101101";
when"0011"=>
led<="1111001";
when"0100"=>
led<="0110011";
when"0101"=>
led<="1011011";
when"0110"=>
led<="1011110";
when"0111"=>
led<="1110000";
when"1000"=>
led<="1111111";
when “1001”=>
led<="1111011";
when others=>
led<="1111111";
end case;
end process;
END seven_behaviour;
(b) Dataflow model of BCD-to-Seven Segment Decoder
LIBRARY ieee;
236
ARCHITECTURE seven_dataflow OF seven_seg_decoder IS

BEGIN
Led<=“1111110” when bcd=”0000” else
“0110000” when bcd=”0001” else
“1101101” when bcd=”0010” else
“1111001” when bcd=”0011” else
“0110011” when bcd=”0100” else
“1011011” when bcd=”0101” else
“1011110” when bcd=”0110” else
“1110000” when bcd=”0111” else
“1111111” when bcd=”1000” else
“1111011” when bcd=”1001” else
“ 1111111” when others;
END seven_dataflow;
(c) Structural model of BCD-to-Seven Segment Decoder
LIBRARY ieee;
--
ARCHITECTURE seven_structure OF seven_seg_decoder IS
Component decoder
Port(input:in bit_vector(0 to 3); output:out bit_vector(0 to 6));
End component;
Begin
Dec1:decoder port map(bcd,led);
END seven_structure;
237
Example 11.5
For a 4-bit Parallel in Parallel Out Register write down
(a) Behavior Model
(b) Dataflow Model
Solution :
Block diagram of 4-bit Parallel in Parallel out Register is shown in
figures 11.9 and waveforms are shown in figure 11.10.
Parallel Input's
D(0) D(1) D(2) D(3)
PR
D Q D Q D Q D Q
FF0 FF1 FF2 FF3

CLK
CR
Parallel Output's
Figure 11.9 Block diagram of 4-bit Parallel In Parallel Out Register

(or Parallel load Register)
(a) Behavior model of 4-bit Parallel In Parallel Out Register
LIBRARY ieee;
ENTITY pipo IS
port(d:in bit_vector(0 to 3);clk,pr,cr:in bit; q:out bit_vector(0 to 3));
END pipo;
238
ARCHITECTURE pipo_behaviour OF pipo IS

BEGIN
process(pr,cr,clk)
begin
if (pr='0' and cr='1') then
q<="1111";
elsif (pr='1' and cr='0') then
q<="0000";
elsif (pr='0'and cr='0')then
q<="1111";
elsif (pr='1'and cr='1' and clk='0' and clk'event) then
q<=d;
end if;
end process;
END pipo_behaviour;
(b) Dataflow model of 4-bit Parallel In Parallel Out Register
LIBRARY ieee;
ENTITY pipo IS
port(d:in bit_vector(0 to 3); pr,cr,clk:in bit; q:out bit_vector(0 to 3));
END pipo;
ARCHITECTURE pipo_dataflow OF pipo IS

BEGIN
q<="1111" when pr='0' and cr='1' else
"0000" when pr='1' and cr='0' else
d when pr='1' and cr='1' and clk='0' and clk'event;
END pipo_dataflow;
(c) Structural model of 4-bit Parallel In Parallel Out Register
LIBRARY ieee;
ENTITY pipo IS
239
port(d:in bit_vector(0 to 3); pr,cr,clk:in bit; q:out bit_vector(0 to 3));

END pipo;
ARCHITECTURE pipo_structure OF pipo IS

component dff
end component;
--in1=d,in2=pr,in3=cr,in4=clk,out1=q
BEGIN
d0:dff port map(d(0),pr,cr,clk,q(0));
END pipo_structure;
Example 11.6
For a 4-bit Serial In Serial Out Register write down
(a) Behavior Model
(b) Dataflow Model
Solution :
Block diagram of 4-bit Serial in Serial out Register is shown in figures
11.11 and waveforms are shown in figure 11.12.
PR
Q(0) D Q Q(1) D Q Q(2) D Q

D Q
D
(serial i/p) FF1 FF2 FF3
FF0
CLK
CR
Z(O/P)
240
Figure 11.11 Block Diagram of 4-bit Serial In Serial Out Register

(or Right Shifter)
(a) Behavior model of 4-bit Serial In Serial Out Register

LIBRARY ieee;
ENTITY siso IS
port(d,clk,pr,cr:in bit; z:out bit);
END siso;
ARCHITECTURE siso_behaviour OF siso IS

signal q(0),q(1),q(2):bit;
BEGIN
process(clk,pr,cr)
begin
if ( pr='1'and cr='1' and clk='0' and clk'event) then
q(0)<=d;
q(1)<=q(0);
q(2)<=q(1);
z<=q(2);
q(0)<='1';
q(1)<='1';
q(2)<='1';
z<='1';
q(0)<='0';
q(1)<='0';
q(2)<='0';
z<='0';
q(0)<='1';
q(1)<='1';
q(2)<='1';
z<='1';
end if;
end process;
END siso_behaviour;
241
(b) Dataflow model of 4-bit Serial In Serial Out Register

LIBRARY ieee;
ENTITY siso IS
port(pr,cr,clk,d:in bit; z:out bit);
END siso;
ARCHITECTURE siso_dataflow OF siso IS

signal q:bit_vector(0 to 3);
BEGIN
q<=d & q(0) & q(1) & q(2) when pr='1' and cr='1' and clk='0' and
clk'event else
"1111" when pr='0' and cr='1';
z<=q(3);
END siso_dataflow;
(c) Structural model of 4-bit Serial In Serial Out Register

LIBRARY ieee;
ENTITY siso IS
port(d,clk,pr,cr:in bit; z:out bit);
END siso;
ARCHITECTURE siso_structure OF siso IS

component dff
end component;
signal q:bit_vector(0 to 2);
BEGIN
d0:dff port map(d,pr,cr,clk,q(0));
d1:dff port map(q(0),pr,cr,clk,q(1));
d3:dff port map(q(2),pr,cr,clk,z);
END siso_structure;
242
Example11.7
For a 4-bit Serial In Parallel Out Register write down
(a) Behavior Model
(b) Dataflow Model
Solution :
Block diagram of 4-bit Serial in Parallel out Register is shown in figures
11.13 and waveforms are shown in figure 11.14.
PR
D D D D
D
Q Q Q
(serial i/p) Q
FF0 FF1 FF2 FF3

CLK
CR
Q(0) Q(1) Q(2) Q(3)
Parallel Output's
Figure 11.13 Block Diagram o[f 4-bit Serial In Parallel Out Register
(a) Behavior model of 4-bit Serial In Parallel Out Register
LIBRARY ieee;
ENTITY sipo IS
port(d,pr,cr,clk:in bit; q:buffer bit_vector(0 to 3));
END sipo;
--
243
ARCHITECTURE sipo_behavioural OF sipo IS

BEGIN
process (pr,cr,clk)
begin
if (pr='1' and cr='1' and clk='0' and clk'event) then
q(0)<=d;
q(1)<=q(0);
q(2)<=q(1);
q(3)<=q(2);
elsif (pr='1' and cr='0')then
q(0)<='0';
q(1)<='0';
q(2)<='0';
q(3)<='0';
q(0)<='1';
q(1)<='1';
q(2)<='1';
q(3)<='1';
q(0)<='1';
q(1)<='1';
q(2)<='1';
q(3)<='1';
end if;
end process;
END sipo_behavioural;
(b) Dataflow model of 4-bit Serial In Parallel Out Register
LIBRARY ieee;
ENTITY sipo IS
port(d,pr,cr,clk:in bit; q:buffer bit_vector(0 to 3));
END sipo;
--
244
ARCHITECTURE sipo_dataflow OF sipo IS

BEGIN
q<= "0000" when(pr='1' and cr='0')else
"1111" when(pr='0' and cr='1')else
d & q(0) & q(1) & q(2)when(pr='1' and cr='1' and clk='0' and
clk'event);
END sipo_dataflow;
(c) Structural model of 4-bit Serial In Parallel Out Register
LIBRARY ieee;
ENTITY sipo IS
port(d,clk,pr,cr:in bit; q:buffer bit_vector(0 to 3));
END sipo;
ARCHITECTURE sipo_structure OF sipo IS

component dff
end component;
BEGIN
d0:dff port map(d,pr,cr,clk,q(0));

END sipo_structure;
Example 11.8
For a 3-bit UP Counter write down
(a) Behavior Model
(b) Dataflow Model
245
Solution :
Block diagram of 3-bit UP Counter is shown in figures 11.15 and
waveforms are shown in figure 11.16.
PR
T Q T Q T Q
FF0 FF1 FF2

CLK
CR
Q(0) Q(1) Q(2)
LSB Parallel Output’s MSB
Figure 11.15 A 3-bit UP Counter

*T input’s of T flip-flop’s is always set to ‘1’.
(a) Behavior model of 3-bit UP Counter
LIBRARY ieee;
ENTITY counter IS
port(pr,cr,clk,t:in bit; q:inout bit_vector(0 to 2));
END counter;
--
ARCHITECTURE behaviour OF counter IS
function "+"(a,b:bit_vector(0 to 2))return bit_vector is
variable cout:bit;
variable cin:bit:='0';
246
variable sum:bit_vector(0 to 2):="000";

begin
for i in 0 to 2 loop
cout:=(a(i) and b(i)) or (b(i) and cin) or (a(i) and cin);
sum(i):=a(i) xor b(i) xor cin;
cin:=cout;
end loop;
return sum;
end "+";
BEGIN
process(clk,pr,cr)
begin
if(pr='0' and cr='1')then
q<="111";
elsif(pr='1' and cr='0')then
q<="000";
elsif(pr='1' and cr='1'and clk='0' and clk'event)then
q<=q + "100";
end if;
end process;
END behaviour;
(b) Dataflow model of 3-bit UP Counter
LIBRARY ieee;
ENTITY counter_up IS
END counter_up;
--
ARCHITECTURE dataflow OF counter_up IS
-- function for addition of two bit arrays
variable cout:bit;
begin
247

cin:=cout;
end loop;
return sum;
end "+";
BEGIN
q<="111" when(pr='0' and cr='1')else

q + "100"when(pr='1' and cr='1'and clk='0' and clk'event);
end dataflow;
(c) Structural model of 3-bit UP Counter
LIBRARY ieee;
ENTITY counter_up IS
END counter_up;
--
ARCHITECTURE counter_up_structure OF counter_up IS
component tff
port(in1,in2,in3,in4:in bit; out1:inout bit);
end component;
BEGIN
ff0:tff port map(t,clk,pr,cr,q(0));
ff1:tff port map(t,q(0),pr,cr,q(1));
ff2:tff port map(t,q(1),pr,cr,q(2));
END counter_up_structure;
Example 11.9
For a 3-bit DOWN Counter write down
(a) Behavior Model
248
(b) Dataflow Model

Solution :
Block diagram of 3-bit DOWN Counter is shown in figures 11.17 and
PR
T Q T Q T Q
S1 S2
FF0 FF1 FF2
CLK
Q Q Q
CR
Q(0) Q(1) Q(2)
LSB Parallel Output’s MSB
Figure 11.17 A 3-bit DOWN Counter
(a) Behavior model of 3-bit DOWN Counter
LIBRARY ieee;
ENTITY counter_down IS
END counter_down;
--
ARCHITECTURE behaviour OF counter_down IS
249
function "-"(a,b:bit_vector(0 to 2))return bit_vector is

variable cout:bit;
variable dif:bit_vector(0 to 2):="000";
begin
cout:=((not a(i)) and b(i)) or (b(i) and cin) or ((not a(i)) and cin);
dif(i):=a(i) xor b(i) xor cin;
cin:=cout;
end loop;
return dif;
end "-";
BEGIN
process(clk,pr,cr)
variable S1,S2 : bit;
begin
S1:=not q(0);
S2:=not q(1);
q<="111";
q<="000";
if (clk='0' and clk'event)then
q<=q - "100";
end if;
end if;
end process;
END behaviour;
(b) Dataflow model of 3-bit DOWN Counter
LIBRARY ieee;
END counter_down;
--
ARCHITECTURE dataflow OF counter_down IS
250
-- function for subtraction of two bit arrays

variable cout:bit;
begin
cin:=cout;
end loop;
return dif;
end "-";
signal S1,S2 : bit;
BEGIN
S1<=not q(0);
S2<=not q(1);
q - "100"when(pr='1' and cr='1'and clk='0' and clk'event);
end dataflow;
(c) Structural model of 3-bit DOWN Counter
LIBRARY ieee;
port(t,clk,pr,cr:in bit; q:out bit_vector(0 to 2));
END counter_down;
--
ARCHITECTURE counter_down_structure OF counter_down IS
component tff
port(in1,in2,in3,in4:in bit; z,zbar:buffer bit);
end component;
signal s1,s2:bit;
BEGIN
t0:tff port map(t,clk,pr,cr,q(0),s1);
251
t1:tff port map(t,s1,pr,cr,q(1),s2);

t2:tff port map(t,s2,pr,cr,q(2),open);
END counter_down_structure;
Example 11.10
For a 3-bit UP/DOWN Counter write down
(a) Behavior Model
(b) Dataflow Model
Solution :
Block diagram of 3-bit DOWN Counter is shown in figures 11.19 and
LSB Parallel Output's MSB
Q(0) Q(1) Q(2)
T
UP
PR
A1 S3 A3 S7
T Q T Q T Q
FF0 S4 FF1 S8 FF2

CLK
S1 S5
Q A0 Q A2 Q
CR
DOWN
Figure 11.19 A 3-bit UP/DOWN Counter (Asynchronous)
When UP = ‘1’, circuit works as UP counter.

When DOWN = ‘1’, circuit works as DOWN counter.
(a) Behavior model of 3-bit UP/DOWN Counter
LIBRARY ieee;
252
ENTITY counter_updown IS
port(pr,cr,up,dn,clk,t:in bit; q:inout bit_vector(0 to 2));
END counter_updown;
--
ARCHITECTURE behaviour OF counter_updown IS
variable cout:bit;
begin
cin:=cout;
end loop;
return sum;
end "+";

variable cout:bit;
begin
cin:=cout;
end loop;
return dif;
end "-";
BEGIN
process(clk,pr,cr)
variable s1,s2,s3,s4,s5,s6,s7,s8:bit;
begin
s1:=not q(0);
253
s2:=up and q(0);

s3:=s1 and dn;
s4:=s2 or s3;
s5:=not q(1);
s6:=up and q(1);
s7:=s5 and dn;
s8:=s6 or s7;

q<="111";
q<="000";
elsif(pr='1' and cr='1'and up='1'and dn='0' and clk='0' and
clk'event)then
q<=q + "100";
elsif(pr='1' and cr='1'and up='0'and dn='1' and clk='0' and
clk'event)then
q<=q - "100";
end if;
end process;
end behaviour;
(b) Dataflow model of 3-bit UP/DOWN Counter
LIBRARY ieee;
ENTITY counter_updown IS
port(pr,cr,up,dn,clk,t:in bit; q:inout bit_vector(0 to 2));
END counter_updown;
--
ARCHITECTURE dataflow OF counter_updown IS
variable cout:bit;
begin
254

cin:=cout;
end loop;
return sum;
end "+";

variable cout:bit;
begin
cin:=cout;
end loop;
return dif;
end "-";
signal s1,s2,s3,s4,s5,s6,s7,s8:bit;
BEGIN
begin
s1<=not q(0);
s2<=up and q(0);
s3<=s1 and dn;
s4<=s2 or s3;
s5<=not q(1);
s6<=up and q(1);
s7<=s5 and dn;
s8<=s6 or s7;

q + "100"when(pr='1' and cr='1'and up='1'and dn='0' and clk='0' and
clk'event)else
q - "100"when(pr='1' and cr='1'and up='0'and dn='1' and clk='0' and
clk'event);
end dataflow;
255
(c) Structural model of 3-bit UP/DOWN Counter
LIBRARY ieee;
ENTITY counter_up_down IS
port(t,clk,pr,cr,up,dn:in bit; q:buffer bit_vector(0 to 2));
END counter_up_down;
ARCHARCHITECTURE counter_up_down_structure OF
counter_up_down ISITECTURE counter_up_down_structure OF
counter_up_down IS
component tff
port(in1,in2,in3,in4:in bit; z,zbar:buffer bit);
end component;
component and2
end component;
component or2
end component;
signal s1,s2,s3,s4,s5,s6,s7,s8:bit;
BEGIN
t0:tff port map(t,clk,pr,cr,q(0),s1);
t1:tff port map(t,s4,pr,cr,q(1),s5);
t2:tff port map(t,s8,pr,cr,q(2),open);
a0:and2 port map(s1,dn,s2);
a1:and2 port map(q(0),up,s3);
a2:and2 port map(s5,dn,s6);
a3:and2 port map(q(1),up,s7);
or0:or2 port map(s2,s3,s4);
or1:or2 port map(s6,s7,s8);
END counter_up_down_structure;
256
Example 11.11
For a ALU(74381) write down Behavior Model.
Solution :
Block diagram of a ALU (74381) is shown in figures 11.21, waveforms
are shown in figure 11.22 and Function table is shown in Table 11.5.
Select Input Operation Output

S2 S1 S0 F
0 0 0 CLEAR 0000
0 0 1 Q–P Q–P
0 1 0 P–Q P–Q
0 1 1 ADD P+Q
1 0 0 XOR P XOR Q
1 0 1 OR P OR Q
1 1 0 AND P AND Q
1 1 1 PRESET 1 1 1 1
Table 11.5 Function Table of ALU(74381)
P(3)
P(2)
P Input
(4-bit) P(1)
P(0) F(3)
ALU
F(2) F Output
74381
F(1) (4-bit)
Q(3)
F(0)
Q(2)
Q Input
Q(1)
(4-bit)
Q(0)
S2 S1 S0
Select Line (4 bit)
Figure 11.21 Block Diagram of ALU(74381)
257
Behavior Model of ALU(74381) :
LIBRARY ieee;
ENTITY alu IS
port(p,q:in bit_vector(0 to 3); s:in bit_vector(0 to 2); f:out bit_vector(0
to 3));
END alu;
--
ARCHITECTURE behavior OF alu IS
variable cout:bit;
begin
cin:=cout;
end loop;
return sum;
end "+";

variable cout:bit;
begin
cin:=cout;
end loop;
return dif;
end "-";
begin
258
process(p,q,s)
begin
case s is
when "000"=>
f<="0000";
when "001"=>
f<= q - p ;
when "010"=>
f<= p - q ;
when "011"=>
f<= p + q ;
when "100"=>
f<=p xor q;
when "101"=>
f<=p or q;
when "110"=>
f<=p and q;
when"111"=>
f<="1111";
end case;
end process;
END behavior;
Example 11.12
For a D flip-flop write down Behavior Model.
Solution :
A D flip flop is shown in figures 11.23, waveforms are shown in figure
11.24 and Truth table is shown in Table 11.6.
259
PR
Input D Q Q
FF
Clk
CR
Figure 11.23 D flip-flop
PR CR D(i/p) Output
Q(t + 1)
0 0 X 1
0 1 X 1
1 0 X 0
1 1 0 0
1 1 1 1
Table 11.6 Truth table of D flip-flop
Boolean Expression of D flip-flop-

Q(t+1) = D
Behavior Model of D flip-flop :

LIBRARY ieee;
ENTITY dff IS
port(clk,pr,cr,d:in bit; q:out bit);
END dff;
260
ARCHITECTURE dff_behaviour OF dff IS

begin
process(clk,pr,cr)
begin
if (pr ='0' and cr ='1') then
q<='1';
elsif (pr ='1' and cr ='0') then
q<='0';
elsif (pr ='1' and cr ='1' and clk = '0' and clk'event) then
q<=d;
end if;
end process;
end dff_behaviour;
Example 11.13
For a T flip-flop write down Behavior Model.
Solution :
A D flip flop is shown in figures 11.25, waveforms are shown in figure
11.26 and Truth table is shown in Table 11.7.
PR
Input
T Q
FF
Clk
Q
CR
Figure 11.25 T flip-flop
261
PR CR T(i/p) Output
Q(t + 1)
0 0 X 1
0 1 X 1
1 0 X 0
1 1 0 Q
1 1 1 `Q
Table 11.7 Truth table of T flip-flop
Boolean Expression of T flip-flop-

Q( t + 1) = T Q + TQ
Behavior Model of T flip-flop :

LIBRARY ieee;
ENTITY tff IS
port(clk,pr,cr,t:in bit; q:inout bit; qbar:out bit);
END tff;
ARCHITECTURE tff_behaviour OF tff IS

begin
process(clk,pr,cr)
begin
if (pr ='0' and cr ='1') then
q<='1';
elsif (pr ='1' and cr ='0') then
q<='0';
elsif (pr ='1' and cr ='1' and clk = '0' and clk'event) then
q<=(not t and q) or (not q and t) ;
end if;
end process;
qbar <= not q;
end tff_behaviour;
262

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Unit-9 Digital Design

Unit 11 Some VHDL Programs

Figure 11.1 Circuit Diagram of 2-of-4 Decoder.

(a) Behavior model of 2-to-4 Decoder

ARCHITECTURE decoder_2_to_4_behaviour OF decoder_2_to_4 IS

(b) Dataflow model of 2-to-4 Decoder

ARCHITECTURE decoder_2_to_4_dataflow OF decoder_2_to_4 IS

z(0)<=s0bar and s1bar and en;

(c) Structural model of 2-to-4 Decoder

a0:and3 port map(s0bar,s1bar,en,z(0));

(b) Dataflow Model

Figure 11.3 Circuit Diagram of Full Adder

Table 11.2 Truth table of Full Adder

(a) Behavior model of Full Adder

ARCHITECTURE full_adder_behaviour OF full_adder IS

(b) Dataflow model of Full Adder

(c) Structural model of Full Adder

Figure 11.5 Circuit Diagram of 4-to-1 Multiplexer

Select Input’s Output

Table 11.3 Truth table of 4-to-1 Multiplexer

(a) Behavior model of 4-to-1 Multiplexer

ARCHITECTURE mux_behaviour OF mux_4to1 IS

(b) Dataflow model of 4-to-1 Multiplexer

ARCHITECTURE mux_dataflow OF mux_4to1 IS

(c) Structural model of 4-to-1 Multiplexer

ARCHITECTURE mux_structure OF mux IS

a0:and3 port map(i0,s1bar,s0bar,u);

Figure 11.7 Circuit Diagram of BCD-to-Seven Segment Decoder

BCD Input’s Output’s

Table 11.4 Truth table of BCD-to-Seven Segment Decoder

(a) Behavior model of BCD-to-Seven Segment Decoder

ARCHITECTURE seven_behaviour OF seven_seg_decoder IS

(b) Dataflow model of BCD-to-Seven Segment Decoder

ARCHITECTURE seven_dataflow OF seven_seg_decoder IS

(c) Structural model of BCD-to-Seven Segment Decoder

D(0) D(1) D(2) D(3)

FF0 FF1 FF2 FF3

Figure 11.9 Block diagram of 4-bit Parallel In Parallel Out Register

(a) Behavior model of 4-bit Parallel In Parallel Out Register

ARCHITECTURE pipo_behaviour OF pipo IS

(b) Dataflow model of 4-bit Parallel In Parallel Out Register

ARCHITECTURE pipo_dataflow OF pipo IS

(c) Structural model of 4-bit Parallel In Parallel Out Register

port(d:in bit_vector(0 to 3); pr,cr,clk:in bit; q:out bit_vector(0 to 3));

ARCHITECTURE pipo_structure OF pipo IS

Q(0) D Q Q(1) D Q Q(2) D Q

Figure 11.11 Block Diagram of 4-bit Serial In Serial Out Register

(a) Behavior model of 4-bit Serial In Serial Out Register

ARCHITECTURE siso_behaviour OF siso IS

(b) Dataflow model of 4-bit Serial In Serial Out Register

ARCHITECTURE siso_dataflow OF siso IS

(c) Structural model of 4-bit Serial In Serial Out Register

ARCHITECTURE siso_structure OF siso IS

FF0 FF1 FF2 FF3

Q(0) Q(1) Q(2) Q(3)

(a) Behavior model of 4-bit Serial In Parallel Out Register

ARCHITECTURE sipo_behavioural OF sipo IS

(b) Dataflow model of 4-bit Serial In Parallel Out Register

ARCHITECTURE sipo_dataflow OF sipo IS