DIGITAL ELECTRONICS LAB MANUAL

Prepared by Mr.P.M.Murali, AP/ECE Mr.G.Ramachandran, AP/ECE Mrs.T.Sheela, AP/ECE

II year/III Sem(Common to ECE, CSE, IT), VMKVEC, VMU-SALEM-636308

INDEX

S.NO

DATE

NAME OF THE EXPERIMENT

PAGE NO

MARKS

SIGNATURE

10

11

AND GATE:

OR GATE:

Exp No: 01

Date:

STUDY OF LOGIC GATES AIM: To study about logic gates and verify their truth tables. APPARATUS: Sl.No. 1. 2. 3. 4. 5. 6. 7. THEORY: Logic gates are the basic elements that make up a digital system. The gate is a digital circuit with one or more inputs, but only one output. By connecting the different gates in different ways, we can build circuits that perform arithmetic and other functions. The operation of a logic gate can be easily understood with the help of truth table. A truth table is a table that shows all the input-output possibilities of a logic circuit ie., the truth table indicates the outputs for different possibilities of the inputs. The types of gates available are the AND, OR, NOT, NAND, NOR, exclusive-OR and the exclusive-NOR. Except for the exclusive-NOR gate they are available in monolithic integrated form. COMPONENT IC IC IC IC IC IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7432 IC 7486 IC 7408 IC 7400 IC 7402 QTY. 1 1 1 1 1 1 -

AND gate: The AND gates has two or more inputs. It performs a logical multiplication. The output is HIGH (1), when both the inputs are 1; otherwise the output from the gate is LOW (0). The output from the AND gate is written as A.B.

NOT GATE:

NAND GATE:

OR gate: The OR gates has two or more inputs. It performs a logical addition. The output is HIGH (1), if any of the inputs are 1; the output is LOW (0) if and only if all the inputs are 0. The output from the AND gate is written as A+B.

NOT gate: The NOT gate has only one input. It performs a basic logic function called inversion. The output is HIGH (1), when the input is 0; the output is LOW (0) when the input is 1. The output from the NOT gate is written as A. NAND gate: The NAND gate is a contraction of AND-NOT. It has two or more inputs. The output is HIGH (1), when any of the inputs are 0; the output is LOW (0), if and only if all the inputs are 1. The output from the AND gate is written as (A.B). It is a universal gate.

NOR gate: The NOR gate is a contraction of OR-NOT. It has two or more inputs. The output is HIGH (1), when all inputs are 0; the output is LOW (0), when any of the inputs are 1. The output from the AND gate is written as (A+B). It is a universal gate.

EX-OR gate: The EX-OR gate has two or more inputs. The output is HIGH (1), when odd number of inputs is 1. The output from the AND gate is written as (AB).

NOR GATE:

EXOR GATE:

PROCEDURE: 1. Connections are given as per the logic diagram. 2. Logic inputs are given as per the truth table. 3. Observe the logic output and verify with the truth table.

RESULT :

.. Signature of the staff in charge

HALF ADDER:
TRUTH TABLE:

Inputs A 0 0 1 1
K- MAP SIMPLIFICATION:

Outputs Carry (C) 0 0 0 1 Sum (S) 0 1 1 0

B 0 1 0 1

LOGIC DIAGRAM:

Exp No: 02

Date: DESIGN AND IMPLEMENTATION OF ADDER CIRCUITS USING LOGIC GATES

AIM: To design and construct Half-adder and Full-adder. APPARATUS: Sl.No. 8. 9. 10. 11. 12. 13. COMPONENT IC IC IC IC IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7432 IC 7486 IC 7408 IC 7400 QTY. 1 1 1 1 1 -

THEORY:
HALF ADDER: A half adder has two inputs for the two bits to be added and two outputs one from the sum S and other from the carry c into the higher adder position. Above circuit is called as a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate. FULL ADDER: A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.

11

K-MAP SIMPLIFICATION:

Full Adder using Two Half Adders:

FULL ADDER:
TRUTH TABLE:

Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum (S) 0 1 1 0 1 0 0 1

Outputs Carry (Cout) 0 0 0 1 0 1 1 1

PROCEDURE: (i) (ii) (iii) Connections are given as per logic diagram. Logical inputs are given as per truth table. Observe the output and verify the truth table.

RESULT :

.. Signature of the staff in charge

13

HALF SUBTRACTOR:
TRUTH TABLE:

Input A 0 0 1 1
K- MAP SIMPLIFICATION:

B 0 1 0 1

Output Difference (D) Borrow (Bout) 0 0 1 1 1 0 0 0

LOGIC DIAGRAM:

Exp No: 03

Date:

DESIGN AND IMPLEMENTATION OF SUBTRACTOR CIRCUITS USING LOGIC GATES AIM: `To design and construct half substractor and full substractor. APPARATUS: Sl.No. 1. 2. 3. 4. 5. 6. 7. COMPONENT IC IC IC IC IC IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7432 IC 7486 IC 7408 IC 7400 IC 7404 QTY. 1 1 1 1 1 1 -

THEORY:
HALF SUBTRACTOR: The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter. FULL SUBTRACTOR: The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full subtractor .The first half subtractor will be C and A B. The output will be difference output of full subtractor. The expression AB assembles the borrow output of the half subtractor and the second term is the inverted difference output of first X- OR.

15

FULL SUBTRACTOR:
K- MAP SIMPLIFICATION:

LOGIC DIAGRAM:

Full Subtractor with Two Half Subtractors:

TRUTH TABLE:

Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Bin 0 1 0 1 0 1 0 1

Outputs Difference(D) Borrow(Bout) 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 1

PROCEDURE: (i) (ii) (iii) Connections are given as per logic diagram. Logical inputs are given as per truth table. Observe the output and verify the truth table.

RESULT :

.. Signature of the staff in charge

17

BCD TO EXCESS-3 CONVERTOR LOGIC DIAGRAM:

K-Map for E3:

E3 = B3 + B2 (B0 + B1)

Exp No:04

Date:

DESIGN AND IMPLEMENTATION OF BCD TO EXCESS-3 CODE CONVERTER USING LOGIC GATES AIM: To convert given BCD to excess-3 codes. APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4 5. 6. THEORY: An availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The input variable are designed as B3,B2,B1,B0 and the output variables are designed as E3,E2,E1,E0. From the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable. COMPONENT IC IC IC IC IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7432 IC 7486 IC 7408 IC 7404 QTY. 1 1 1 1 1 40

19

K-Map for E2:

K-Map for E1:

To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit.

21

K-Map for E0:

TRUTH TABLE: | BCD input B3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

| E3 0 0 0 0 0 1 1 1 1 1 x x x x x

Excess 3 output E2 0 1 1 1 1 0 0 0 0 1 x x x x x E1 1 0 0 1 1 0 0 1 1 0 x x x x x E0 1 0 1 0 1 0 1 0 1 0 x x x x x

PROCEDURE: (i) (ii) (iii) Connections are given as per logic diagram. Logical inputs are given as per truth table. Observe the output and verify the truth table.

RESULT: .. Signature of the staff in charge

23

BINARY TO GRAY CODE CONVERTOR LOGIC DIAGRAM:

K-Map for G3:

Exp No:05

Date:

DESIGN AND IMPLEMENTATION OF BINARY TO GRAY CODE CONVERTER USING LOGIC GATES AIM: To convert given binary numbers to gray codes. APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4 5. 6. COMPONENT IC IC IC IC IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7432 IC 7486 IC 7408 IC 7404 QTY. 1 1 1 1 1 40

THEORY: An availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The input variable are designed as B3,B2,B1,B0 and the output variables are designed as G3,G2,G1,G0. From the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable.

25

K-Map for G2:

K-Map for G1:

K-Map for G0:

27

TRUTH TABLE: | Binary input B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1

| G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1

Gray code output G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

PROCEDURE: (i) (ii) (iii) Connections are given as per logic diagram. Logical inputs are given as per truth table. Observe the output and verify the truth table.

RESULT: .. Signature of the staff in charge

29

PIN DIAGRAM FOR IC 7483:

K MAP

Y = S4 (S3 + S2)

Experiment No: 06

Date:

AIM:

DESIGN AND IMPLEMENTATION OF 4-BIT BCD ADDER USING IC 7483 To design and implement 4-bit adder using IC 7483.

APPARATUS REQUIRED: Sl.No. 1. 2. 3. 3. 4. IC EX-OR GATE NOT GATE IC TRAINER KIT PATCH CORDS COMPONENT SPECIFICATION IC 7483 IC 7486 IC 7404 QTY. 2 1 1 1 40

THEORY: Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum. The two BCD inputs to be added are applied at inputs
A and B of the first binary adder IC 7483. The sum output of the first binary adder is

given to the B input of the second binary adder. The A input of the binary adder is given (0110) BCD when a carry is generated from the first adder or when sum from the first binary adder is greater than (0110) BCD, else A input is (0000) BCD. The following Boolean expression is used to find whether (0110) BCD or (0000) BCD needs to be applied to the A input, Cout = Cout1 + S4 (S3 + S2) Where S4, S3, S2, S1 are the sum of the BCD from the first binary adder with S4 as the MSB and S1 as the LSB. Cout1 is the carry output from the first binary adder.

31

LOGIC DIAGRAM OF 4-BIT BCD ADDER:

TRUTH TABLE for BCD adder:

PROCEDURE:

(i) (ii) (iii)

Connections are given as per logic diagram. Logical inputs are given as per truth table. Observe the output and verify the truth table.

RESULT:

.. Signature of the staff in charge

2-BIT MAGNITUDE COMPARATOR: 33

LOGIC DIAGRAM:

Experiment No: 07

Date:

DESIGN AND IMPLEMENTATION OF 2-BIT MAGNITUDE COMPARATOR AIM: To design and implement 2-bit magnitude comparator using basic gates APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. 6. COMPONENT AND GATE X-OR GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7408 IC 7486 IC 7432 IC 7404 QTY. 2 1 1 1 1 30

THEORY: The comparison of two numbers is an operator that determine one number is greater than, less than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determine their relative magnitude. The outcome of the comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B. A = A3 A2 A1 A0 B = B3 B2 B1 B0 The equality of the two numbers and B is displayed in a combinational circuit designated by the symbol (A=B). This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits starting from most significant position. A is 0 and that of B is 0.

35

PROCEDURE: (i) (ii) (iii) Connections are given as per logic diagram. Logical inputs are given as per truth table. Observe the output and verify the truth table.

RESULT:

.. Signature of the staff in charge

29

4:1 MULTIPLEXER: BLOCK DIAGRAM

PIN DIAGRAM:

LOGIC DIAGRAM FOR MULTIPLEXER:

Experiment No:08

Date:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER AIM: To design and implement Multiplexer and Demultiplexer circuits APPARATUS REQUIRED: Sl.No. 1. 2. 3. 2. 3. THEORY: MULTIPLEXER: Multiplexer transmits a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine which input is selected. DEMULTIPLEXER: The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line. COMPONENT 3 I/P AND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7411 IC 7432 IC 7404 QTY. 2 1 1 1 32

31

FUNCTION TABLE: S1 0 0 1 1 S0 0 1 0 1 INPUTS Y D0 D0 S1 S0 D1 D1 S1 S0 D2 D2 S1 S0 D3 D3 S1 S0

Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0 TRUTH TABLE:

S1

S0

Y = OUTPUT

D0

D1

D2

D3

1:4 DEMULTIPLEXERS: BLOCK DIAGRAM

LOGIC DIAGRAM FOR DEMULTIPLEXER:

33

FUNCTION TABLE: S1 0 0 1 1 S0 0 1 0 1 INPUT X D0 = X S1 S0 X D1 = X S1 S0 X D2 = X S1 S0 X D3 = X S1 S0

Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0

TRUTH TABLE: INPUT S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 I/P 0 1 0 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 D1 0 0 0 1 0 0 0 0 OUTPUT D2 0 0 0 0 0 1 0 0 D3 0 0 0 0 0 0 0 1

PROCEDURE: (i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per the truth table. Observe the output and verify the truth table.

Result: -

.. Signature of the staff in charge

35

LOGIC DIAGRAM FOR 4x2 ENCODER:

TRUTH TABLE:
Input D0 1 0 0 0 D1 0 1 0 0 D2 0 0 1 0 D3 0 0 0 1 B 0 0 1 1 Output A 0 1 0 1

Experiment No: 09

Date:

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER AIM: To design and implement encoder and decoder using logic gates.

APPARATUS REQUIRED: Sl.No. 1. 2. 3. 2. 3. COMPONENT AND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7408 IC 7432 IC 7404 QTY. 1 2 1 1 1 -

THEORY: ENCODER: An encoder is a digital circuit that perform inverse operation of a decoder. An encoder has 2n input lines and n output lines. In encoder the output lines generates the binary code corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output that generate the corresponding binary code. In encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is meaningless. It has an undefined output when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 = 1. DECODER: A decoder is a multiple input multiple output logic circuit which converts coded input into coded output where input and output codes are different. The input code generally has fewer bits than the output code. Each input code word produces a different output code word i.e there is one to one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded information is present as n input producing 2n possible outputs. 2n output values are from 0 through out 2n 1.

37

LOGIC DIAGRAM FOR 2X4 DECODER:

TRUTH TABLE:
Input A 0 0 1 1 B 0 1 0 1 D0 1 0 0 0 Output D1 0 1 0 0 D2 0 0 1 0 D3 0 0 0 1

PROCEDURE: (i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per the truth table. Observe the output and verify the truth table.

Result: -

.. Signature of the staff in charge

39

LOGIC DIAGRAM OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER:

CHARACTERISTICS TABLE: Q 0 0 1 1 Qt+1 0 1 0 1 J 0 1 X X K X X 1 0

Experiment No: 10

Date:

DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER AIM: To design and implement 3 bit synchronous up/down counter. APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. 6. 7. COMPONENT JK FLIP FLOP 3 I/P AND GATE OR GATE XOR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7476 IC 7411 IC 7432 IC 7486 IC 7404 QTY. 2 1 1 1 1 1 35

THEORY: A Counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of progressing in increasing order or decreasing order through a certain sequence. An up/down counter is also called bi-directional counter. Usually up/down operation of the counter is controlled by up/down signal. When this signal high counter goes through up sequence and when up/down signal is low counter follows reverse sequence. The counter counts upwards when UP control are logic 1 and DOWN control is logic 0. In this case the clock input of each flip -flop other than the LSB flip-flop is fed from the normal output of the immediately preceding flip-flop. The counter counts downwards when the UP controls input are logic 0 and DOWN control is logic 1. In this case, the clock input of each flip-flop other than the LSB flip-flop is fed from the complemented output of the immediately preceding flip-flop.

41

TRUTH TABLE: Input Present State QA QB Q C Up/Down 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Next State QA+1 Q B+1 QC+1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

A JA 1 X X X X 0 0 0 0 0 0 1 X X X X KA X 0 0 0 1 X X X X X X X 0 0 0 1 JB 1 X X 0 1 X X 0 0 1 X X 0 1 X X

B KB X 0 1 X X 0 1 X X X 0 1 X X 0 1 JC 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X

C KC X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1

K-MAPS

STATE DIAGRAM:

43

PROCEDURE: (i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per the truth table. Observe the output and verify the truth table.

Result: -

.. Signature of the staff in charge

Experiment No:11

Date:

DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS AIM: To design and implement (i) Serial in serial out (ii) Serial in parallel out (iii) Parallel in serial out (iv) Parallel in parallel out APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. COMPONENT D FLIP FLOP OR GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7474 IC 7432 QTY. 2 1 1 35

THEORY: A register is capable of shifting its binary information in one or both directions is known as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right.

45

PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE: CLK 1 2 3 4 5 6 7 Serial in 1 0 0 1 X X X Serial out 0 0 0 1 0 0 1

LOGIC DIAGRAM: SERIAL IN PARALLEL OUT:

TRUTH TABLE: OUTPUT CLK 1 2 3 4 DATA 1 0 0 1 QA 1 0 0 1 QB 0 1 0 0 QC 0 0 1 0 QD 0 0 1 1

47

LOGIC DIAGRAM: PARALLEL IN SERIAL OUT:

TRUTH TABLE: CLK 0 1 2 3 Q3 1 0 0 0 Q2 0 0 0 0 Q1 0 0 0 0 Q0 1 0 0 0 O/P 1 0 0 1

LOGIC DIAGRAM: PARALLEL IN PARALLEL OUT:

TRUTH TABLE: DATA INPUT CLK 1 2 DA 1 1 DB 0 0 DC 0 1 DD 1 0 QA 1 1 OUTPUT QB 0 0 QC 0 1 QD 1 0

PROCEDURE: (i). Connections are given as per logic diagram. (ii). Logical inputs are given as per truth table. (iii) Observe the output and verify the truth table.

Result: -

.. Signature of the staff in charge

49

VIVA QUESTIONS 1) Define binary logic? Binary logic consists of binary variables and logical operations. The variables are Designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT. 2) State the different classification of binary codes? 1. Weighted codes 2. Non - weighted codes 3. Reflective codes 4. Sequential codes 5. Alphanumeric codes 6. Error Detecting and correcting codes. 3) Define byte? Group of 8 bits. 4) List the different number systems? 1. Decimal Number system 2. Binary Number system 3. Octal Number system 4. Hexadecimal Number system 5) What are basic properties of Boolean algebra? The basic properties of Boolean algebra are commutative property, associative Property and distributive property. 6) State the associative property of Boolean algebra. The associative property of Boolean algebra states that the OR ing of several variables results in the same regardless of the grouping of the variables. The associative property is stated as follows: A+ (B+C) = (A+B) +C 7) State the commutative property of Boolean algebra. The commutative property states that the order in which the variables are OR ed makes no difference. The commutative property is: A+B=B+A 8) State the distributive property of Boolean algebra. The distributive property states that AND ing several variables and OR ing the result With a single variable is equivalent to OR ing the single variable with each of the the several Variables and then AND ing the sums. The distributive property is: A+BC= (A+B) (A+C) 9) State the absorption law of Boolean algebra. The absorption law of Boolean algebra is given by X+XY=X, X(X+Y) =X. 10) State De Morgan's theorem. De Morgan suggested two theorems that form important part of Boolean algebra.

They are, 1) The complement of a product is equal to the sum of the complements. (AB)' = A' + B' 2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B' 11) Define duality property. Duality property states that every algebraic expression deducible from the postulates Of Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's. 12) What are the methods adopted to reduce Boolean function? 1. Karnaug map 2. Tabular method or Quine Mc-Cluskey method 3. Variable entered map technique. 13) State the limitations of karnaugh map. 1. Generally it is limited to six variable map (i.e) more then six variable involving expression are not reduced. 2. The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form. 14) What is a karnaugh map? A karnaugh map or k map is a pictorial form of truth table, in which the map diagram is made up of squares, with each squares representing one minterm of the function. 44) Find the minterms of the logical expression Y = A'B'C' + A'B'C + A'BC + ABC' Y = A'B'C' + A'B'C + A'BC + ABC' =m0 + m1 +m3 +m6 =_m(0, 1, 3, 6) 15) What are called dont care conditions? In some logic circuits certain input conditions never occur, therefore the corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by X ord in the truth tables and are called dont care conditions or incompletely specified functions. 16) What is a Logic gate? Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. 17) What are the basic digital logic gates? The three basic logic gates are 1. AND gate 2. OR gate 3. NOT gate 51

18) Which gates are called as the universal gates? What are its advantages? The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application. 19) Classify the logic family by operation? The Bipolar logic family is classified into Saturated logic unsaturated logic. The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family. The Schottky TTL, and ECL logic comes under the unsaturated logic family. 20) Mention the different IC packages? 1. DIP- Dual in line package 2. LCC- Leadless Chip Carrier 3. PLCC- Plastic Leaded Chip carrier 4. PQFP- Plastic Quad Flat Pack 5. PGA- Pin Grid Array 21) Mention the important characteristics of digital ICs? Fan out, Power dissipation, Propagation Delay, Noise Margin, Fan In, Operating temperature, Power supply requirements 22) Define combinational logic When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic. 23) Define Half adder and full adder. The logic circuit that performs the addition of two bits is a half adder. The circuit that performs the addition of three bits is a full adder. 24) Define Decoder? A decoder is a multiple - input multiple output logic circuit that converts coded inputs into coded outputs where the input and output codes are different. 25) What is binary decoder? A decoder is a combinational circuit that converts binary information from n-input lines to a maximum of 2n out puts lines. 26) Define Encoder? An encoder has 2n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input value. 27) What is priority Encoder? A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. 28) Define multiplexer? Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line. 29) What do you mean by comparator?

A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers. 30) What are the classification of sequential circuits? The sequential circuits are classified on the basis of timing of their signals into two types. They are, 1. Synchronous sequential circuit. 2. Asynchronous sequential circuit. 31) Define Flip flop. The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state. 32) What are the different types of flip-flop? There are various types of flip flops. Some of them are mentioned below they are, 1. RS flip-flop 2. SR flip-flop 3. D flip-flop 4. JK flip-flop 5. T flip-flop 33) Define registers. A register is a group of flip-flops flip-flop can store one bit information. So an n- bit register has a group of n flip-flops and is capable of storing any binary information/number containing n-bits. 34) Define shift registers. The binary information in a register can be moved from stage to stage within the register or into or out of the register upon application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers. 35) What are the different types of shift type? There are five types. They are, 1. Serial In Serial Out Shift Register 2. Serial In Parallel Out Shift Register 3. Parallel In Serial Out Shift Register 4. Parallel In Parallel Out Shift Register 5. Bidirectional Shift Register 37) Give the comparison between combinational circuits and sequential circuits. Combinational circuits Sequential circuits Memory unit is not required Memory unity is required Parallel adder is a combinational circuit Serial adder is a sequential circuit 38) What do you mean by present state? The information stored in the memory elements at any given time defines the present state of the sequential circuit. 53

39) What do you mean by next state? The present state and the external inputs determine the outputs and the next state of the sequential circuit. 40) Give the comparison between synchronous & Asynchronous sequential circuits? Synchronous sequential circuits Asynchronous sequential circuits. Memory elements are clocked flip-flops Memory elements are either unlocked flip-flops or time delay elements. Easier to design More difficult to design