PHYSICSPROJECT

Submitted For Exam

TOPIC OF THE PROJECT

ELECTRONICADDER

Department Of Physics
Indira Gandhi Memorial High School
456, P.K.GUHA ROAD, DUMDUM
KOLKATA 700028

PROJECT PREPARED BY
BOARD'S ROLL NO. :

ACKNOWLEDGEMENT
At the outset, I express my gratitude to
of the department of physics under whose overall guidance
this project was undertaken and successfully accomplished.

DATE : ........................

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(Signature of Student)

CERTIFICATION

This is to certify that , Roll no. of class XII has completed

DATE : ........................

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ADDER
In electronics, an adder or summer is a digital circuit that performs
addition of numbers. In many computers and other kinds of
processors, adders are used not only in the arithmetic logic units, but
also in other parts of the processor, where they are used to calculate
addresses, table indices, increment and decrement operators, and
similar operations.
Although adders can be constructed for many numerical
representations, such as binary-coded decimal or excess-3, the most
common adders operate on binary numbers. In cases where two's
complement or ones' complement is being used to represent
negative numbers, it is trivial to modify an adder into an adder
subtractor. Other signed number representations require more logic
around the basic adder.

AND GATE
The AND gate is a basic digital logic gate that implements logical
conjunction - it behaves according to the truth table below. A HIGH output
(1) results only if both the inputs to the AND gate are HIGH (1). If neither or
only one input to the AND gate is HIGH, a LOW output results. In another
sense, the function of AND efectively fnds the minimum between two
binary digits, just as the OR function fnds the maximum. Therefore, the
output is always 0 except when all the inputs are 1.

SYMBOLS
There are three symbols for AND gates: the American (ANSI or 'military')
symbol and the IEC ('European' or 'rectangular') symbol, as well as the
deprecated DIN symbol.

MIL/ANSI Symbol

IEC Symbol

DIN Symbol

The AND gate with inputs A and B and output C implements the logical
expression C = A.B

ALTERNATIVES
If no specifc AND gates are available, one can be made from NAND or NOR
gates, because NAND and NOR gates are considered the "universal gates,"
meaning that they can be used to make all the others.

Desired gate

NAND construction

NOR construction

OR GATE
The OR gate is a digital logic gate that implements logical disjunction - it
behaves according to the truth table below. A HIGH output (1) results if
one or both the inputs to the gate are HIGH (1). If neither input is high, a
LOW output (0) results. In another sense, the function of OR efectively
fnds the maximum between two binary digits, just as the complementary
AND function fnds the minimum.
INPUT
A
0
0
1
1

B
0
1
0
1

OUTPUT
A OR B
0
1
1
1

SYMBOLS
There are two symbols of OR gates: the American (ANSI or 'military')
symbol and the IEC ('European' or 'rectangular') symbol, as well as the
deprecated DIN symbol.

MIL/ANSI Symbol

IEC Symbol

DIN Symbol

ALTERNATIVES
If no specifc OR gates are available, one can be made from NAND or NOR
gates in the confguration shown in the image below. Any logic gate can be
made from a combination of NAND or NOR gates.
NAND Construction

NOR construction

XOR GATE
The XOR gate (sometimes EOR gate, or EXOR gate and pronounced as
Exclusive OR gate) is a digital logic gate that implements an exclusive or;
that is, a true output (1/HIGH) results if one, and only one, of the inputs to
the gate is true. If both inputs are false (0/LOW) or both are true, a false
output results. XOR represents the inequality function, i.e., the output is
true if the inputs are not alike otherwise the output is false. A way to
remember XOR is "one or the other but not both".
XOR can also be viewed as addition modulo 2. As a result, XOR gates are
used to implement binary addition in computers. A Half adder consists of
an XOR gate and an AND gate. Other uses include subtractors,
comparators, and controlled inverters.

The algebraic expressions A.B' + B.A' and (A+B).(A'+B') both represent

SYMBOLS
There are two symbols for XOR gates: the traditional symbol and the IEEE
symbol.

Traditional XOR Symbol

IEEE XOR Symbol

ALTERNATIVES
If a specifc type of gate is not available, a circuit that implements the
same function can be constructed from other available gates. A circuit
implementing an XOR function can be trivially constructed from an XNOR
gate followed by a NOT gate. If we consider the expression A.B'+A'.B , we
can construct an XOR gate circuit directly using AND, OR and NOT gates.
An XOR gate circuit can also be made from four NAND or fve NOR gates in
the confguration shown below.

XOR gate circuit constructed using only

XOR gate circuit constructed using only

XOR gate circuit using three

NOR gates.

HALF ADDER
The half adder adds two single binary digits A and B. It has two outputs,
sum (S) and carry (C). The carry signal represents an overfow into the
next digit of a multi-digit addition. The value of the sum is 2C + S. The
simplest half-adder design, pictured on the right, incorporates an XOR
gate for S and an AND gate for C. With the addition of an OR gate to
combine their carry outputs, two half adders can be combined to make a
full adder.

Half adder logic diagram

The half adder adds two input bits and generates a carry and sum, which
are the two outputs of a half adder. The input variables of a half adder are
called the augend and addend bits. The output variables are the sum and
carry. The truth table for the half adder is:

FULL ADDER
A full adder adds binary numbers and accounts for values carried in as well
as out. A one-bit full adder adds three one-bit numbers, often written as A,

B, and Cin; A and B are the operands, and Cin is a bit carried in from the
previous less signifcant stage. The full adder is usually a component in a
cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The
circuit produces a two-bit output, output carry and sum typically
represented by the signals Cout and S, where sum = 2Cout + S.

Schematic symbol for a 1-bit full adder

Logic diagram for a full adder.

with Cin and Cout drawn on sides of block to

In this implementation, the fnal OR gate before the carry-out output may
be replaced by an XOR gate without altering the resulting logic. Using only
two types of gates is convenient if the circuit is being implemented using
simple IC chips which contain only one gate type per chip.

A full adder can be constructed from two half adders by connecting A and
B to the input of one half adder, connecting the sum from that to an input
to the second adder, connecting Ci to the other input and OR the two carry
outputs. The critical path of a full adder runs through both XOR-gates and
ends at the sum bit s. Assumed that an XOR-gate takes 3 delays to
complete, the delay imposed by the critical path of a full adder is equal to
TFA = 2.TXOR = 2 . 3D =6D
The carry-block subcomponent consists of 2 gates and therefore has a
delay of
Tc=2D

RIPPLE-CARRY ADDER

It is possible to create a logical circuit using multiple full adders to add Nbit numbers. Each full adder inputs a Cin, which is the Cout of the previous
adder. This kind of adder is called a ripple-carry adder, since each carry bit
"ripples" to the next full adder. Note that the frst full adder may be
replaced by a half adder (under the assumption that Cin =0).
The layout of a ripple-carry adder is simple, which allows for fast design
time; however, the ripple-carry adder is relatively slow, since each full
adder must wait for the carry bit to be calculated from the previous full
adder. The gate delay can easily be calculated by inspection of the full
adder circuit. Each full adder requires three levels of logic. In a 32-bit
ripple-carry adder, there are 32 full adders, so the critical path (worst
case) delay is 3 (from input to carry in frst adder) + 31 * 2 (for carry
propagation in later adders) = 65 gate delays. The general equation for
the worst-case delay for a n-bit carry-ripple adder is

BIBLIOGRAPHY
WEBSITES
www.google.com
www.wikipedia.com

BOOKS
NCERT Physics Book (Class-XII).
Morris Mano Architecture.