DIGITALSYSTEMDESIGNUSINGVERILOG(21EC32)

MODULE-2 LOGICDESIGNWITHMSICOMPONENTSAND
PROGRAMMABLELOGICDEVICES

Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers,

Programmable Logic Devices (PLD’s).

DESIGNOFCOMBINATIONAL CIRCUITS
Thedesignofcombinationalcircuitsstartsfromtheverbaloutlineoftheproblemandendsina logic
circuit diagram. The procedure involves the following steps:
1. Statethe given problemcompletely and exactly
2. Interprettheproblem,anddeterminetheavailableinputvariablesandrequiredoutput variables.
3. Assignaletter symboltoeach inputandoutputvariables.
4. Designthetruth table, whichdefines the requiredrelations betweeninputsand outputs.
5. ObtainthesimplifiedBooleanexpressionforeachoutputusingk-maps.
6. Drawthelogic circuitdiagramtoimplementtheBooleanexpression.

ARITHMETICCIRCUITS
One essential function of most computers and calculators is the performance of arithmetic
operations.Thelogicgatesdesignedsofarcanbeusedtoperformarithmeticoperationssuchas
addition, subtraction, multiplication and division in electronic calculators and digital
instruments.Since these circuits are electronic, they are very fast. Typically an addition
operation takes less than 1 µs.

HALF– ADDER

ALogiccircuitusedfortheadditionoftwoonebitnumbersisreferredtoasahalf-adder.From the verbal

explanation of a half adder, we find that this circuit needs two binary inputs and two binary
outputs. The input variables designate the augend and addend bits; the output variables produce
the sum and carry. We assign the symbols A and B to the two inputs and S (for sum) and C (for
carry) to the outputs. The truth table for the half-adder is shown below.

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HeretheC output is1 only when both inputs are1. TheS output represents theleast significant bit
of the sum. The logic expression for the sum output can be obtained from the truth table. It
canbewrittenasaSOPexpressionbysumminguptheinputcombinationsforwhichthesumis equal to
1.

Inthetruthtable,thesumoutput is1forA′BandAB′. Therefore,theexpressionforthesum is

S= A′B+ AB′=A⊕B.

Similarly,thelogicexpressionforcarryoutputcan bewrittenas aSOPexpressionbysumming up the

input combinations for which the carry is equal to 1.In the truth table, the carry is 1 for
AB.ThereforeC=ABThisexpressionforCcannotbesimplified.Thesumoutputcorresponds to
alogicEx-OR function whilethecarry output corresponds to an AND function.So thehalf- adder
circuit can be implemented using Ex-OR and AND gate as shown below.

Fig1:HalfAdderLogiccircuit

ThiscircuitiscalledHalf-Adder,becauseitcannotacceptaCARRY-INfrompreviousadditions.
Thisisthereasonthathalf–addercircuitcanbeusedforbinaryadditionoflowermostbitsonly. For
higher order columns we use a 3-input adder called full-adder

FULL–ADDER

A combinational logic circuit for adding three bits. As seen, a half-adder has only two inputs
andthereisnoprovisiontoaddcarrycomingfromthelowerbitorderwhenmultibitadditionis
performed.Forthispurposeweusealogiccircuitthatcanaddthreebits,thethirdbitisthecarry

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from the lower column. This implies that we need a logic circuit with 3 inputs and 2 outputs.
Such a circuit is called a full – adder. The truth table for the full-adder is as shown below.

As shown there are 8 possible input combinations for the three inputs and for each case the S
and Cout values are listed. From the truth table, the logic expression for S can be written by
summing up the input combinations for which the sum output is 1 as:

S =A′B′Cin + A′BC′in+AB′C′in + ABCin

=A′(B′Cin +BC′in) +A(B′C′in +BCin)
= A′(B⊕Cin)+ A(B⊕Cin)′ LetB⊕Cin=X
Now, S =A′X+AX′ = A ⊕ X Replacing X in theabove expression we get
S = A⊕B⊕Cin
SimilarlythelogicexpressionforCoutcanbewrittenas Cout=
A′BCin + AB′Cin + ABC′in + ABCin

Cout=BCin+ACin+ AB (using the map shown)

FromthesimplifiedexpressionsofSandCthefulladderCircuitcanbeimplementedusingtwo 2-input
XOR gates, Three 2 –input AND gates and one 3-input OR gate a shown below fig (a). The
logic symbol is also shown as fig (b).

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Fig2:FullAdderLogicCircuit
The logic symbol has two inputs A and B plus a third input Cin called the Carry-in and two
outputsSUMandtheCarrycalledCarryout,Coutgoingtothenexthighercolumn..Afulladder can be
made by using two half adders and an OR gate as shown below.

Fig3:Fulladder circuit usingtwohalfadders

HALF– SUBTRACTOR
A logic circuit that subtracts Y (subtrahend) from X(minuend), where X and Y are 1-bit
numbers, is known as a half-subtractor. It has two inputs X (minuend) and Y (subtrahend) and
two outputs D (difference) and B (borrow), as shown in the block diagram.

The operation of this logic circuit is based on the rules of binary subtraction given in the truth
table reproduced on the basis of the subtraction process.

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The difference output in the third column has the same logic pattern as when X is XORed with
Y(sameas in thecaseof sum). Hencean Ex-Orgatecan beused to givedifferenceoftwo bits. The
borrow output in the 4th column can be obtained by using a NOT gate and AND gate, as shown
in the circuit diagram below.
Thelogicalequations for thedifferenceDandborrowBare given as
D=X′Y+XY′=X⊕ Y. B =
X′Y

Fig4:HalfSubtractorLogiccircuit

FULL–SUBTRACTOR
Thefull-subtractorisacombinationalcircuitwhichisusedtoperformsubtractionofthreesingle bits.

X Y Z

FULL
SUBTRACTOR

B
D
Thetruth tablefor thefull-subtractor isas shown below.

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INPUT OUTPUT

X Y Z D B

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

As shown there are 8 possible input combinations for the three inputs and for each case the D
and B values are listed. From the truth table, the logic expression for D can be written by
summing up the input combinations for which the Difference output is 1 as:

D=X’Y'Z+X’YZ’ +XY’Z'+XYZ
=X’(Y’Z+YZ’) +X(Y’Z'+YZ)

=X’(Y⊕Z)+X(Y⊕Z)’

D=X ⊕Y ⊕ Z

B=X’Y'Z+X’YZ’ +X’YZ+XYZ

=Z (X’Y+XY’)+X’Y(Z’+Z)

B=Z (X⊕Y)+ X’Y

Thecircuitdiagramforfullsubtractorisconstructed fromhalfsubtractor and theextensiontoit

,as shown below.

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Fig5:FullSubtractorLogic circuit

4-BITPARALLELADDER

The 4-bit binary adder performs the addition of two 4-bit numbers. Let the 4-bit binary
numbers,A=A3 A2 A1 A0 andB=B3 B2 B1 B0. We can implement 4-bit binary adder in one of
the two following ways.

 Use one Half adder for doing the addition of two Least significant bits and three
Fulladders for doing the addition of three higher significant bits. 

 Use four Full adders for uniformity. Since, initialcarry C0is zero, the Fulladder which is
used for adding the least significant bits becomes Half adder.

For the time being, we considered second approach. The block diagramof 4-bit binary adder
is shown in the following figure.

Fig6:4-BitBinaryAdderCircuit

Here,the4Fulladdersarecascaded.EachFulladderisgettingtherespectivebitsoftwoparallel inputs
A & B. The carry output of one Full adder will be the carry input of subsequent higher order
Full adder. This 4-bit binary adder produces the resultant sum having at most 5 bits. So, carry
out of last stage Full adder will be the MSB.

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In this way, we can implement any higher order binary adder just by cascading the required
numberofFulladders.Thisbinaryadderisalsocalledasripplecarry(binary)adderbecause the
carry propagates (ripples) from one stage to the next stage.

BINARYSUBTRACTOR
The circuit, which performs the subtraction of two binary numbers is known as Binary
subtractor. We can implement Binary subtractor in following two methods.

 CascadeFull subtractors

 2’scomplement method

Infirstmethod,wewillgetann-bitbinarysubtractorbycascading‘n’Fullsubtractors.So,first
youcanimplementHalfsubtractorandFullsubtractor,similartoHalfadder&Fulladder.Then,
youcanimplementann-bitbinarysubtractor,bycascading‘n’Fullsubtractors.So,wewillbe having
two separate circuits for binary addition and subtraction of two binary numbers.

In second method, we can use same binary adder for subtracting two binary numbers just by
doing some modifications in the second input. So, internally binary addition operation takes
place but, the output is resultant subtraction.

WeknowthatthesubtractionoftwobinarynumbersA&Bcanbewrittenas, A−B =

A+(2′s complement of B)
A−B=A+(2′scomplementofB)

⇒A−B=A+(1′s complement ofB)+1

4-bitBinary Subtractor

The4-bitbinarysubtractorproducesthesubtractionoftwo4-bitnumbers.Letthe4bitbinary
numbers,A = A3 A2 A1 A0andB = B3 B2 B1 B0 . Internally, the operation of 4-bit Binary
subtractor is similar to that of 4-bit Binary adder. If the normal bits of binary number A,
complemented bits of binary number B and initial carry (borrow), C inas one are applied to 4-
bit Binary adder, then it becomes 4-bit Binary subtractor. Theblock diagram of 4-bit binary
subtractor is shown in the following figure.

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Fig7:4-BitBinarySubtractorCircuit

This4-bitbinarysubtractorproducesanoutput,whichishavingatmost5bits.IfBinarynumber
Aisgreaterthan Binary numberB,thenMSB oftheoutputiszeroandthe remainingbitshold the
magnitude of A-B. If Binary number A is less than Binary number B, then MSB of the output
is one. So, take the 2’s complement of output in order to get the magnitude of A-B.

Inthisway,wecanimplementanyhigherorderbinarysubtractorjustbycascadingtherequired
number of Full adders with necessary modifications.

4-bitBinaryAdder/ Subtractor

The 4-bit binary adder / subtractor produces either the addition or the subtraction of two 4-bit
numbersbasedonthevalueofinitialcarryorborrow,C0.Letthe4-bitbinarynumbers,A=A3 A2 A1
A0andB =B3 B2 B1 B0. Theoperation of4-bit Binary adder/ subtractoris similarto that of 4-bit
Binary adder and 4-bit Binary subtractor.
Apply the normal bits of binary numbers A and B & initial carry or borrow, C 0 from
externallytoa4-bitbinaryadder.Theblockdiagramof4-bitbinaryadder/subtractoris shown in the
following figure.

Fig8:4-BitBinaryAdder/SubtractorCircuit

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If initial carry, C0is zero, then each full adder gets the normal bits of binary numbers A & B.
So,the4-bitbinaryadder/subtractorproducesanoutput,whichistheadditionoftwobinary
numbers A & B.

If initial borrow, 𝐶0 is one, then each full adder gets the normal bits of binary number A
&complemented bits of binary number B. So, the 4-bit binary adder / subtractor produces an
output, which is the subtraction of two binary numbers A & B.

Therefore, with the help of additional Ex-OR gates, the same circuit can be used for both
addition and subtraction of two binary numbers.

Fig9:4-BitCarryLookAheadAdderBlockDiagram

Pi=Ai⊕ BiCarrypropagate Gi

= AiBB i Carry generate For

i=0

c1=g0+p0c0For

i=1

c2=g1+p1c1

=g1+p1(g0+p0c0)

=g1+p1g0+p1p0c0For

i=2

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c3=g2+p2c2

=g2+p2g1+p2p1g0+p2p1p0c0For

i=3

c4=g3+p3c3=g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0

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Fig10:4-BitCarryLookAheadAdderLogiccircuit

ComplexProgrammableLogicDevices(CPLD’s)
• AsnumberofBooleanexpressionincreases,designingadigitalcircuitusingPLD’s becomes
difficult.

• Toovercomethisproblemwecanuse complexprogrammablelogicdevices.

• UsingCPLDs wecan implementmorethan20 Booleanexpression ina digital circuit.

Fig 11: Block Diagramof CPLD

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FeaturesofCPLD
• High Performance
• FastconnectionofSwitch matrix

• Programmableswitching mode

Applicationsof CPLD
• Itis used inadigital circuit whereNumber ofinput andoutput are>32.

• TelevisionandAutomationIndustries.

• Implementationoflargedigitalcircuits.

FieldProgrammableGateArrays(FPGA)
• AField-ProgrammableGateArrayisanintegratedcircuitsiliconchipwhichhasarray of
logic gates and this array can be programmed in the field i.e. the user can overwrite the
existing configurations with its new defined configurations and can create their own
digital circuit on field. The FPGAs can be considered as blank slate. FPGAs do nothing
by itself whereas it is upto designers to create a configuration file often called a bit file
fortheFPGA. TheFPGAwill behavelikethedigitalcircuitonceitis loadedwith abit file.

• Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based
around a matrix of configurable logic blocks (CLBs) connected via programmable
interconnects.

• FPGAs are particularly useful for prototyping application-specific integrated circuits

(ASICs) or processors.

• AnFPGAcan bereprogrammeduntil theprocessor designis final and bug-free.

FPGAArchitecture

• AnFPGAhas aregularstructureoflogic cells or modules and interlinks which is under the

developers and designers complete control. The FPGA is built with mainly three major
blocks such as Configurable Logic Block (CLB), I/O Blocks or Pads and Switch
Matrix/ Interconnection Wires. Each block will be discussed below in brief.

• CLB (Configurable Logic Block): These are the basic cells of FPGA. It consists of one
8-bitfunctiongenerator,two16-bitfunctiongenerators,tworegisters(flip-flopsor

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latches), and reprogrammable routing controls (multiplexers). The CLBs are applied to
implement other designed function and macros. Each CLBs have inputs on each side
which makes them flexile for the mapping and partitioning of logic.

• I/OPadsorBlocks:TheInput/Outputpadsareusedfortheoutsideperipheralstoaccess the
functions of FPGA and using the I/O pads it can also communicate with FPGA for
different applications using different peripherals.

• Switch Matrix/ Interconnection Wires: Switch Matrix is used in FPGA to connect the
longandshortinterconnectionwirestogetherinflexiblecombination.Italsocontainsthe
transistors to turn on/off connections between different lines.

Fig 12: Block Diagramof FPGA

Configurablelogic blocks:
EachConfigurablelogic block cangenerateaLogicfunctionwithmany inputs.
InterconnectionSwitches:
Theyareusedtointerconnect variousblockwithinput/output blocks.
Application:
FPGAmostcommonlyused inDigitalsystems suchassmart phones,Computersystems etc.

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CPLDvsFPGAcomparisonsummary

CPLD FPGA
1. Instant-on.CPLDsstartworkingas soon Since FPGA has to load configuration data
as they are powered up from external ROM and setup the fabric
before it can start functioning, there is a time
delay between power ON and FPGA starts
working. The time delay can be as large as
several tens of milliseconds.

2. Non-volatile. CPLDs remain FPGAs uses SRAM based configuration

programmed, and retain their circuit storage.Thecontentsofthememoryislostas
afterpoweringdown.FPGAsgoblank as soon as power is disconnected.
soon as powered-off.

3. Deterministic Timing Analysis. Since Size and complexity of FPGA logic can be
CPLDs are comparatively simpler to humongous compared to CPLDs. This opens
FPGAs, and the number of up the possibility less deterministic signal
interconnects are less, the timing routing and thus causing complicated timing
analysis can be done much more scenarios. Thankfully implementation tools
easily. providedbyFPGAvendorshavemechanisms to
assist achieving deterministic timing. But
additional steps by the user is usually
necessary to achieve this.

4. Lower idle power consumption. Relativelyhigheridlepower consumption.

Newer CPLDs such as CoolRunner-II
use around 50 uA in idle conditions.

5. Mightbecheaperforimplementing FPGAs are much more capable compared to

simpler circuits CPLDs but can be more expensive as well.

6. More"secure"duetodesignstorage FPGAs that use external memory can expose

within built in non-volatile memory. the IP externally. Many FPGA vendors offer
mechanisms such as encryption to combat
this. Design specific protection mechanisms
also can be implemented.

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7. Verysmallamount oflogic resources. Massive amount logic and storage elements,

withwhichincrediblycomplexcircuitscanbe
designed. FPGAs have thousands times more
resources! This point alone makes FPGAs
more popular than CPLDs.

8. Noon-diehardIPsavailabletooffload Variety of on-die dedicated hardware such as

processing from the logic fabric. Block RAM, DSP blocks, PLL, DCMs,
Memory Controllers, Multi-Gigabit
Transceivers etc give immense flexibility.
This is not even thinkable with CPLDs.

9. Power down and reprogramming is FPGAs can change their circuit even while
always required in order to modify running! (Since it is just a matter of updating
design functionality. LUTs with different content) This is called
Partial Reconfiguration, and is very useful
when FPGAs need to keep running a design
and at the same time update the it with
different design as per requirement. This
feature is widely used in Accelerated
Computing.

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