PIC32MX5XX/6XX/7XX Family Data Sheet: High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

PIC32MX5XX/6XX/7XX
Family Data Sheet

High-Performance, USB, CAN and Ethernet
32-Bit Flash Microcontrollers
 2010 Microchip Technology Inc. Preliminary DS61156C

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-037-9
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS61156C-page 2 Preliminary  2010 Microchip Technology Inc.

PIC32MX5XX/6XX/7XX
High-Performance, USB, CAN and Ethernet
32-Bit Flash Microcontrollers
High-Performance 32-Bit RISC CPU: Peripheral Features (Continued):
• MIPS32® M4K™ 32-bit core with 5-stage pipeline • Internal 8 MHz and 32 kHz oscillators
• 80 MHz maximum frequency • Six UART modules with:
• 1.56 DMIPS/MHz (Dhrystone 2.1) performance - RS-232, RS-485 and LIN 1.2 support
at zero Wait state Flash access - IrDA® with on-chip hardware encoder and
• Single-cycle multiply and high-performance divide decoder
unit • Up to four SPI modules
• MIPS16e™ mode for up to 40% smaller code size • Up to five I2C™ modules
• Two sets of 32 core register files (32-bit) to reduce • Separate PLLs for CPU and USB clocks
interrupt latency • Parallel Master and Slave Port (PMP/PSP) with
• Prefetch Cache module to speed execution from 8-bit and 16-bit data, and up to 16 address lines
Flash • Hardware Real-Time Clock/Calendar (RTCC)
• Five 16-bit Timers/Counters (two 16-bit pairs
Microcontroller Features: combine to create two 32-bit timers)
• Operating voltage range of 2.3V to 3.6V • Five Capture inputs
• 256K to 512K Flash memory (plus an additional • Five Compare/PWM outputs
12 KB of Boot Flash) • Five external interrupt pins
• 64K to 128K SRAM memory • High-speed I/O pins capable of toggling at up to
• Pin-compatible with most PIC24/dsPIC® devices 80 MHz
• Multiple power management modes • High-current sink/source (18 mA/18 mA) on
• Multiple interrupt vectors with individually all I/O pins
programmable priority • Configurable open-drain output on digital I/O pins
• Fail-Safe Clock Monitor mode
• Configurable Watchdog Timer with on-chip Debug Features:
Low-Power RC oscillator for reliable operation • Two programming and debugging Interfaces:
- 2-wire interface with unintrusive access and
Peripheral Features: real-time data exchange with application
• Atomic Set, Clear and Invert operation on select - 4-wire MIPS® standard enhanced JTAG
peripheral registers interface
• 8-channel hardware DMA with automatic data • Unintrusive hardware-based instruction trace
size detection • IEEE Standard 1149.2 compatible (JTAG)
• USB 2.0-compliant full-speed device and boundary scan
On-The-Go (OTG) controller:
- Dedicated DMA channels Analog Features:
• 10/100 Mbps Ethernet MAC with MII and RMII • Up to 16-channel, 10-bit Analog-to-Digital
interface: Converter:
- Dedicated DMA channels - 1 Msps conversion rate
• CAN module: - Conversion available during Sleep and Idle
- 2.0B Active with DeviceNet™ addressing • Two Analog Comparators
support
• 5V tolerant input pins (digital pins only)
- Dedicated DMA channels
• 3 MHz to 25 MHz crystal oscillator
 2010 Microchip Technology Inc. Preliminary DS61156C-page 3

PIC32MX5XX/6XX/7XX
TABLE 1: PIC32MX FEATURES
Timers/Capture/Compare
Program Memory (KB)
10-Bit 1 Msps ADC

Data Memory (KB)
(Programmable/
DMA Channels
Comparators
Packages(4)
(Channels)
Dedicated)
PMP/PSP
UART(2,3)
Ethernet
I2C™(3)
Device
Trace
SPI(3)
JTAG
CAN
Pins
USB
PT,
PIC32MX575F256H 64 256 + 12(1) 64 1 0 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No
MR
PT,
MR
PT,
MR
PT,
MR
PT,
MR
PT,
MR
PT,
MR
PT,
MR
PT,
PIC32MX575F256L 100 256 + 12(1) 64 1 0 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PF,
BG
PT,
BG
PT,
BG
PT,
BG
PT,
BG
PT,
512 + 12(1)
PIC32MX695F512L 100 128 1 1 0 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PF,
BG
PT,
BG
PT,
BG
Legend: PF, PT = TQFP MR = QFN BG = XBGA
Note 1: This device features 12 KB boot Flash memory.
2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.
3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more
information.
4: Refer to Section 32.0 “Packaging Information” for detailed information.

PIC32MX5XX/6XX/7XX
Pin Diagrams
64-Pin QFN = Pins are up to 5V tolerant
SCK1A/U1BTX/U1ARTS/OC2/RD1
SCL1A/SDO1A/U1ATX/OC4/RD3
SDA1A/SDI1A/U1ARX/OC3/RD2
OC5/IC5/PMWR/CN13/RD4
PMRD/CN14/RD5
VCAP/VDDCORE
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
C1RX/RF0
CN16/RD7
CN15/RD6
C1TX/RF1
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5 1 48 SOSCO/T1CK/CN0/RC14
PMD6/RE6 2 47 SOSCI/CN1/RC13
PMD7/RE7 3 46 OC1/INT0/RD0
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 4 45 IC4/PMCS1/PMA14/INT4/RD11
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 5 44 SCL1/IC3/PMCS2/PMA15/INT3/RD10
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 6 43 SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
MCLR 7 42 RTCC/IC1/INT1/RD8
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 8 PIC32MX575F256H 41 Vss
VSS 9 40 OSC2/CLKO/RC15
PIC32MX575F512H
VDD 10 39 OSC1/CLKI/RC12
AN5/C1IN+/VBUSON/CN7/RB5 11 38 VDD
AN4/C1IN-/CN6/RB4 12 37 D+/RG2
AN3/C2IN+/CN5/RB3 13 36 D-/RG3
AN2/C2IN-/CN4/RB2 14 35 VUSB
PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15 34 VBUS
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16 33 USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AVDD
VDD
AVSS
VSS
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TDO/AN11/PMA12/RB11
TCK/AN12/PMA11/RB12
AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
TDI/AN13/PMA10/RB13
AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14
AN15/OCFB/PMALL/PMA0/CN12/RB15
AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
TMS/AN10/CVREFOUT/PMA13/RB10
Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.

PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
ERXCLK/EREFCLK/PMD3/RE3
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
ERXDV/ECRSDV/PMD2/RE2
AETXD0/ERXD2/RF1
AETXD1/ERXD3/RF0
ERXERR/PMD4/RE4
ERXD0/PMD1/RE1
ERXD1/PMD0/RE0
PMRD/CN14/RD5
VCAP/VDDCORE
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 SOSCO/T1CK/CN0/RC14
ETXEN/PMD5/RE5 1
47 SOSCI/CN1/RC13
ETXD0/PMD6/RE6 2
46 OC1/INT0/RD0
ETXD1/PMD7/RE7 3
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
4
44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 5
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 43 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
6
42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8
MCLR 7
VSS 9 PIC32MX675F512H 40 OSC2/CLKO/RC15
VDD 10 PIC32MX695F512H 39 OSC1/CLKI/RC12

38 VDD
AN5/C1IN+/VBUSON/CN7/RB5 11
37 D+/RG2
AN4/C1IN-/CN6/RB4 12
36 D-/RG3
AN3/C2IN+/CN5/RB3 13
35 VUSB
34 VBUS
PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15
33 USBID/RF3
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AVDD
VDD
AVSS
VSS
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AN9/C2OUT/PMA7/RB9
TDO/AN11/PMA12/RB11
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
VSS externally.

PIC32MX5XX/6XX/7XX
ERXCLK/EREFCLKPMD3/RE3
C1RX/AETXD1/ERXD3/RF0
C1TX/AETXD0/ERXD2/RF1
ERXERR/PMD4/RE4
ERXD1/PMD0/RE0
ERXD0/PMD1/RE1
PMRD/CN14/RD5
VCAP/VDDCORE
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ETXEN/PMD5/RE5 1
47 SOSCI/CN1/RC13
ETXD0/PMD6/RE6 2
46 OC1/INT0/RD0
ETXD1/PMD7/RE7 3
45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 4
44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 5
43 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 6
MCLR 7 PIC32MX775F256H
41 Vss
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 8 PIC32MX775F512H
40 OSC2/CLKO/RC15
VSS 9 PIC32MX795F512H OSC1/CLKI/RC12
39
VDD 10
38 VDD
37 D+/RG2
36 D-/RG3
35 VUSB
34 VBUS
33 USBID/RF3
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AN14/C2RX/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14
PGED2/AN7/RB7
TCK/AN12/PMA11/RB12
VDD
AVSS
VSS
PGEC2/AN6/OCFA/RB6
AN8/C2TX/SS3A/U3BRX/U3ACTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TDO/AN11/PMA12/RB11
TDI/AN13/PMA10/RB13
AVDD
VSS externally.

PIC32MX5XX/6XX/7XX
64-Pin TQFP = Pins are up to 5V tolerant
SCK1A/U1BTX/U1ARTS/OC2/RD1
PMRD/CN14/RD5
VCAP/VDDCORE
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
C1RX/RF0
CN16/RD7
CN15/RD6
C1TX/RF1
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5 1 48 SOSCO/T1CK/CN0/RC14
PMD7/RE7 3 46 OC1/INT0/RD0
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 4 45 IC4/PMCS1/PMA14/INT4/RD11
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 5 44 SCL1/IC3/PMCS2/PMA15/INT3/RD10
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 6 43 SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
MCLR 7 42 RTCC/IC1/INT1/RD8
VSS 9 40 OSC2/CLKO/RC15
VDD
PIC32MX575F512H
10 39 OSC1/CLKI/RC12
AN5/C1IN+/VBUSON/CN7/RB5 11 38 VDD
AN4/C1IN-/CN6/RB4 12 37 D+/RG2
AN3/C2IN+/CN5/RB3 13 36 D-/RG3
PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15 34 VBUS
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16 33 USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AN9/C2OUT/PMA7/RB9
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
TDO/AN11/PMA12/RB11
TDI/AN13/PMA10/RB13
AVDD
VDD
TCK/AN12/PMA11/RB12
AVSS
VSS

PIC32MX5XX/6XX/7XX
AETXD0/ERXD2/RF1
AETXD1/ERXD3/RF0
ERXERR/PMD4/RE4
ERXD1/PMD0/RE0
ERXD0/PMD1/RE1
PMRD/CN14/RD5
VCAP/VDDCORE
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ETXEN/PMD5/RE5 1
47 SOSCI/CN1/RC13
ETXD0/PMD6/RE6 2
ETXD1/PMD7/RE7 46 OC1/INT0/RD0
3
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
4
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
5
6
MCLR 42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8
7 PIC32MX675F256H 41 Vss
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 8 PIC32MX675F512H 40 OSC2/CLKO/RC15
VSS 9
PIC32MX695F512H 39 OSC1/CLKI/RC12
VDD 10
38 VDD
37 D+/RG2
36 D-/RG3
35 VUSB
34 VBUS
33 USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PGED2/AN7/RB7
TCK/AN12/PMA11/RB12
VDD
AVSS
PGEC2/AN6/OCFA/RB6
AN9/C2OUT/PMA7/RB9
TDO/AN11/PMA12/RB11
TDI/AN13/PMA10/RB13
AVDD
VSS

PIC32MX5XX/6XX/7XX
C1RX/AETXD1/ERXD3/RF0
C1TX/AETXD0/ERXD2/RF1
ERXERR/PMD4/RE4
ERXD0/PMD1/RE1
ERXD1/PMD0/RE0
PMRD/CN14/RD5
VCAP/VDDCORE
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ETXEN/PMD5/RE5 48 SOSCO/T1CK/CN0/RC14
1
ETXD0/PMD6/RE6 2 47 SOSCI/CN1/RC13
ETXD1/PMD7/RE7 46 OC1/INT0/RD0
3
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 4 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
5
6
MCLR 7 PIC32MX775F256H
41 Vss
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 8 PIC32MX775F512H OSC2/CLKO/RC15
VSS 40
9 PIC32MX795F512H 39 OSC1/CLKI/RC12
VDD 10
AN5/C1IN+/VBUSON/CN7/RB5 38 VDD
11
AN4/C1IN-/CN6/RB4 37 D+/RG2
12
AN3/C2IN+/CN5/RB3 36 D-/RG3
13
35 VUSB
PGEC1/AN1/VREF-/CVREF-/CN3/RB1 34 VBUS
15
33 USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AVDD
VDD
AVSS
VSS
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AN9/C2OUT/PMA7/RB9
TDO/AN11/PMA12/RB11
AN8/C2TX/SS3A/U3BRX/U3ACTS/C1OUT/RB8
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/C2RX/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14

PIC32MX5XX/6XX/7XX
OC5/PMWR/CN13/RD4
PMD13/CN19/RD13
PMD15/CN16/RD7
PMD14/CN15/RD6
C1RX/PMD11/RF0
C1TX/PMD10/RF1
PMRD/CN14/RD5
IC5/PMD12/RD12
VCAP/VDDCORE
TRD0/RG13
TRD1/RG12
TRD2/RG14
TRCLK/RA6
PMD8/RG0
PMD9/RG1
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
TRD3/RA7
OC4/RD3
OC3/RD2
OC2/RD1
VDD
99
98
97
96
95
94
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
93
100
RG15 1 75 VSS
VDD 2 74 SOSCO/T1CK/CN0/RC14
PMD6/RE6 4 72 SDO1/OC1/INT0/RD0
PMD7/RE7 5 71 IC4/PMCS1/PMA14/RD11
T2CK/RC1 6 70 SCK1/IC3/PMCS2/PMA15/RD10
T3CK/RC2 7 69 SS1/IC2/RD9
T4CK/RC3 8 68 RTCC/IC1/RD8
T5CK/SDI1/RC4 9 67 SDA1/INT4/RA15
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 10 66 SCL1/INT3/RA14
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 11 65 VSS
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 12 64 OSC2/CLKO/RC15
MCLR 13 63 OSC1/CLKI/RC12
PIC32MX575F512L
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 14 62 VDD
VSS
PIC32MX575F256L
15 61 TDO/RA5
VDD 16 60 TDI/RA4
TMS/RA0 17 59 SDA2/RA3
INT1/RE8 18 58 SCL2/RA2
INT2/RE9 19 57 D+/RG2
AN5/C1IN+/VBUSON/CN7/RB5 20 56 D-/RG3
AN3/C2IN+/CN5/RB3 22 54 VBUS
AN2/C2IN-/CN4/RB2 23 53 SCL1A/SDO1A/U1ATX/RF8
PGEC1/AN1/CN3/RB1 24 52 SDA1A/SDI1A/U1ARX/RF2
PGED1/AN0/CN2/RB0 25 51 USBID/RF3
26
27
39
40
41
42
43
44
45
46
47
48
49
50
28
29
30
31
32
33
34
35
36
37
38
AVDD
VDD
VDD
AVSS
VSS
VSS
TCK/RA1
AC1TX/SCK3A/U3BTX/U3ARTS/RF13
AC1RX/SS3A/U3BRX/U3ACTS/RF12
AN13/PMA10/RB13
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN11/PMA12/RB11
AN14/PMALH/PMA1/RB14
SS1A/U1BRX/U1ACTS/CN20/RD14
SCK1A/U1BTX/U1ARTS/CN21/RD15
AN12/PMA11/RB12
AN10/CVREFOUT/PMA13/RB10
VREF-/CVREF-/PMA7/RA9
VREF+/CVREF+/PMA6/RA10

DS61156C-page 12
PIC32MX5XX/6XX/7XX
ETXCLK/PMD15/CN16/RD7
ETXD3/PMD13/CN19/RD13
100-Pin TQFP
ETXEN/PMD14/CN15/RD6
= Pins are up to 5V tolerant
ETXD2/IC5/PMD12/RD12
OC5/PMWR/CN13/RD4
ETXERR/PMD9/RG1
ETXD0/PMD10/RF1
ETXD1/PMD11/RF0
PMRD/CN14/RD5
VCAP/VDDCORE
TRD2/RG14
TRD0/RG13
TRD1/RG12
TRCLK/RA6
PMD8/RG0
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
PMD4/RE4
TRD3/RA7
OC4/RD3
OC3/RD2
OC2/RD1
VDD
75 VSS
100
96
95
94
89
88
87
82
81
80
79
99
98
97
93
92
91
90
86
85
84
83
78
77
76
AERXERR/RG15 1 73 SOSCI/CN1/RC13
VDD 2 72 SDO1/OC1/INT0/RD0
PMD5/RE5 3 71 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
PMD6/RE6 4 PIC32MX675F256L SCK1/IC3/PMCS2/PMA15/RD10
70
PMD7/RE7 5 PIC32MX675F512L 69 SS1/IC2/RD9
T2CK/RC1 6 PIC32MX695F512L 68 RTCC/EMDIO/AEMDIO/IC1/RD8
T3CK/RC2 7 67 AETXEN/SDA1/INT4/RA15
T4CK/RC3 8 66 AETXCLK/SCL1/INT3/RA14
T5CK/SDI1/RC4 9 65 VSS
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 10 64 OSC2/CLKO/RC15
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 11 63 OSC1/CLKI/RC12
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 12 VDD
Preliminary
62
MCLR 13
61 TDO/RA5
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 14
60 TDI/RA4
VSS 15
59 SDA2/RA3
VDD 16
58 SCL2/RA2
TMS/RA0 17
57 D+/RG2
AERXD0/INT1/RE8 18
56 D-/RG3
AERXD1/INT2/RE9 19
55 VUSB
54 VBUS
53 SCL1A/SDO1A/U1ATX/RF8
52 SDA1A/SDI1A/U1ARX/RF2
51 USBID/RF3
PGEC1/AN1/CN3/RB1 24
39
40
41
42
43
44
50
27
45
46
47
48
49
28
34
35
36
37
38
29
30
31
32
33
PGED1/AN0/CN2/RB0 25
AN11/ERXERR/AETXERR/PMA12/RB11
PGED2/AN7/RB7
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN13/ERXD1/AECOL/PMA10/RB13
AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
AVDD
VDD
VDD
AVSS
VSS
VSS
VREF-/CVREF-/AERXD2/PMA7/RA9
SS3A/U3BRX/U3ACTS/RF12
VREF+/CVREF+/AERXD3/PMA6/RA10
SCK3A/U3BTX/U3ARTS/RF13
TCK/RA1
AN12/ERXD0/AECRS/PMA11/RB12
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
 2010 Microchip Technology Inc.
100-Pin TQFP
ETXCLK/PMD15/CN16/RD7
ETXD3/PMD13/CN19/RD13
= Pins are up to 5V tolerant
C2TX/ETXERR/PMD9/RG1
ETXEN/PMD14/CN15/RD6
C1RX/ETXD1/PMD11/RF0
C1TX/ETXD0/PMD10/RF1
ETXD2/IC5/PMD12/RD12
OC5/PMWR/CN13/RD4
C2RX/PMD8/RG0
PMRD/CN14/RD5
VCAP/VDDCORE
TRD1/RG12
TRD0/RG13
TRD2/RG14
TRCLK/RA6
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
TRD3/RA7
OC4/RD3
OC3/RD2
OC2/RD1
VSS
VDD
75
73 SOSCI/CN1/RC13
98
96
94
92
90
87
85
83
81
79
77
100
99
97
95
93
91
89
88
86
84
82
80
78
76
72 SDO1/OC1/INT0/RD0
AERXERR/RG15 1
71 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
VDD 2
70 SCK1/IC3/PMCS2/PMA15/RD10
PMD5/RE5 3
PMD6/RE6 4 PIC32MX775F256L 69 SS1/IC2/RD9
68 RTCC/EMDIO/AEMDIO/IC1/RD8
PMD7/RE7 5 PIC32MX775F512L
67 AETXEN/SDA1/INT4/RA15
T2CK/RC1 6 PIC32MX795F512L 66 AETXCLK/SCL1/INT3/RA14
T3CK/AC2TX/RC2 7
65 VSS
T4CK/AC2RX/RC3 8
64 OSC2/CLKO/RC15
T5CK/SDI1/RC4 9
63 OSC1/CLKI/RC12
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 10
62 VDD
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 11
Preliminary
61 TDO/RA5
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 12
60 TDI/RA4
MCLR 13
59 SDA2/RA3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 14
58 SCL2/RA2
VSS 15
PIC32MX5XX/6XX/7XX
57 D+/RG2
VDD 16
56 D-/RG3
TMS/RA0 17
55 VUSB
AERXD0/INT1/RE8 18
54 VBUS
AERXD1/INT2/RE9 19
53 SCL1A/SDO1A/U1ATX/RF8
52 SDA1A/SDI1A/U1ARX/RF2
51 USBID/RF3
41
42
46
47
48
26
27
39
40
43
44
45
49
50
28
32
33
37
38
29
30
31
34
35
36
PGEC1/AN1/CN3/RB1 24
PGED1/AN0/CN2/RB0 25
PGED2/AN7/RB7
VREF-/CVREF-/AERXD2/PMA7/RA9
AN9/C2OUT/RB9
AN12/ERXD0/AECRS/PMA11/RB12
AN11/ERXERR/AETXERR/PMA12/RB11
AC1TX/SCK3A/U3BTX/U3ARTS/RF13
AN13/ERXD1/AECOL/PMA10/RB13
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
AVDD
VDD
VDD
AVSS
VSS
VSS
AC1RX/SS3A/U3BRX/U3ACTS/RF12
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
PGEC2/AN6/OCFA/RB6
VREF+/CVREF+/AERXD3/PMA6/RA10
AN8/C1OUT/RB8
TCK/RA1
DS61156C-page 13
PIC32MX5XX/6XX/7XX
121-Pin XBGA(1) = Pins are up to 5V tolerant
PIC32MX575F256L
PIC32MX675F256L
PIC32MX775F256L
PIC32MX575F512L
PIC32MX675F512L
PIC32MX695F512L
PIC32MX775F512L
PIC32MX795F512L
1 2 3 4 5 6 7 8 9 10 11
A
RE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1
B NC RG15 RE2 RE1 RA7 RF0 VCAP/ RD5 RD3 VSS RC14
VDDCORE
C
RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11
D
RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10
E
RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14
F
MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15
G
RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4
H
RB5 RB4 VSS VDD NC VDD NC VBUS VUSB RG2 RA2
J
RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3
K
RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2
L
RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5
Note 1: Refer to Table 2, Table 3 and Table 4 for full pin names.

PIC32MX5XX/6XX/7XX
TABLE 2: PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES
Pin Pin
Full Pin Name Full Pin Name
Number Number
A1 PMD4/RE4 E8 SDA1/INT4/RA15
A2 PMD3/RE3 E9 RTCC/IC1/RD8
A3 TRD0/RG13 E10 SS1/IC2/RD9
A4 PMD0/RE0 E11 SCL1/INT3/RA14
A5 PMD8/RG0 F1 MCLR
A6 C1TX/PMD10/RF1 F2 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
A7 VDD F3 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
A8 VSS F4 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
A9 IC5/PMD12/RD12 F5 VSS
A10 OC3/RD2 F6 No Connect (NC)
B1 No Connect (NC) F8 VDD
B2 RG15 F9 OSC1/CLKI/RC12
B3 PMD2/RE2 F10 VSS
B4 PMD1/RE1 F11 OSC2/CLKO/RC15
B5 TRD3/RA7 G1 INT1/RE8
B6 C1RX/PMD11/RF0 G2 INT2/RE9
B7 VCAP/VDDCORE G3 TMS/RA0
B8 PMRD/CN14/RD5 G4 No Connect (NC)
B9 OC4/RD3 G5 VDD
B10 VSS G6 VSS
B11 SOSCO/T1CK/CN0/RC14 G7 VSS
C1 PMD6/RE6 G8 No Connect (NC)
C2 VDD G9 TDO/RA5
C3 TRD1/RG12 G10 SDA2/RA3
C4 TRD2/RG14 G11 TDI/RA4
C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5
C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4
C7 PMD15/CN16/RD7 H3 VSS
C8 OC5/PMWR/CN13/RD4 H4 VDD
C9 VDD H5 No Connect (NC)
C10 SOSCI/CN1/RC13 H6 VDD
C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)
D1 T2CK/RC1 H8 VBUS
D2 PMD7/RE7 H9 VUSB
D3 PMD5/RE5 H10 D+/RG2
D4 VSS H11 SCL2/RA2
D5 VSS J1 AN3/C2IN+/CN5/RB3
D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2
D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7
D8 PMD13/CN19/RD13 J4 AVDD
D9 SDO1/OC1/INT0/RD0 J5 AN11/PMA12/RB11
D10 No Connect (NC) J6 TCK/RA1
D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12
E1 T5CK/SDI1/RC4 J8 No Connect (NC)
E2 T4CK/RC3 J9 No Connect (NC)
E3 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 J10 SCL1A/SDO1A/U1ATX/RF8
E4 T3CK/RC2 J11 D-/RG3
E5 VDD K1 PGEC1/AN1/CN3/RB1
E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0
E7 VSS K3 VREF+/CVREF+/PMA6/RA10

PIC32MX5XX/6XX/7XX
TABLE 2: PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED)
Pin Pin
Number Number
K4 AN8/C1OUT/RB8 L3 AVSS
K5 No Connect (NC) L4 AN9/C2OUT/RB9
K6 AC1RX/SS3A/U3BRX/U3ACTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10
K7 AN14/PMALH/PMA1/RB14 L6 AC1TX/SCK3A/U3BTX/U3ARTS/RF13
K8 VDD L7 AN13/PMA10/RB13
K9 SCK1A/U1BTX/U1ARTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15
K10 USBID/RF3 L9 SS1A/U1BRX/U1ACTS/CN20/RD14
K11 SDA1A/SDI1A/U1ARX/RF2 L10 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
L1 PGEC2/AN6/OCFA/RB6 L11 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
L2 VREF-/CVREF-/PMA7/RA9

PIC32MX5XX/6XX/7XX
TABLE 3: PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES
Pin Pin
Number Number
A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15
A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8
A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14
A5 PMD8/RG0 F1 MCLR
A6 ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL2A/SDO2A/
U2ATX/PMA3/CN10/RG8
A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2A/U2BRX/
U2ACTS/PMA2/CN11/RG9
A8 VSS F4 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
A9 ETXD2/IC5/PMD12/RD12 F5 VSS
B2 AERXERR/RG15 F9 OSC1/CLKI/RC12
B3 PMD2/RE2 F10 VSS
B5 TRD3/RA7 G1 AERXD0/INT1/RE8
B6 ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9
B9 OC4/RD3 G5 VDD
B10 VSS G6 VSS
C2 VDD G9 TDO/RA5
C7 ETXCLK/PMD15/CN16/RD7 H3 VSS
C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)
D1 T2CK/RC1 H8 VBUS
D2 PMD7/RE7 H9 VUSB
D4 VSS H11 SCL2/RA2
D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7
D8 ETXD3/PMD13/CN19/RD13 J4 AVDD
D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11
D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12
E2 T4CK/RC3 J9 No Connect (NC)
E3 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 J10 SCL1A/SDO1A/U1ATX/RF8
E4 T3CK/RC2 J11 D-/RG3
E6 EXTERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0
E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10

PIC32MX5XX/6XX/7XX
TABLE 3: PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES
Pin Pin
Number Number
K6 SS3A/U3BRX/U3ACTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10
K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 SCK3A/U3BTX/U3ARTS/RF13
K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13
K9 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K10 USBID/RF3 L9 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
L2 VREF-/CVREF-/AERXD2/PMA7/RA9

PIC32MX5XX/6XX/7XX
TABLE 4: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES
Pin Pin
Number Number
A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15
A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8
A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14
A5 C2RX/PMD8/RG0 F1 MCLR
A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/
U2ATX/PMA3/CN10/RG8
A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/
U2ACTS/PMA2/CN11/RG9
A8 VSS F4 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
A9 ETXD2/IC5/PMD12/RD12 F5 VSS
B2 AERXERR/RG15 F9 OSC1/CLKI/RC12
B3 PMD2/RE2 F10 VSS
B5 TRD3/RA7 G1 AERXD0/INT1/RE8
B6 C1RX/ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9
B9 OC4/RD3 G5 VDD
B10 VSS G6 VSS
C2 VDD G9 TDO/RA5
C7 ETXCLK/PMD15/CN16/RD7 H3 VSS
C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)
D1 T2CK/RC1 H8 VBUS
D2 PMD7/RE7 H9 VUSB
D4 VSS H11 SCL2/RA2
D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7
D8 ETXD3/PMD13/CN19/RD13 J4 AVDD
D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11
D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12
E2 T4CK/AC2RX/RC3 J9 No Connect (NC)
E3 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 J10 SCL1A/SDO1A/U1ATX/RF8
E4 T3CK/AC2TX/RC2 J11 D-/RG3
E6 C2TX/EXTERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0
E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10

PIC32MX5XX/6XX/7XX
TABLE 4: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES
Pin Pin
Number Number
K6 AC1RX/SS3A/U3BRX/U3ACTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10
K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK3A/U3BTX/U3ARTS/RF13
K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13
K9 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K10 USBID/RF3 L9 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
L2 VREF-/CVREF-/AERXD2/PMA7/RA9

PIC32MX5XX/6XX/7XX
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 23
2.0 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 35
3.0 PIC32MX MCU........................................................................................................................................................................... 39
4.0 Memory Organization ................................................................................................................................................................. 45
5.0 Flash Program Memory............................................................................................................................................................ 105
6.0 Resets ...................................................................................................................................................................................... 107
7.0 Interrupt Controller ................................................................................................................................................................... 109
8.0 Oscillator Configuration ............................................................................................................................................................ 113
9.0 Prefetch Cache......................................................................................................................................................................... 115
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................ 117
11.0 USB On-The-Go (OTG)............................................................................................................................................................ 119
12.0 I/O Ports ................................................................................................................................................................................... 121
13.0 Timer1 ...................................................................................................................................................................................... 123
14.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 125
15.0 Input Capture............................................................................................................................................................................ 127
16.0 Output Compare....................................................................................................................................................................... 129
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 131
18.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 133
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 135
20.0 Parallel Master Port (PMP) ...................................................................................................................................................... 137
21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 139
22.0 10-Bit Analog-to-Digital Converter (ADC)................................................................................................................................. 141
23.0 Controller Area Network (CAN) ................................................................................................................................................ 143
24.0 Ethernet Controller ................................................................................................................................................................... 145
25.0 Comparator .............................................................................................................................................................................. 147
26.0 Comparator Voltage Reference (CVref) ................................................................................................................................... 149
27.0 Power-Saving Features ........................................................................................................................................................... 151
28.0 Special Features ...................................................................................................................................................................... 153
29.0 Instruction Set .......................................................................................................................................................................... 165
30.0 Development Support............................................................................................................................................................... 167
31.0 Electrical Characteristics .......................................................................................................................................................... 171
32.0 Packaging Information.............................................................................................................................................................. 213
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PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
1.0 DEVICE OVERVIEW This document contains device-specific information for
PIC32MX5XX/6XX/7XX devices.
Note 1: This data sheet summarizes the features Figure 1-1 shows a general block diagram of the core
of the PIC32MX5XX/6XX/7XX family of and peripheral modules in the PIC32MX5XX/6XX/7XX
devices. It is not intended to be a family of devices.
comprehensive reference source. To
complement the information in this data Table 1-1 lists the functions of the various pins shown
sheet, refer to the related section of the in the pinout diagrams.
“PIC32MX Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 1-1: BLOCK DIAGRAM(1,2)

VCAP/VDDCORE
OSC2/CLKO OSC/SOSC
OSC1/CLKI Oscillators Power-up VDD, VSS
Timer
FRC/LPRC MCLR
Oscillators Voltage Oscillator
Regulator Start-up Timer
PLL
Power-on
Precision
Dividers Band Gap Reset
Reference
PLL-USB Watchdog
USBCLK Timer
SYSCLK Brown-out
Timing Reset
Generation PBCLK
Peripheral Bus Clocked by SYSCLK

CN1-22
PORTA
Timer1-5
Priority
JTAG Interrupt
BSCAN Controller PWM
CAN1, CAN2
Peripheral Bus Clocked by PBCLK

ETHERNET
PORTB OC1-5
DMAC
USB
ICD
EJTAG INT 32
MIPS32® M4K™ IC1-5

PORTC CPU Core
IS DS
32 32 32 32 32
32 SPI1,1A,2A,3A
32 32
PORTD
Bus Matrix
I2C1,2,1A,
32 32 32 2A,3A
PORTE 32
Prefetch
Peripheral Bridge
Module Data RAM
PMP
PORTF 10-Bit ADC

128
UART1A,1B,2A,
2B,3A,3B
Controller
128-Bit Wide
Flash
PORTG Program Flash Memory RTCC
Comparators
Note 1: Some features are not available on all device variants.
2: BOR functionality is provided when the on-board voltage regulator is enabled.

PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin Description
Type Type
QFN/TQFP TQFP XBGA
AN0 16 25 K2 I Analog Analog input channels.
AN1 15 24 K1 I Analog
AN2 14 23 J2 I Analog
AN4 12 21 H2 I Analog
AN5 11 20 H1 I Analog
AN6 17 26 L1 I Analog
CLKI 39 63 F9 I ST/CMOS External clock source input. Always associated
with OSC1 pin function.
CLKO 40 64 F11 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. Optionally
functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1 39 63 F9 I ST/CMOS Oscillator crystal input. ST buffer when
configured in RC mode; CMOS otherwise.
OSC2 40 64 F11 I/O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. Optionally
functions as CLKO in RC and EC modes.
SOSCI 47 73 C10 I ST/CMOS 32.768 kHz low-power oscillator crystal input;
CMOS otherwise.
SOSCO 48 74 B11 O — 32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.

PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
CN0 48 74 B11 I ST Change notification inputs.
CN1 47 73 C10 I ST Can be software programmed for internal weak
pull-ups on all inputs.
CN2 16 25 K2 I ST
CN3 15 24 K1 I ST
CN4 14 23 J2 I ST
CN5 13 22 J1 I ST
CN6 12 21 H2 I ST
CN7 11 20 H1 I ST
CN8 4 10 E3 I ST
CN9 5 11 F4 I ST
CN10 6 12 F2 I ST
CN11 8 14 F3 I ST
CN12 30 44 L8 I ST
CN13 52 81 C8 I ST
CN14 53 82 B8 I ST
CN15 54 83 D7 I ST
CN16 55 84 C7 I ST
CN17 31 49 L10 I ST
CN18 32 50 L11 I ST
CN19 — 80 D8 I ST
CN20 — 47 L9 I ST
CN21 — 48 K9 I ST
IC1 42 68 E9 I ST Capture Inputs 1-5.
IC2 43 69 E10 I ST
IC3 44 70 D11 I ST
IC4 45 71 C11 I ST
IC5 52 79 A9 I ST
OCFA 17 26 L1 I ST Output Compare Fault A input.
OC1 46 72 D9 O — Output Compare Output 1.
OC2 49 76 A11 O — Output Compare Output 2
OC3 50 77 A10 O — Output Compare Output 3.
OC4 51 78 B9 O — Output Compare Output 4.
OC5 52 81 C8 O — Output Compare Output 5.
OCFB 30 44 L8 I ST Output Compare Fault B input.
INT0 46 72 D9 I ST External Interrupt 0.
INT1 42 18 G1 I ST External Interrupt 1.
INT2 43 19 G2 I ST External Interrupt 2.
INT3 44 66 E11 I ST External Interrupt 3.
INT4 45 67 E8 I ST External Interrupt 4.

PIC32MX5XX/6XX/7XX
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
RA0 — 17 G3 I/O ST PORTA is a bidirectional I/O port.
RA1 — 38 J6 I/O ST
RA2 — 58 H11 I/O ST
RA3 — 59 G10 I/O ST
RA4 — 60 G11 I/O ST
RA5 — 61 G9 I/O ST
RA6 — 91 C5 I/O ST
RA7 — 92 B5 I/O ST
RA9 — 28 L2 I/O ST
RA10 — 29 K3 I/O ST
RA14 — 66 E11 I/O ST
RA15 — 67 E8 I/O ST
RB0 16 25 K2 I/O ST PORTB is a bidirectional I/O port.
RB1 15 24 K1 I/O ST
RB2 14 23 J2 I/O ST
RB3 13 22 J1 I/O ST
RB4 12 21 H2 I/O ST
RB5 11 20 H1 I/O ST
RB6 17 26 L1 I/O ST
RB7 18 27 J3 I/O ST
RB8 21 32 K4 I/O ST
RB9 22 33 L4 I/O ST
RB10 23 34 L5 I/O ST
RB11 24 35 J5 I/O ST
RB12 27 41 J7 I/O ST
RB13 28 42 L7 I/O ST
RB14 29 43 K7 I/O ST
RB15 30 44 L8 I/O ST
RC1 — 6 D1 I/O ST PORTC is a bidirectional I/O port.
RC2 — 7 E4 I/O ST
RC3 — 8 E2 I/O ST
RC4 — 9 E1 I/O ST
RC12 39 63 F9 I/O ST
RC13 47 73 C10 I/O ST
RC14 48 74 B11 I/O ST
RC15 40 64 F11 I/O ST

PIC32MX5XX/6XX/7XX
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
RD0 46 72 D9 I/O ST PORTD is a bidirectional I/O port.
RD1 49 76 A11 I/O ST
RD2 50 77 A10 I/O ST
RD3 51 78 B9 I/O ST
RD4 52 81 C8 I/O ST
RD5 53 82 B8 I/O ST
RD6 54 83 D7 I/O ST
RD7 55 84 C7 I/O ST
RD8 42 68 E9 I/O ST
RD9 43 69 E10 I/O ST
RD10 44 70 D11 I/O ST
RD11 45 71 C11 I/O ST
RD12 — 79 A9 I/O ST
RD13 — 80 D8 I/O ST
RD14 — 47 L9 I/O ST
RD15 — 48 K9 I/O ST
RE0 60 93 A4 I/O ST PORTE is a bidirectional I/O port.
RE1 61 94 B4 I/O ST
RE2 62 98 B3 I/O ST
RE3 63 99 A2 I/O ST
RE4 64 100 A1 I/O ST
RE5 1 3 D3 I/O ST
RE6 2 4 C1 I/O ST
RE7 3 5 D2 I/O ST
RE8 — 18 G1 I/O ST
RE9 — 19 G2 I/O ST
RF0 58 87 B6 I/O ST PORTF is a bidirectional I/O port.
RF1 59 88 A6 I/O ST
RF2 — 52 K11 I/O ST
RF3 33 51 K10 I/O ST
RF4 31 49 L10 I/O ST
RF5 32 50 L11 I/O ST
RF8 — 53 J10 I/O ST
RF12 — 40 K6 I/O ST
RF13 — 39 L6 I/O ST

PIC32MX5XX/6XX/7XX
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
RG0 — 90 A5 I/O ST PORTG is a bidirectional I/O port.
RG1 — 89 E6 I/O ST
RG6 4 10 E3 I/O ST
RG7 5 11 F4 I/O ST
RG8 6 12 F2 I/O ST
RG9 8 14 F3 I/O ST
RG12 — 96 C3 I/O ST
RG13 — 97 A3 I/O ST
RG14 — 95 C4 I/O ST
RG15 — 1 B2 I/O ST
RG2 37 57 H10 I ST PORTG input pins.
RG3 36 56 J11 I ST
T1CK 48 74 B11 I ST Timer1 external clock input.
T2CK — 6 D1 I ST Timer2 external clock input.
T3CK — 7 E4 I ST Timer3 external clock input.
U1ACTS 43 47 L9 I ST UART1A clear to send.
U1ARTS 49 48 K9 O — UART1A ready to send.
U1ARX 50 52 K11 I ST UART1A receive.
U1ATX 51 53 J10 O — UART1A transmit.
U2ACTS 8 14 F3 I ST UART2A clear to send.
U2ARTS 4 10 E3 O — UART2A ready to send.
U2ARX 5 11 F4 I ST UART2A receive.
U2ATX 6 12 F2 O — UART2A transmit.
U3ACTS 21 40 K6 I ST UART3A clear to send.
U3ARTS 29 39 L6 O — UART3A ready to send.
U3ARX 31 49 L10 I ST UART3A receive.
U3ATX 32 50 L11 O — UART3A transmit.
U1BRX 43 47 L9 I ST UART1B receive.
U1BTX 49 48 K9 O — UART1B transmit.
U2BRX 8 14 F3 I ST UART2B receive.
U2BTX 4 10 E3 O — UART2B transmit.
U3BRX 21 40 K6 I ST UART3B receive.
U3BTX 29 39 L6 O — UART3B transmit.
SCK1 — 70 D11 I/O ST Synchronous serial clock input/output for SPI1.
SDI1 — 9 E1 I ST SPI1 data in.

PIC32MX5XX/6XX/7XX
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
SDO1 — 72 D9 O — SPI1 data out.
SS1 — 69 E10 I/O ST SPI1 slave synchronization or frame pulse I/O.
SCK1A 49 48 K9 I/O ST Synchronous serial clock input/output for
SPI1A.
SDI1A 50 52 K11 I ST SPI1A data in.
SDO1A 51 53 J10 O — SPI1A data out.
SS1A 43 47 L9 I/O ST SPI1A slave synchronization or frame pulse
I/O.
SCK2A 4 10 E3 I/O ST Synchronous serial clock input/output for
SPI2A.
SDI2A 5 11 F4 I ST SPI2A data in.
SDO2A 6 12 F2 O — SPI2A data out.
SS2A 8 14 F3 I/O ST SPI2A slave synchronization or frame pulse
I/O.
SCK3A 29 39 L6 I/O ST Synchronous serial clock input/output for
SPI3A.
SDI3A 31 49 L10 I ST SPI3A data in.
SDO3A 32 50 L11 O — SPI3A data out.
SS3A 21 40 K6 I/O ST SPI3A slave synchronization or frame pulse
I/O.
SCL1 44 66 E11 I/O ST Synchronous serial clock input/output for I2C1.
SDA1 43 67 E8 I/O ST Synchronous serial data input/output for I2C1.
SCL1A 51 53 J10 I/O ST Synchronous serial clock input/output for
I2C1A.
SDA1A 50 52 K11 I/O ST Synchronous serial data input/output for
I2C1A.
SCL2 — 58 H11 I/O ST Synchronous serial clock input/output for I2C2.
SDA2 — 59 G10 I/O ST Synchronous serial data input/output for I2C2.
SCL2A 6 12 F2 I/O ST Synchronous serial clock input/output for
I2C2A.
SDA2A 5 11 F4 I/O ST Synchronous serial data input/output for
I2C2A.
SCL3A 32 50 L11 I/O ST Synchronous serial clock input/output for
I2C3A.
SDA3A 31 49 L10 I/O ST Synchronous serial data input/output for
I2C3A.
TMS 23 17 G3 I ST JTAG Test mode select pin.
TCK 27 38 J6 I ST JTAG test clock input pin.
TDI 28 60 G11 I ST JTAG test data input pin.
TDO 24 61 G9 O — JTAG test data output pin.
RTCC 42 68 E9 O — Real-Time Clock alarm output.

PIC32MX5XX/6XX/7XX
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
CVREF- 15 28 L2 I Analog Comparator Voltage Reference (low).
CVREF+ 16 29 K3 I Analog Comparator Voltage Reference (high).
CVREFOUT 23 34 L5 O Analog Comparator Voltage Reference output.
C1IN- 12 21 H2 I Analog Comparator 1 negative input.
C1IN+ 11 20 H1 I Analog Comparator 1 positive input.
C1OUT 21 32 K4 O — Comparator 1 output.
C2IN- 14 23 J2 I Analog Comparator 2 negative input.
C2IN+ 13 22 J1 I Analog Comparator 2 positive input.
C2OUT 22 33 L4 O — Comparator 2 output.
PMA0 — 44 L8 I/O TTL/ST Parallel Master Port Address Bit 0 input
(Buffered Slave modes) and output (Master
modes).
PMA1 — 43 K7 I/O TTL/ST Parallel Master Port Address Bit 1 input
(Buffered Slave modes) and output (Master
modes).
PMA2 8 14 F3 O — Parallel Master Port address (Demultiplexed
PMA3 6 12 F2 O — Master modes).
PMA4 5 11 F4 O —
PMA5 4 10 E3 O —
PMA6 16 29 K3 O —
PMA7 22 28 L2 O —
PMA8 32 50 L11 O —
PMA9 31 49 L10 O —
PMA10 28 42 L7 O —
PMA11 27 41 J7 O —
PMA12 24 35 J5 O —
PMA13 23 34 L5 O —
PMA14 45 71 C11 O —
PMA15 44 70 D11 O —
PMCS1 45 71 C11 O — Parallel Master Port Chip Select 1 strobe.
PMCS2 44 70 D11 O — Parallel Master Port Chip Select 2 strobe.

PIC32MX5XX/6XX/7XX
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
PMD0 60 93 A4 I/O TTL/ST Parallel Master Port data (Demultiplexed
PMD1 61 94 B4 I/O TTL/ST Master mode) or address/data (Multiplexed
Master modes).
PMD2 62 98 B3 I/O TTL/ST
PMD3 63 99 A2 I/O TTL/ST
PMD4 64 100 A1 I/O TTL/ST
PMD5 1 3 D3 I/O TTL/ST
PMD6 2 4 C1 I/O TTL/ST
PMD7 3 5 D2 I/O TTL/ST
PMD8 — 90 A5 I/O TTL/ST
PMD9 — 89 E6 I/O TTL/ST
PMD11 — 87 B6 I/O TTL/ST
PMD13 — 80 D8 I/O TTL/ST
PMD14 — 83 D7 I/O TTL/ST
PMD15 — 84 C7 I/O TTL/ST
PMALL 30 44 L8 O — Parallel Master Port address latch enable
low byte (Multiplexed Master modes).
PMALH 29 43 K7 O — Parallel Master Port address latch enable
high byte (Multiplexed Master modes).
PMRD 53 82 B8 O — Parallel Master Port read strobe.
PMWR 52 81 C8 O — Parallel Master Port write strobe.
VBUS 34 54 H8 I Analog USB bus power monitor.
VUSB 35 55 H9 P — USB internal transceiver supply.
VBUSON 11 20 H1 O — USB Host and OTG bus power control output.
D+ 37 57 H10 I/O Analog USB D+.
D- 36 56 J11 I/O Analog USB D-.
USBID 33 51 K10 I ST USB OTG ID detect.
C1RX 58 87 B6 I ST CAN1 bus receive pin.
C1TX 59 88 A6 O — CAN1 bus transmit pin.
AC1RX 32 40 K6 I ST Alternate CAN1 bus receive pin.
AC1TX 31 39 L6 O — Alternate CAN1 bus transmit pin.
C2RX 29 90 A5 I ST CAN2 bus receive pin.
C2TX 21 89 E6 O — CAN2 bus transmit pin.
AC2RX — 8 E2 1 ST Alternate CAN2 bus receive pin.
AC2TX — 7 E4 O — Alternate CAN2 bus transmit pin.
ERXD0 61 41 J7 I ST Ethernet Receive Data 0.(2)
ERXD1 60 42 L7 I ST Ethernet Receive Data 1.(2)
ERXD2 59 43 K7 I ST Ethernet Receive Data 2.(2)

PIC32MX5XX/6XX/7XX
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
ERXD3 58 44 L8 I ST Ethernet Receive Data 3.(2)
ERXERR 64 35 J5 I ST Ethernet receive error input.(2)
ERXDV 62 12 F2 I ST Ethernet receive data valid.(2)
ECRSDV 61 12 F2 I ST Ethernet carrier sense data valid.(2)
ERXCLK 63 14 F3 I ST Ethernet receive clock.(2)
EREFCLK 63 14 F3 I ST Ethernet reference clock.(2)
ETXD0 2 88 A6 O — Ethernet Transmit Data 0.(2)
ETXD1 3 87 B6 O — Ethernet Transmit Data 1.(2)
ETXD2 43 79 A9 O — Ethernet Transmit Data 2.(2)
ETXD3 42 80 D8 O — Ethernet Transmit Data 3.(2)
ETXERR 54 89 E6 O — Ethernet transmit error.(2)
ETXEN 1 83 D7 O — Ethernet transmit enable.(2)
ETXCLK 55 84 C7 I ST Ethernet transmit clock.(2)
ECOL 44 10 E3 I ST Ethernet collision detect.(2)
ECRS 45 11 F4 I ST Ethernet carrier sense.(2)
EMDC 30 71 C11 O — Ethernet management data clock.(2)
EMDIO 49 68 E9 I/O — Ethernet management data.(2)
AERXD0 43 18 G1 I ST Alternate Ethernet Receive Data 0.(2)
AERXD1 42 19 G2 I ST Alternate Ethernet Receive Data 1.(2)
AERXD2 — 28 L2 I ST Alternate Ethernet Receive Data 2.(2)
AERXD3 — 29 K3 I ST Alternate Ethernet Receive Data 3.(2)
AERXERR 55 1 B2 I ST Alternate Ethernet receive error input.(2)
AERXDV 44 — — I ST Alternate Ethernet receive data valid.(2)
AECRSDV 44 — — I ST Alternate Ethernet carrier sense data valid.(2)
AERXCLK 45 — — I ST Alternate Ethernet receive clock.(2)
AEREFCLK 45 — — I ST Alternate Ethernet reference clock.(2)
AETXD0 59 47 L9 O — Alternate Ethernet Transmit Data 0.(2)
AETXD1 58 48 K9 O — Alternate Ethernet Transmit Data 1.(2)
AETXD2 — 44 L8 O — Alternate Ethernet Transmit Data 2.(2)
AETXD3 — 43 K7 O — Alternate Ethernet Transmit Data 3.(2)
AETXERR — 35 J5 O — Alternate Ethernet transmit error.(2)
AETXEN 54 67 E8 O — Alternate Ethernet transmit enable.(2)
AETXCLK — 66 E11 I ST Alternate Ethernet transmit clock.(2)
AECOL — 42 L7 I ST Alternate Ethernet collision detect.(2)
AECRS — 41 J7 I ST Alternate Ethernet carrier sense.(2)
TRCLK — 91 C5 O — Trace clock.

PIC32MX5XX/6XX/7XX
Pin Number(1)
Pin Buffer
Type Type
QFN/TQFP TQFP XBGA
TRD0 — 97 A3 O — Trace Data Bits 0-3.
TRD1 — 96 C3 O —
TRD2 — 95 C4 O —
TRD3 — 92 B5 O —
PGED1 16 25 K2 I/O ST Data I/O pin for Programming/Debugging
Communication Channel 1.
PGEC1 15 24 K1 I ST Clock input pin for Programming/Debugging
PGED2 18 27 J3 I/O ST Data I/O pin for Programming/Debugging
PGEC2 17 26 L1 I ST Clock input pin for Programming/Debugging
MCLR 7 13 F1 I/P ST Master Clear (Reset) input. This pin is an
active-low Reset to the device.
AVDD 19 30 J4 P P Positive supply for analog modules. This pin
must be connected at all times.
AVSS 20 31 L3 P P Ground reference for analog modules.
VDD 10, 26, 38, 2, 16, 37, A7, C2, P — Positive supply for peripheral logic and I/O
57 46, 62, 86 C9, E5, pins.
K8, F8,
G5, H4, H6
VCAP/ 56 85 B7 P — CPU logic filter capacitor connection.
VDDCORE
VSS 9, 25, 41 15, 36, 45, A8, B10, P — Ground reference for logic and I/O pins. This
65, 75 D4, D5, pin must be connected at all times.
E7, F5,
F10, G6,
G7, H3
VREF+ 16 29 K3 I Analog Analog voltage reference (high) input.
VREF- 15 28 L2 I Analog Analog voltage reference (low) input.

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors
STARTED WITH 32-BIT The use of decoupling capacitors on power supply
MICROCONTROLLERS pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Note 1: This data sheet summarizes the features
Consider the following criteria when using decoupling
of the PIC32MX5XX/6XX/7XX family of
capacitors:
devices. It is not intended to be a
comprehensive reference source. To • Value and type of capacitor: A value of 0.1 µF
complement the information in this data (100 nF), 10-20V is recommended. The capacitor
sheet, refer to the related section of the should be a low Equivalent Series Resistance
“PIC32MX Family Reference Manual”, (low-ESR) capacitor and have resonance fre-
which is available from the Microchip web quency in the range of 20 MHz and higher. It is
site (www.microchip.com/PIC32) further recommended that ceramic capacitors be
used.
described in this section may not be avail- • Placement on the printed circuit board: The
able on all devices. Refer to Section 4.0 decoupling capacitors should be placed as close
“Memory Organization” in this data to the pins as possible. It is recommended that
sheet for device-specific register and bit the capacitors be placed on the same side of the
information. board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
2.1 Basic Connection Requirements
length from the pin to the capacitor is within one-
Getting started with the PIC32MX5XX/6XX/7XX family quarter inch (6 mm) in length.
of 32-bit Microcontrollers (MCU) requires attention to a • Handling high frequency noise: If the board is
minimal set of device pin connections before proceed- experiencing high frequency noise, upward of
ing with development. The following is a list of pin tens of MHz, add a second ceramic-type capacitor
names, which must always be connected: in parallel to the above described decoupling
• All VDD and VSS pins capacitor. The value of the second capacitor can
(see Section 2.2 “Decoupling Capacitors”) be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
• All AVDD and AVSS pins–even if the ADC module capacitor. In high-speed circuit designs, consider
is not used implementing a decade pair of capacitances as
(see Section 2.2 “Decoupling Capacitors”) close to the power and ground pins as possible.
• VCAP/VDDCORE pin For example, 0.1 µF in parallel with 0.001 µF.
(see Section 2.3 “Capacitor on Internal • Maximizing performance: On the board layout
Voltage Regulator (VCAP/VDDCORE)”) from the power supply circuit, run the power and
• MCLR pin return traces to the decoupling capacitors first,
(see Section 2.4 “Master Clear (MCLR) Pin”) and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
• PGECx/PGEDx pins–used for In-Circuit Serial
Equally important is to keep the trace length
Programming (ICSP™) and debugging purposes
between the capacitor and the power pins to a
(see Section 2.5 “ICSP Pins”)
minimum thereby reducing PCB track inductance.
• OSC1 and OSC2 pins–when external oscillator
source is used
(see Section 2.8 “External Oscillator Pins”)
The following pin may be required, as well:
VREF+/VREF- pins–used when external voltage refer-
ence for ADC module is implemented
Note: The AVDD and AVSS pins must be
connected, regardless of ADC use and the
ADC voltage reference source.

PIC32MX5XX/6XX/7XX
FIGURE 2-1: RECOMMENDED 2.4 Master Clear (MCLR) Pin
MINIMUM CONNECTION
The MCLR pin provides for two specific device
functions:
0.1 µF
CEFC Ceramic
• Device Reset
VDD
CBP • Device programming and debugging
Pulling The MCLR pin low generates a device Reset.
VCAP/VDDCORE
VSS
VDD
R
R1
Figure 2-2 shows a typical MCLR circuit. During
MCLR device programming and debugging, the resistance
and capacitance that can be added to the pin must
C be considered. Device programmers and debuggers
PIC32MX drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
VSS VDD
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
VDD VSS
0.1 µF 0.1 µF application and PCB requirements.
AVDD
AVSS
VDD
VSS
Ceramic Ceramic
CBP CBP
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
0.1 µF 0.1 µF
Ceramic Ceramic the MCLR pin during programming and debugging
10 
CBP CBP operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
2.2.1 BULK CAPACITORS
The use of a bulk capacitor is recommended to improve FIGURE 2-2: EXAMPLE OF MCLR PIN
power supply stability. Typical values range from 4.7 µF
CONNECTIONS
to 47 µF. This capacitor should be located as close to
the device as possible.
VDD
2.3 Capacitor on Internal Voltage

R
Regulator (VCAP/VDDCORE) R1
MCLR
2.3.1 INTERNAL REGULATOR MODE
JP PIC32MX
A low-ESR (1 ohm) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the inter- C
nal voltage regulator output. The VCAP/VDDCORE pin
must not be connected to VDD, and must have a CEFC
capacitor, with at least a 6V rating, connected to Note 1: R  10 k is recommended. A suggested
ground. The type can be ceramic or tantalum. Refer to starting value is 10 k. Ensure that the MCLR
Section 31.0 "Electrical Characteristics" for pin VIH and VIL specifications are met.
additional information on CEFC specifications. 2: R1  470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
3: The capacitor can be sized to prevent uninten-
tional Resets from brief glitches or to extend
the device Reset period during POR.

PIC32MX5XX/6XX/7XX
2.5 ICSP Pins 2.6 JTAG
The PGECx and PGEDx pins are used for In-Circuit The TMS, TDO, TDI and TCK pins are used for testing
Serial Programming™ (ICSP™) and debugging pur- and debugging according to the Joint Test Action
poses. It is recommended to keep the trace length Group (JTAG) standard. It is recommended to keep the
between the ICSP connector and the ICSP pins on the trace length between the JTAG connector and the
device as short as possible. If the ICSP connector is JTAG pins on the device as short as possible. If the
expected to experience an ESD event, a series resistor JTAG connector is expected to experience an ESD
is recommended, with the value in the range of a few event, a series resistor is recommended, with the value
tens of Ohms, not to exceed 100 Ohms. in the range of a few tens of Ohms, not to exceed 100
Pull-up resistors, series diodes and capacitors on the Ohms.
PGECx and PGEDx pins are not recommended as they Pull-up resistors, series diodes and capacitors on the
will interfere with the programmer/debugger communi- TMS, TDO, TDI and TCK pins are not recommended
cations to the device. If such discrete components are as they will interfere with the programmer/debugger
an application requirement, they should be removed communications to the device. If such discrete compo-
from the circuit during programming and debugging. nents are an application requirement, they should be
Alternatively, refer to the AC/DC characteristics and removed from the circuit during programming and
timing requirements information in the respective debugging. Alternatively, refer to the AC/DC character-
device Flash programming specification for information istics and timing requirements information in the
on capacitive loading limits and pin input voltage high respective device Flash programming specification for
(VIH) and input low (VIL) requirements. information on capacitive loading limits and pin input
Ensure that the “Communication Channel Select” (i.e., voltage high (VIH) and input low (VIL) requirements.
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to 2.7 Trace
MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL
The trace pins can be connected to a hardware-trace-
ICE™.
enabled programmer to provide a compress real time
For more information on ICD 2, ICD 3 and REAL ICE instruction trace. When used for trace the TRD3,
connection requirements, refer to the following TRD2, TRD1, TRD0 and TRCLK pins should be dedi-
documents that are available on the Microchip web cated for this use. The trace hardware requires a
site. 22 ohm series resistor between the trace pins and the
• “MPLAB® ICD 2 In-Circuit Debugger User's trace connector.
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Debugger
User's Guide” DS51616
• “Using MPLAB® REAL ICE™ Emulator” (poster)
DS51749

PIC32MX5XX/6XX/7XX
2.8 External Oscillator Pins 2.9 Configuration of Analog and
Many MCUs have options for at least two oscillators: a
Digital Pins During ICSP
high-frequency primary oscillator and a low-frequency Operations
secondary oscillator (refer to Section 8.0 "Oscillator If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a
Configuration" for details). debugger, it automatically initializes all of the A/D input
The oscillator circuit should be placed on the same side pins (ANx) as “digital” pins by setting all bits in the
of the board as the device. Also, place the oscillator cir- ADPCFG register.
cuit close to the respective oscillator pins, not exceed- The bits in this register that correspond to the A/D pins
ing one-half inch (12 mm) distance between them. The that are initialized by MPLAB ICD 2, ICD 3, or REAL
load capacitors should be placed next to the oscillator ICE, must not be cleared by the user application
itself, on the same side of the board. Use a grounded firmware; otherwise, communication errors will result
copper pour around the oscillator circuit to isolate them between the debugger and the device.
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not If your application needs to use certain A/D pins as
run any signal traces or power traces inside the ground analog input pins during the debug session, the user
pour. Also, if using a two-sided board, avoid any traces application must clear the corresponding bits in the
on the other side of the board where the crystal is ADPCFG register during initialization of the ADC
placed. A suggested layout is shown in Figure 2-3. module.
When MPLAB ICD 2, ICD 3, or REAL ICE is used as a
FIGURE 2-3: SUGGESTED OSCILLATOR programmer, the user application firmware must cor-
CIRCUIT PLACEMENT rectly configure the ADPCFG register. Automatic initial-
ization of this register is only done during debugger
operation. Failure to correctly configure the register(s)
will result in all A/D pins being recognized as analog
input pins, resulting in the port value being read as a
logic '0', which may affect user application functionality.
Oscillator
Secondary
2.10 Unused I/Os
Guard Trace
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
Guard Ring
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
Main Oscillator
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.

PIC32MX5XX/6XX/7XX
3.0 PIC32MX MCU - Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
Note 1: This data sheet summarizes the features for interrupt handlers
of the PIC32MX5XX/6XX/7XX family of - Bit field manipulation instructions
• MIPS16e™ Code Compression
complement the information in this data - 16-bit encoding of 32-bit instructions to
sheet, refer to Section 2. “MCU” improve code density
(DS61113) in the “PIC32MX Family - Special PC-relative instructions for efficient
Reference Manual”, which is available loading of addresses and constants
from the Microchip web site - SAVE & RESTORE macro instructions for
(www.microchip.com/PIC32). Resources setting up and tearing down stack frames
for the MIPS32® M4K® Processor Core within subroutines
are available at http://www.mips.com. - Improved support for handling 8 and 16-bit
2: Some registers and associated bits data types
described in this section may not be avail- • Simple Fixed Mapping Translation (FMT)
able on all devices. Refer to Section 4.0 mechanism
“Memory Organization” in this data • Simple Dual Bus Interface
sheet for device-specific register and bit - Independent 32-bit address and data busses
information.
- Transactions can be aborted to improve
The MCU module is the heart of the interrupt latency
PIC32MX5XX/6XX/7XX family processor. The MCU • Autonomous Multiply/Divide Unit
fetches instructions, decodes each instruction, fetches - Maximum issue rate of one 32x16 multiply
source operands, executes each instruction and writes per clock
the results of instruction execution to the proper
destinations. - Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
3.1 Features maximum 33 clock latency (dividend (rs) sign
• 5-Stage Pipeline extension-dependent)
• 32-Bit Address and Data Paths • Power Control
• MIPS32 Enhanced Architecture (Release 2) - Minimum frequency: 0 MHz
- Multiply-Accumulate and Multiply-Subtract - Low-Power mode (triggered by WAIT
instructions instruction)
- Targeted Multiply instruction - Extensive use of local gated clocks
- Zero/One Detect instructions • EJTAG Debug and Instruction Trace
- WAIT instruction - Support for single stepping
- Conditional Move instructions (MOVN, MOVZ) - Virtual instruction and data address/value
- Vectored interrupts - Breakpoints
- Programmable exception vector base - PC tracing with trace compression
FIGURE 3-1: MCU BLOCK DIAGRAM
MCU
EJTAG Trace I/F
MDU
Trace
Off-Chip
TAP
Debug I/F
Execution
Bus Matrix
Core FMT Bus Interface Dual Bus I/F

(RF/ALU/Shift)
System Power
Coprocessor Management

PIC32MX5XX/6XX/7XX
3.2 Architecture Overview 3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
The PIC32MX5XX/6XX/7XX family core contains sev- The PIC32MX5XX/6XX/7XX family core includes a
eral logic blocks working together in parallel, providing Multiply/Divide Unit (MDU) that contains a separate
an efficient high-performance computing engine. The pipeline for multiply and divide operations. This pipeline
following blocks are included with the core: operates in parallel with the Integer Unit (IU) pipeline
and does not stall when the IU pipeline stalls. This
• Execution Unit allows MDU operations to be partially masked by
• Multiply/Divide Unit (MDU) system stalls and/or other integer unit instructions.
• System Control Coprocessor (CP0) The high-performance MDU consists of a 32x16 booth
• Fixed Mapping Translation (FMT) recoded multiplier, result/accumulation registers (HI
• Dual Internal Bus interfaces and LO), a divide state machine, and the necessary
• Power Management multiplexers and control logic. The first number shown
• MIPS16e Support (‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
• Enhanced JTAG (EJTAG) Controller
PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
3.2.1 EXECUTION UNIT
must pass through the multiplier. The 16x16 and 32x16
The PIC32MX5XX/6XX/7XX family core execution unit operations pass through the multiplier once. A 32x32
implements a load/store architecture with single-cycle operation passes through the multiplier twice.
ALU operations (logical, shift, add, subtract) and an
The MDU supports execution of one 16x16 or 32x16
autonomous multiply/divide unit. The core contains
multiply operation every clock cycle; 32x32 multiply
thirty-two 32-bit General Purpose Registers (GPRs)
operations can be issued every other clock cycle.
used for integer operations and address calculation.
Appropriate interlocks are implemented to stall the
One additional register file shadow set (containing
issuance of back-to-back 32x32 multiply operations.
thirty-two registers) is added to minimize context
The multiply operand size is automatically determined
switching overhead during interrupt/exception process-
by logic built into the MDU.
ing. The register file consists of two read ports and one
write port and is fully bypassed to minimize operation Divide operations are implemented with a simple 1 bit
latency in the pipeline. per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
The execution unit includes:
If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit
• 32-bit adder used for calculating the data address wide rs, 15 iterations are skipped and for a 24-bit wide
• Address unit for calculating the next instruction rs, 7 iterations are skipped. Any attempt to issue a sub-
address sequent MDU instruction while a divide is still active
• Logic for branch determination and branch target causes an IU pipeline stall until the divide operation is
address calculation completed.
• Load aligner Table 3-1 lists the repeat rate (peak issue rate of cycles
• Bypass multiplexers used to avoid stalls when until the operation can be reissued) and latency (num-
executing instruction streams where data ber of cycles until a result is available) for the PIC32MX
producing instructions are followed closely by core multiply and divide instructions. The approximate
consumers of their results latency and repeat rates are listed in terms of pipeline
• Leading Zero/One detect unit for implementing clocks.
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations
• Shifter and store aligner

PIC32MX5XX/6XX/7XX
TABLE 3-1: PIC32MX5XX/6XX/7XX FAMILY CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate
MULT/MULTU, MADD/MADDU, 16 bits 1 1
MSUB/MSUBU 32 bits 2 2
MUL 16 bits 2 1
32 bits 3 2
DIV/DIVU 8 bits 12 11
16 bits 19 18
24 bits 26 25
32 bits 33 32
The MIPS architecture defines that the result of a 3.2.3 SYSTEM CONTROL
multiply or divide operation be placed in the HI and LO COPROCESSOR (CP0)
registers. Using the Move-From-HI (MFHI) and Move-
In the MIPS architecture, CP0 is responsible for the
From-LO (MFLO) instructions, these values can be
virtual-to-physical address translation, the exception
transferred to the General Purpose Register file.
control system, the processor’s diagnostics capability,
In addition to the HI/LO targeted operations, the the operating modes (Kernel, User and Debug) and
MIPS32 architecture also defines a multiply instruction, whether interrupts are enabled or disabled. Configura-
MUL, which places the least significant results in the pri- tion information, such as presence of options like
mary register file instead of the HI/LO register pair. By MIPS16e, is also available by accessing the CP0
avoiding the explicit MFLO instruction required when registers, listed in Table 3-2.
using the LO register, and by supporting multiple desti-
nation registers, the throughput of multiply-intensive
operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.

PIC32MX5XX/6XX/7XX
TABLE 3-2: COPROCESSOR 0 REGISTERS
Register Register
Function
Number Name
0-6 Reserved Reserved in the PIC32MX5XX/6XX/7XX family core.
7 HWREna Enables access via the RDHWR instruction to selected hardware registers.
8 BadVAddr(1) Reports the address for the most recent address-related exception.
9 Count(1) Processor cycle count.
10 Reserved Reserved in the PIC32MX5XX/6XX/7XX family core.
(1)
11 Compare Timer interrupt control.
12 Status(1) Processor status and control.
(1)
12 IntCtl Interrupt system status and control.
12 SRSCtl(1) Shadow register set status and control.
12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set.
13 Cause(1) Cause of last general exception.
(1)
14 EPC Program counter at last exception.
15 PRId Processor identification and revision.
15 EBASE Exception vector base register.
16 Config Configuration register.
16 Config1 Configuration Register 1.
(2)
23 Debug Debug control and exception status.
24 DEPC(2) Program counter at last debug exception.
30 ErrorEPC(1) Program counter at last error.
(2)
31 DESAVE Debug handler scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used during debug.

PIC32MX5XX/6XX/7XX
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES

Exception Description
Reset Assertion MCLR or a Power-on Reset (POR).

DSS EJTAG debug single step.
DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI Assertion of NMI signal.
Interrupt Assertion of unmasked hardware or software interrupt signal.
DIB EJTAG debug hardware instruction break matched.
AdEL Fetch address alignment error.
Fetch reference to protected address.
IBE Instruction fetch bus error.
DBp EJTAG breakpoint (execution of SDBBP instruction).
Sys Execution of SYSCALL instruction.
Bp Execution of BREAK instruction.
RI Execution of a reserved instruction.
CpU Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU Execution of a CorExtend instruction when CorExtend is not enabled.
Ov Execution of an arithmetic instruction that overflowed.
Tr Execution of a trap (when trap condition is true).
DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
AdEL Load address alignment error.
Load reference to protected address.
AdES Store address alignment error.
Store to protected address.
DBE Load or store bus error.
DDBL EJTAG data hardware breakpoint matched in load data compare.

PIC32MX5XX/6XX/7XX
3.3 Power Management 3.4 EJTAG Debug Support
The PIC32MX5XX/6XX/7XX family core offers a number The PIC32MX5XX/6XX/7XX family core provides for
of power management features, including low-power an Enhanced JTAG (EJTAG) interface for use in the
design, active power management and power-down software debug of application and kernel code. In
modes of operation. The core is a static design that addition to standard User mode and Kernel modes of
supports slowing or Halting the clocks, which reduces operation, the PIC32MX5XX/6XX/7XX family core pro-
system power consumption during Idle periods. vides a Debug mode that is entered after a debug
exception (derived from a hardware breakpoint, single-
3.3.1 INSTRUCTION-CONTROLLED step exception, etc.) is taken and continues until a
POWER MANAGEMENT Debug Exception Return (DERET) instruction is
The mechanism for invoking Power-Down mode is executed. During this time, the processor executes the
through execution of the WAIT instruction. For more debug exception handler routine.
information on power management, see Section 27.0 The EJTAG interface operates through the Test Access
“Power-Saving Features”. Port (TAP), a serial communication port used for trans-
ferring test data in and out of the
3.3.2 LOCAL CLOCK GATING PIC32MX5XX/6XX/7XX family core. In addition to the
The majority of the power consumed by the standard JTAG instructions, special instructions
PIC32MX5XX/6XX/7XX family core is in the clock tree defined in the EJTAG specification define which
and clocking registers. The PIC32MX family uses registers are selected and how they are used.
extensive use of local gated clocks to reduce this
dynamic power consumption.

PIC32MX5XX/6XX/7XX
4.0 MEMORY ORGANIZATION 4.1 PIC32MX5XX/6XX/7XX Memory
Layout
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of PIC32MX5XX/6XX/7XX microcontrollers implement
devices. It is not intended to be a compre- two address schemes: virtual and physical. All
hensive reference source. For detailed hardware resources, such as program memory, data
information, refer to Section 3. “Memory memory and peripherals, are located at their respective
Organization” (DS61115) in the physical addresses. Virtual addresses are exclusively
“PIC32MX Family Reference Manual”, used by the CPU to fetch and execute instructions as
which is available from the Microchip web well as access peripherals. Physical addresses are
site (www.microchip.com/PIC32). used by bus master peripherals, such as DMA and the
Flash controller, that access memory independently of
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB the CPU.
of unified virtual memory address space. All memory
The memory maps for the PIC32MX5XX/6XX/7XX
regions, including program, data memory, SFRs and
devices are shown in Figure 4-1, Figure 4-2 and
Configuration registers, reside in this address space at
Figure 4-3.
their respective unique addresses. The program and
data memories can be optionally partitioned into user
4.1.1 PERIPHERAL REGISTERS
and kernel memories. In addition, the data memory can
LOCATIONS
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory. Table 4-1 through Table 4-44 contain the peripheral
address maps for the PIC32MX5XX/6XX/7XX
Key features include:
devices. Peripherals located on the PB bus are
• 32-bit native data width mapped to 512-byte boundaries. Peripherals on the
• Separate User (KUSEG) and Kernel FPB bus are mapped to 4-Kbyte boundaries.
(KSEG0/KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions

PIC32MX5XX/6XX/7XX
FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L,
PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND
PIC32MX775F256L DEVICES(1)
Virtual Physical
Memory Map Memory Map
0xFFFFFFFF 0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FF0 Registers
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1
0xBF800000
Reserved
0xBD040000
0xBD03FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0010000
0xA000FFFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
0x9FC02FF0 Configuration
0x9FC02FFF Device Registers 0x1FC02FF0
Configuration 0x1FC02FEF
0x9FC02FEF Registers Boot Flash
0x9FC02FEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0
0x9D040000 0x1F800000
0x9D03FFFF
Program Flash(2) Reserved
0x9D000000 0x1D040000
0x1D03FFFF
Reserved
0x80008000 Program Flash(2)
0x80007FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00010000
0x0000FFFF
Reserved RAM(2)
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).

PIC32MX5XX/6XX/7XX
PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND
PIC32MX775F512L DEVICES
Virtual Physical
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
0xBF800000 KSEG1
Reserved
0xBD080000
0xBD07FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0010000
0xA000FFFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0
0x9D080000 0x1F800000
0x9D07FFFF
0x9D000000 0x1D080000
0x1D07FFFF
Reserved
0x8000FFFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00010000
(2) 0x0000FFFF
Reserved RAM
0x00000000 0x00000000


PIC32MX5XX/6XX/7XX
PIC32MX795F512H AND PIC32MX795F512L DEVICES
Virtual Physical
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1
0xBF800000
Reserved
0xBD080000
0xBD07FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0020000
0xA001FFFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0
0x9D080000 0x1F800000
0x9D07FFFF
0x9D000000 0x1D080000
0x1D07FFFF
Reserved
0x8001FFFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00020000
0x0001FFFF
Reserved RAM(2)
0x00000000 0x00000000


TABLE 4-1: BUS MATRIX REGISTER MAP

Virtual Address
Bits
Bit Range
(BF88_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — BMXCHEDMA — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

2000 BMXCON(1)
15:0 — — — — — — — — — BMXWSDRM — — — BMXARB<2:0> 0040
31:16 — — — — — — — — — — — — — — — — 0000
2010 BMXDKPBA(1)
15:0 BMXDKPBA<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
2020 BMXDUDBA(1)
15:0 BMXDUDBA<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
2030 BMXDUPBA(1)
15:0 BMXDUPBA<15:0> 0000
31:16 xxxx
2040 BMXDRMSZ BMXDRMSZ<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000
2050 BMXPUPBA(1)
Preliminary
15:0 BMXPUPBA<15:0> 0000

31:16 xxxx
2060 BMXPFMSZ BMXPFMSZ<31:0>
15:0 xxxx
PIC32MX5XX/6XX/7XX
31:16 0000
2070 BMXBOOTSZ BMXBOOTSZ<31:0>
15:0 3000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DS61156C-page 49
INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1)
DS61156C-page 50
PIC32MX5XX/6XX/7XX
TABLE 4-2:
Virtual Address
Bits
Bit Range
(BF88_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
15:0 — FRZ — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — RIPL<2:0> — — VEC<5:0> 0000
31:16 0000
1020 IPTMR IPTMR<31:0>
15:0 0000
U1ATXIF U1ARXIF U1AEIF
31:16 I2C1MIF I2CSIF I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF — — — OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000
1030 IFS0
I2C1AMIF I2C1ASIF I2C1ABIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 IC3EIF IC2EIF IC1EIF — — CAN1IF USBIF FCEIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF 0000
Preliminary
U3ATXIF U3ARXIF U3AEIF U2ATXIF U2ARXIF U2AEIF

1040 IFS1
15:0 RTCCIF FSCMIF — — — SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000
I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF I2C2ASIF I2C2ABIF
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
15:0 — — — — U3BTXIF U3BRXIF U3BEIF U2BTXIF U2BRXIF U2BEIF U1BTXIF U1BRXIF U1BEIF PMPEIF IC5EIF IC4EIF 0000
U1ATXIE U1ARXIE U1AEIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE — — — OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
I2C1AMIE I2C1ASIE I2C1ABIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 IC3EIE IC2EIE IC1EIE — — CAN1IE USBIE FCEIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE 0000
U3ATXIE U3ARXIE U3AEIE U2ATXIE U2ARXIE U2AEIE
1070 IEC1
15:0 RTCCIE FSCMIE — — — SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE

31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
15:0 — — — — U3BTXIE U3BRXIE U3BEIE U2BTXIE U2BRXIE U2BEIE U1BTXIE U1BRXIE U1BEIE PMPEIE IC5EIE IC4EIE 0000
31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
1090 IPC0
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
TABLE 4-2: INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) (CONTINUED)
Virtual Address
Bits
Bit Range
(BF88_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
U1AIP<2:0> U1AIS<1:0>
10F0 IPC6
15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — SPI1AIP<2:0> SPI1AIS<1:0> 0000
Preliminary
I2C1AIP<2:0> I2C1AIS<1:0>
U2AIP<2:0> U2AIS<1:0>
31:16 — — — SPI2AIP<2:0> SPI2AIS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000
1100 IPC7
PIC32MX5XX/6XX/7XX
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
U3AIP<2:0> U3AIS<1:0>
1110 IPC8
15:0 — — — — — — — — — — — SPI3AIP<2:0> SPI3AIS<1:0> 0000
31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
1120 IPC9
1130 IPC10
31:16 — — — — — — — — — — — CAN1IP<2:0> CAN1IS<1:0> 0000
1140 IPC11
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
31:16 — — — U3BIP<2:0> U3BIS<1:0> — — — U2BIP<2:0> U2BIS<1:0> 0000
1150 IPC12
15:0 — — — U1BIP<2:0> U1BIS<1:0> — — — — — — — — 0000
DS61156C-page 51
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
DS61156C-page 52
PIC32MX5XX/6XX/7XX
TABLE 4-3: INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES(1)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — RIPL<2:0> — — VEC<5:0> 0000
31:16 0000
15:0 0000
1030 IFS0
31:16 IC3EIF IC2EIF IC1EIF ETHIF — — USBIF FCEIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF 0000
1040 IFS1
Preliminary
31:16 — — — — — — — — — — — — — — 0000
1050 IFS2
1060 IEC0
31:16 IC3EIE IC2EIE IC1EIE ETHIE — — USBIE FCEIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE 0000
1070 IEC1
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
1090 IPC0
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-3: INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES(1) (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
U1AIP<2:0> U1AIS<1:0>
10F0 IPC6
U2AIP<2:0> U2AIS<1:0>
1100 IPC7
Preliminary

U3AIP<2:0> U3AIS<1:0>
1110 IPC8
15:0 — — — — — — — — — — — SPI3AIP<2:0> SPI3AIS<1:0> 0000
PIC32MX5XX/6XX/7XX
1120 IPC9
1130 IPC10
31:16 — — — — — — — — — — — — — — — — 0000
1140 IPC11
1150 IPC12
15:0 — — — U1BIP<2:0> U1BIS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DS61156C-page 53
DS61156C-page 54
PIC32MX5XX/6XX/7XX
TABLE 4-4: INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES(1)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — RIPL<2:0> — — VEC<5:0> 0000
31:16 0000
15:0 0000
1030 IFS0
31:16 IC3EIF IC2EIF IC1EIF ETHIF CAN2IF CAN1IF USBIF FCEIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF 0000
1040 IFS1
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
1060 IEC0
31:16 IC3EIE IC2EIE IC1EIE ETHIE CAN2IE CAN1IE USBIE FCEIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE 0000
1070 IEC1
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
1090 IPC0
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-4: INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES(1) (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
U1AIP<2:0> U1AIS<1:0>
10F0 IPC6
U2AIP<2:0> U2AIS<1:0>
1100 IPC7
Preliminary

U3AIP<2:0> U3AIS<1:0>
1110 IPC8
15:0 — — — — — — — — — — — SPI3AIP<2:0> SPI3AIS<1:0> 0000
PIC32MX5XX/6XX/7XX
1120 IPC9
1130 IPC10
31:16 — — — CAN2IP<2:0> CAN2IS<1:0> — — — CAN1IP<2:0> CAN1IS<1:0> 0000
1140 IPC11
1150 IPC12
information.
DS61156C-page 55
INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1)
DS61156C-page 56
PIC32MX5XX/6XX/7XX
TABLE 4-5:
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — RIPL<2:0> — — VEC<5:0> 0000
31:16 0000
15:0 0000
31:16 I2C1MIF I2CSIF I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF SPI1TXIF SPI1RXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000
1030 IFS0
31:16 IC3EIF IC2EIF IC1EIF — — CAN1IF USBIF FCEIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF 0000
1040 IFS1
15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000
Preliminary

31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
31:16 I2C1MIE I2C1SIE I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE SPI1TXIE SPI1RXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
31:16 IC3EIE IC2EIE IC1EIE — — CAN1IE USBIE FCEIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE 0000
1070 IEC1
15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
1090 IPC0

10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
information.
TABLE 4-5: INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000

10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
U1AIP<2:0> U1AIS<1:0>
10F0 IPC6
U2AIP<2:0> U2AIS<1:0>
1100 IPC7
U3AIP<2:0> U3AIS<1:0>
1110 IPC8
Preliminary

1120 IPC9
1130 IPC10
PIC32MX5XX/6XX/7XX
31:16 — — — — — — — — — — — CAN1IP<2:0> CAN1IS<1:0> 0000
1140 IPC11
1150 IPC12
15:0 — — — U1BIP<2:0> U1BIS<1:0> — — — — — — — — 0000
information.
DS61156C-page 57
DS61156C-page 58
PIC32MX5XX/6XX/7XX
TABLE 4-6: INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — RIPL<2:0> — — VEC<5:0> 0000
31:16 0000
15:0 0000
1030 IFS0
31:16 IC3EIF IC2EIF IC1EIF ETHIF — — USBIF FCEIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF 0000
1040 IFS1
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
1060 IEC0
31:16 IC3EIE IC2EIE IC1EIE ETHIE — — USBIE FCEIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE 0000
1070 IEC1
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
1090 IPC0
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
information.
PIC32MX695F512L DEVICES(1) (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
U1AIP<2:0> U1AIS<1:0>
10F0 IPC6
U2AIP<2:0> U2AIS<1:0>
1100 IPC7
Preliminary

U3AIP<2:0> U3AIS<1:0>
1110 IPC8
PIC32MX5XX/6XX/7XX
1120 IPC9
1130 IPC10
31:16 — — — — — — — — — — — — — — — — 0000
1140 IPC11
1150 IPC12
information.
DS61156C-page 59
DS61156C-page 60
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — RIPL<2:0> — — VEC<5:0> 0000
31:16 0000
15:0 0000
1030 IFS0
31:16 IC3EIF IC2EIF IC1EIF ETHIF CAN2IF CAN1IF USBIF FCEIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF 0000
1040 IFS1
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
1060 IEC0
31:16 IC3EIE IC2EIE IC1EIE ETHIE CAN2IE CAN1IE USBIE FCEIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE 0000
1070 IEC1
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
1090 IPC0
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
information.
PIC32MX795F512L DEVICES(1) (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
U1AIP<2:0> U1AIS<1:0>
10F0 IPC6
U2AIP<2:0> U2AIS<1:0>
1100 IPC7
Preliminary

U3AIP<2:0> U3AIS<1:0>
1110 IPC8
PIC32MX5XX/6XX/7XX
1120 IPC9
1130 IPC10
31:16 — — — CAN2IP<2:0> CAN2IS<1:0> — — — CAN1IP<2:0> CAN1IS<1:0> 0000
1140 IPC11
1150 IPC12
information.
DS61156C-page 61
TIMER1-TIMER5 REGISTER MAP(1)
DS61156C-page 62
PIC32MX5XX/6XX/7XX
TABLE 4-8:
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
0600 T1CON
15:0 ON FRZ SIDL TWDIS TWIP — — — TGATE — TCKPS<1:0> — TSYNC TCS — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0610 TMR1
15:0 TMR1<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0620 PR1
15:0 PR1<15:0> FFFF
31:16 — — — — — — — — — — — — — — — — 0000
0800 T2CON
15:0 ON FRZ SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0810 TMR2
15:0 TMR2<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0820 PR2
15:0 PR2<15:0> FFFF
31:16 — — — — — — — — — — — — — — — — 0000
0A00 T3CON
Preliminary
15:0 ON FRZ SIDL — — — — — TGATE TCKPS<2:0> — — TCS — 0000

31:16 — — — — — — — — — — — — — — — — 0000
0A10 TMR3
15:0 TMR3<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0A20 PR3
15:0 PR3<15:0> FFFF
31:16 — — — — — — — — — — — — — — — — 0000
0C00 T4CON
15:0 ON FRZ SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0C10 TMR4
15:0 TMR4<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0C20 PR4
15:0 PR4<15:0> FFFF
31:16 — — — — — — — — — — — — — — — — 0000
0E00 T5CON
15:0 ON FRZ SIDL — — — — — TGATE TCKPS<2:0> — — TCS — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0E10 TMR5
15:0 TMR5<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0E20 PR5
15:0 PR5<15:0> FFFF
information.
TABLE 4-9: INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP

Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
2000 IC1CON(1)
15:0 ON FRZ SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2010 IC1BUF IC1BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2200 IC2CON(1)
31:16 xxxx
15:0 xxxx
(1) 31:16 — — — — — — — — — — — — — — — — 0000
2400 IC3CON
31:16 xxxx
15:0 xxxx
(1) 31:16 — — — — — — — — — — — — — — — — 0000
2600 IC4CON
Preliminary
31:16 xxxx
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
PIC32MX5XX/6XX/7XX
2800 IC5CON(1)
31:16 xxxx
15:0 xxxx
DS61156C-page 63
OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1)
DS61156C-page 64
PIC32MX5XX/6XX/7XX
TABLE 4-10:
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3000 OC1CON
15:0 ON FRZ SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3010 OC1R OC1R<31:0>
15:0 xxxx
31:16 xxxx
3020 OC1RS OC1RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3200 OC2CON
31:16 xxxx
3210 OC2R OC2R<31:0>
15:0 xxxx
31:16 xxxx
3220 OC2RS OC2RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3400 OC3CON
Preliminary

31:16 xxxx
3410 OC3R OC3R<31:0>
15:0 xxxx
31:16 xxxx
3420 OC3RS OC3RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3600 OC4CON
31:16 xxxx
3610 OC4R OC4R<31:0>
15:0 xxxx
31:16 xxxx
3620 OC4RS OC4RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3800 OC5CON
31:16 xxxx
3810 OC5R OC5R<31:0>
15:0 xxxx
31:16 xxxx
3820 OC5RS OC5RS<31:0>
15:0 xxxx
information.
I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1)
TABLE 4-11:
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
5000 I2C1ACON
15:0 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0000
31:16 — — — — — — — — — — — — — — — — 0000
5010 I2C1ASTAT
15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5020 I2C1AADD
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5030 I2C1AMSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5040 I2C1ABRG
15:0 — — — — I2C1BRG<11:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5050 I2C1ATRN
15:0 — — — — — — — — I2CT1DATA<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5060 I2C1ARCV
Preliminary
15:0 — — — — — — — — I2CR1DATA<7:0> 0000

31:16 — — — — — — — — — — — — — — — — 0000
5100 I2C2ACON
31:16 — — — — — — — — — — — — — — — — 0000
PIC32MX5XX/6XX/7XX
5110 I2C2ASTAT
31:16 — — — — — — — — — — — — — — — — 0000
5120 I2C2AADD
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5130 I2C2AMSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5140 I2C2ABRG
15:0 — — — — I2C1BRG<11:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5150 I2C2ATRN
15:0 — — — — — — — — I2CT1DATA<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5160 I2C2ARCV
15:0 — — — — — — — — I2CR1DATA<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5200 I2C3ACON
31:16 — — — — — — — — — — — — — — — — 0000
5210 I2C3ASTAT
DS61156C-page 65
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-11: I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1) (CONTINUED)
DS61156C-page 66
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
5220 I2C3AADD
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5230 I2C3AMSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5240 I2C3ABRG
15:0 — — — — I2C1BRG<11:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5250 I2C3ATRN
15:0 — — — — — — — — I2CT1DATA<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5260 I2C3ARCV
15:0 — — — — — — — — I2CR1DATA<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5300 I2C1CON
31:16 — — — — — — — — — — — — — — — — 0000
5310 I2C1STAT
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
5320 I2C1ADD
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5330 I2C1MSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5340 I2C1BRG
15:0 — — — — I2C1BRG<11:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5350 I2C1TRN
15:0 — — — — — — — — I2CT1DATA<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5360 I2C1RCV
15:0 — — — — — — — — I2CR1DATA<7:0> 0000
TABLE 4-12: I2C2 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
5400 I2C2CON
31:16 — — — — — — — — — — — — — — — — 0000
5410 I2C2STAT
31:16 — — — — — — — — — — — — — — — — 0000
5420 I2C2ADD
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5430 I2C2MSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5440 I2C2BRG
15:0 — — — — I2C2BRG<11:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5450 I2C2TRN
15:0 — — — — — — — — I2CT1DATA<7:0> 0000
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
5460 I2C2RCV
15:0 — — — — — — — — I2CR1DATA<7:0> 0000
PIC32MX5XX/6XX/7XX
DS61156C-page 67
DS61156C-page 68
PIC32MX5XX/6XX/7XX
TABLE 4-13:
Virtual Address UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6000 U1AMODE(1)
15:0 ON FRZ SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
(1) 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6010 U1ASTA
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 — — — — — — — — — — — — — — — — 0000
6020 U1ATXREG
15:0 — — — — — — — TX8 Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6030 U1ARXREG
15:0 — — — — — — — RX8 Receive Register 0000
(1) 31:16 — — — — — — — — — — — — — — — — 0000
6040 U1ABRG
15:0 BRG<15:0> 0000
(1) 31:16 — — — — — — — — — — — — — — — — 0000
6200 U1BMODE
15:0 ON FRZ SIDL IREN — — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6210 U1BSTA(1)
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
6220 U1BTXREG
31:16 — — — — — — — — — — — — — — — — 0000
6230 U1BRXREG
31:16 — — — — — — — — — — — — — — — — 0000
6240 U1BBRG(1)
15:0 BRG<15:0> 0000
(1) 31:16 — — — — — — — — — — — — — — — — 0000
6400 U2AMODE
(1) 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6410 U2ASTA
31:16 — — — — — — — — — — — — — — — — 0000
6420 U2ATXREG
31:16 — — — — — — — — — — — — — — — — 0000
6430 U2ARXREG
(1) 31:16 — — — — — — — — — — — — — — — — 0000

6440 U2ABRG
15:0 BRG<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
6600 U2BMODE(1)
(1) 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6610 U2BSTA
31:16 — — — — — — — — — — — — — — — — 0000
6620 U2BTXREG
TABLE 4-13: UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6630 U2BRXREG
(1) 31:16 — — — — — — — — — — — — — — — — 0000
6640 U2BBRG
15:0 BRG<15:0> 0000
(1) 31:16 — — — — — — — — — — — — — — — — 0000
6800 U3AMODE
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6810 U3ASTA(1)
31:16 — — — — — — — — — — — — — — — — 0000
6820 U3ATXREG
31:16 — — — — — — — — — — — — — — — — 0000
6830 U3ARXREG
31:16 — — — — — — — — — — — — — — — — 0000
6840 U3ABRG(1)
15:0 BRG<15:0> 0000
Preliminary
(1) 31:16 — — — — — — — — — — — — — — — — 0000

6A00 U3BMODE
(1) 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6A10 U3BSTA
PIC32MX5XX/6XX/7XX
31:16 — — — — — — — — — — — — — — — — 0000
6A20 U3BTXREG
31:16 — — — — — — — — — — — — — — — — 0000
6A30 U3BRXREG
(1) 31:16 — — — — — — — — — — — — — — — — 0000
6A40 U3BBRG
15:0 BRG<15:0> 0000
DS61156C-page 69
SPI1A, SPI2A AND SPI3A REGISTER MAP(1)
DS61156C-page 70
PIC32MX5XX/6XX/7XX
TABLE 4-14:
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
5800 SPI1ACON
15:0 ON FRZ SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000
5810 SPI1ASTAT
15:0 — — — — SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0000
31:16 0000
5820 SPI1ABUF DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5830 SPI1ABRG
15:0 — — — — — — — BRG<8:0> 0000
5A00 SPI2ACON
5A10 SPI2ASTAT
31:16 0000
5A20 SPI2ABUF DATA<31:0>
Preliminary
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5A30 SPI2ABRG
15:0 — — — — — — — BRG<8:0> 0000
5C00 SPI3ACON
5C10 SPI3ASTAT
31:16 0000
5C20 SPI3ABUF DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5C30 SPI3ABRG
15:0 — — — — — — — BRG<8:0> 0000
Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
TABLE 4-15: SPI1 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L,
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
5E00 SPI1CON
5E10 SPI1STAT
31:16 0000
5E20 SPI1BUF DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5E30 SPI1BRG
15:0 — — — — — — — BRG<8:0> 0000
Preliminary
PIC32MX5XX/6XX/7XX
DS61156C-page 71
DS61156C-page 72
PIC32MX5XX/6XX/7XX
TABLE 4-16:
Virtual Address ADC REGISTER MAP
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
9000 AD1CON1(1)
15:0 ON FRZ SIDL — — FORM<2:0> SSRC<2:0> CLRASAM — ASAM SAMP DONE 0000
(1) 31:16 — — — — — — — — — — — — — — — — 0000
9010 AD1CON2
15:0 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — — BUFS — SMPI<3:0> BUFM ALTS 0000
(1) 31:16 — — — — — — — — — — — — — — — — 0000
9020 AD1CON3
15:0 ADRC — — SAMC<4:0> ADCS<7:0> 0000
31:16 CH0NB — — — CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000
9040 AD1CHS(1)
15:0 — — — — — — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
9060 AD1PCFG(1)
15:0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
(1) 31:16 — — — — — — — — — — — — — — — — 0000
9050 AD1CSSL
15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000
31:16 0000
9070 ADC1BUF0 ADC Result Word 0 (ADC1BUF0<31:0>)
Preliminary
15:0 0000
31:16 0000
15:0 0000
31:16 0000
15:0 0000
31:16 0000
90A0 ADC1BUF3 ADC Result Word 3 (ADC1BUF3<31:0>)
15:0 0000
31:16 0000
90B0 ADC1BUF4 ADC Result Word 4 (ADC1BUF4<31:0>)
15:0 0000
31:16 0000
90C0 ADC1BUF5 ADC Result Word 5 (ADC1BUF5<31:0>)
15:0 0000
31:16 0000
90D0 ADC1BUF6 ADC Result Word 6 (ADC1BUF6<31:0>)
15:0 0000
31:16 0000
90E0 ADC1BUF7 ADC Result Word 7 (ADC1BUF7<31:0>)
15:0 0000
31:16 0000
90F0 ADC1BUF8 ADC Result Word 8 (ADC1BUF8<31:0>)
15:0 0000
31:16 0000
15:0 0000
31:16 0000
9110 ADC1BUFA ADC Result Word A (ADC1BUFA<31:0>)
15:0 0000
31:16 0000
9120 ADC1BUFB ADC Result Word B (ADC1BUFB<31:0>)
15:0 0000
TABLE 4-16: ADC REGISTER MAP (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
9130 ADC1BUFC ADC Result Word C (ADC1BUFC<31:0>)
15:0 0000
31:16 0000
9140 ADC1BUFD ADC Result Word D (ADC1BUFD<31:0>)
15:0 0000
31:16 0000
9150 ADC1BUFE ADC Result Word E (ADC1BUFE<31:0>)
15:0 0000
31:16 0000
9160 ADC1BUFF ADC Result Word F (ADC1BUFF<31:0>)
15:0 0000
Preliminary
PIC32MX5XX/6XX/7XX
DS61156C-page 73
DS61156C-page 74
PIC32MX5XX/6XX/7XX
TABLE 4-17:
Virtual Address DMA GLOBAL REGISTER MAP
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3000 DMACON(1)
15:0 ON FRZ — SUSPEND BUSY — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
3010 DMASTAT
15:0 — — — — — — — — — — — — RDWR DMACH<2:0> 0000
31:16 0000
3020 DMAADDR DMAADDR<31:0>
15:0 0000
TABLE 4-18: DMA CRC REGISTER MAP(1)

Virtual Address
Bits
Preliminary
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — BYTO<1:0> WBO — — BITO — — — — — — — — 0000

3030 DCRCCON
15:0 — — — PLEN<4:0> CRCEN CRCAPP CRCTYP — — CRCCH<2:0> 0000
31:16 0000
3040 DCRCDATA DCRCDATA<31:0>
15:0 0000
31:16 0000
3050 DCRCXOR DCRCXOR<31:0>
15:0 0000
DMA CHANNELS 0-7 REGISTER MAP(1)
TABLE 4-19:
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3060 DCH0CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
3070 DCH0ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
3080 DCH0INT
15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
3090 DCH0SSA CHSSA<31:0>
15:0 0000
31:16 0000
30A0 DCH0DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
30B0 DCH0SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
30C0 DCH0DSIZ
Preliminary
15:0 CHDSIZ<15:0> 0000

31:16 — — — — — — — — — — — — — — — — 0000
30D0 DCH0SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
PIC32MX5XX/6XX/7XX
30E0 DCH0DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
30F0 DCH0CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3100 DCH0CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3110 DCH0DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3120 DCH1CON
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
3130 DCH1ECON
3140 DCH1INT
31:16 0000
15:0 0000
31:16 0000
DS61156C-page 75
3160 DCH1DSA CHDSA<31:0>

15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
3170 DCH1SSIZ
15:0 CHSSIZ<15:0> 0000
TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
DS61156C-page 76
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3180 DCH1DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3190 DCH1SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31A0 DCH1DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31B0 DCH1CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31C0 DCH1CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31D0 DCH1DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31E0 DCH2CON
Preliminary
31:16 — — — — — — — — CHAIRQ<7:0> 00FF

31F0 DCH2ECON
3200 DCH2INT
31:16 0000
15:0 0000
31:16 0000
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
3230 DCH2SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3240 DCH2DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3250 DCH2SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3260 DCH2DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3270 DCH2CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3280 DCH2CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3290 DCH2DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
32A0 DCH3CON
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
32B0 DCH3ECON
32C0 DCH3INT
31:16 0000
32D0 DCH3SSA CHSSA<31:0>
15:0 0000
31:16 0000
32E0 DCH3DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
32F0 DCH3SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3300 DCH3DSIZ
15:0 CHDSIZ<15:0> 0000
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
3310 DCH3SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3320 DCH3DPTR
PIC32MX5XX/6XX/7XX
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3330 DCH3CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3340 DCH3CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3350 DCH3DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3360 DCH4CON
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
3370 DCH4ECON
3380 DCH4INT
31:16 0000
15:0 0000
31:16 0000
33A0 DCH4DSA CHDSA<31:0>
DS61156C-page 77
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
33B0 DCH4SSIZ
15:0 CHSSIZ15:0> 0000
DS61156C-page 78
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
33C0 DCH4DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
33D0 DCH4SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
33E0 DCH4DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
33F0 DCH4CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3400 DCH4CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3410 DCH4DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3420 DCH5CON
Preliminary
31:16 — — — — — — — — CHAIRQ<7:0> 00FF

3430 DCH5ECON
3440 DCH5INT
31:16 0000
15:0 0000
31:16 0000
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
3470 DCH5SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3480 DCH5DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3490 DCH5SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
34A0 DCH5DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
34B0 DCH5CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
34C0 DCH5CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
34D0 DCH5DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
34E0 DCH6CON
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
34F0 DCH6ECON
3500 DCH6INT
31:16 0000
15:0 0000
31:16 0000
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
3530 DCH6SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3540 DCH6DSIZ
15:0 CHDSIZ<15:0> 0000
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
3550 DCH6SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3560 DCH6DPTR
PIC32MX5XX/6XX/7XX
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3570 DCH6CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3580 DCH6CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3590 DCH6DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
35A0 DCH7CON
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
35B0 DCH7ECON
35C0 DCH7INT
31:16 0000
35D0 DCH7SSA CHSSA<31:0>
15:0 0000
31:16 0000
35E0 DCH7DSA CHDSA<31:0>
DS61156C-page 79
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
35F0 DCH7SSIZ
15:0 CHSSIZ<15:0> 0000
DS61156C-page 80
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3600 DCH7DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3610 DCH7SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3620 DCH7DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3630 DCH7CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3640 DCH7CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3650 DCH7DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
Preliminary

COMPARATOR REGISTER MAP(1)
TABLE 4-20:
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
A000 CM1CON
15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
A010 CM2CON
15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
A060 CMSTAT
15:0 — FRZ SIDL — — — — — — — — — — — C2OUT C1OUT 0000
TABLE 4-21: COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1)

Virtual Address
Bits
Preliminary
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
PIC32MX5XX/6XX/7XX
31:16 — — — — — — — — — — — — — — — — 0000
9800 CVRCON
15:0 ON — — — — — — — — CVROE CVRR CVRSS CVR<3:0> 0000
DS61156C-page 81
DS61156C-page 82
PIC32MX5XX/6XX/7XX
TABLE 4-22:
Virtual Address FLASH CONTROLLER REGISTER MAP
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
F400 NVMCON(1)
15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — NVMOP<3:0> 0000
31:16 0000
F410 NVMKEY NVMKEY<31:0>
15:0 0000
(1) 31:16 0000
F420 NVMADDR NVMADDR<31:0>
15:0 0000
31:16 0000
F430 NVMDATA NVMDATA<31:0>
15:0 0000
NVMSRC 31:16 0000
F440 NVMSRCADDR<31:0>
ADDR 15:0 0000
Preliminary
TABLE 4-23: SYSTEM CONTROL REGISTER MAP(1,2)

Virtual Address
Bits
All Resets(2)
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — PLLODIV<2:0> RCDIV<2:0> — SOSCRDY — PBDIV<1:0> PLLMULT<2:0> 0000

F000 OSCCON
15:0 — COSC<2:0> — NOSC<2:0> CLKLOCK ULOCK LOCK SLPEN CF UFRCEN SOSCEN OSWEN 0000
31:16 — — — — — — — — — — — — — — — — 0000
F010 OSCTUN
15:0 — — — — — — — — — — TUN<5:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0000 WDTCON
15:0 ON — — — — — — — — SWDTPS<4:0> — WDTCLR 0000
31:16 — — — — — — — — — — — — — — — — 0000
F600 RCON
15:0 — — — — — — CM VREGS EXTR SWR — WDTO SLEEP IDLE BOR POR 0000
31:16 — — — — — — — — — — — — — — — — 0000
F610 RSWRST
15:0 — — — — — — — — — — — — — — — SWRST 0000
information.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
TABLE 4-24: PORTA REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6000 TRISA
15:0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF
31:16 — — — — — — — — — — — — — — — — 0000
6010 PORTA
15:0 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6020 LATA
15:0 LATA15 LATA14 — — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6030 ODCA
15:0 ODCA15 ODCA14 — — — ODCA10 ODCA9 — ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
Preliminary
TABLE 4-25: PORTB REGISTER MAP(1)

Virtual Address
Bits
All Resets
Bit Range
PIC32MX5XX/6XX/7XX
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6040 TRISB
15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
31:16 — — — — — — — — — — — — — — — — 0000
6050 PORTB
15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6060 LATB
15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6070 ODCB
15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
DS61156C-page 83
DS61156C-page 84
PIC32MX5XX/6XX/7XX
TABLE 4-26: PORTC REGISTER MAP FOR PIC32MX575F256H, PIC32MX675F256H, PIC32MX575F512H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6080 TRISC
15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000
31:16 — — — — — — — — — — — — — — — — 0000
6090 PORTC
15:0 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60A0 LATC
15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — — — — — — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60B0 ODCC
15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — — — — — — 0000
Preliminary
TABLE 4-27: PORTC REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6080 TRISC
15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F00F
31:16 — — — — — — — — — — — — — — — — 0000
6090 PORTC
15:0 RC15 RC14 RC13 RC12 — — — — — — — RC4 RC3 RC2 RC1 — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60A0 LATC
15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 —
xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60B0 ODCC
15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — ODCC4 ODCC3 ODCC2 ODCC1 — 0000
TABLE 4-28: PORTD REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
60C0 TRISD
15:0 — — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0FFF
31:16 — — — — — — — — — — — — — — — — 0000
60D0 PORTD
15:0 — — — — RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60E0 LATD
15:0 — — — — LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60F0 ODCD
15:0 — — — — ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000
Preliminary
TABLE 4-29: PORTD REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
60C0 TRISD
15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF
31:16 — — — — — — — — — — — — — — — — 0000
60D0 PORTD
15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60E0 LATD
15:0 LAT15 LAT14 LAT13 LAT12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60F0 ODCD
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000
DS61156C-page 85
TABLE 4-30: PORTE REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6100 TRISE
15:0 — — — — — — — — TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF
31:16 — — — — — — — — — — — — — — — — 0000
6110 PORTE
15:0 — — — — — — — — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6120 LATE
15:0 — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6130 ODCE
15:0 — — — — — — — — ODCE7 0DCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000
Preliminary
TABLE 4-31: PORTE REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6100 TRISE
15:0 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF
31:16 — — — — — — — — — — — — — — — — 0000
6110 PORTE
15:0 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6120 LATE
15:0 — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6130 ODCE
15:0 — — — — — — ODCE9 ODCE8 ODCE7 0DCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000
DS61156C-page 86
TABLE 4-32: PORTF REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6140 TRISF
15:0 — — — — — — — — — — TRISF5 TRISF4 TRISF3 — TRISF1 TRISF0 003B
31:16 — — — — — — — — — — — — — — — — 0000
6150 PORTF
15:0 — — — — — — — — — — RF5 RF4 RF3 — RF1 RF0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6160 LATF
15:0 — — — — — — — — — — LATF5 LATF4 LATF3 — LATF1 LATF0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6170 ODCF
15:0 — — — — — — — — — — ODCF5 ODCF4 ODCF3 — ODCF1 ODCF0 0000
Preliminary
TABLE 4-33: PORTF REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6140 TRISF
15:0 — — TRISF13 TRISF12 — — — TRISF8 — — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F
31:16 — — — — — — — — — — — — — — — — 0000
6150 PORTF
15:0 — — RF13 RF12 — — — RF8 — — RF5 RF4 RF3 RF2 RF1 RF0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6160 LATF
15:0 — — LATF13 LATF12 — — — LATF8 — — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6170 ODCF
15:0 — — ODCF13 ODCF12 — — — ODCF8 — — ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000
DS61156C-page 87
DS61156C-page 88
PIC32MX5XX/6XX/7XX
TABLE 4-34: PORTG REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6180 TRISG
15:0 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 — — 03CC
31:16 — — — — — — — — — — — — — — — — 0000
6190 PORTG
15:0 — — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 — — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
61A0 LATG
15:0 — — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 — — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
61B0 ODCG
15:0 — — — — — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 — — 0000
Preliminary
TABLE 4-35: PORTG REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6180 TRISG
15:0 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF
31:16 — — — — — — — — — — — — — — — — 0000
6190 PORTG
15:0 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
61A0 LATG
15:0 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0
xxxx
31:16 — — — — — — — — — — — — — — — — 0000
61B0 ODCG
15:0 ODCG15 ODCG14 ODCG13 ODCG12 — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 ODCG1 ODCG0 0000
TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L,
PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
61C0 CNCON
15:0 ON FRZ SIDL — — — — — — — — — — — — — 0000
31:16 — — — — — — — — — — CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000
61D0 CNEN
15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000
31:16 — — — — — — — — — — CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
61E0 CNPUE
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
TABLE 4-37: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H,
Preliminary
PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)

Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
PIC32MX5XX/6XX/7XX
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
61C0 CNCON
15:0 ON FRZ SIDL — — — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — CNEN18 CNEN17 CNEN16 0000
61D0 CNEN
15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000
31:16 — — — — — — — — — — — — — CNPUE18 CNPUE17 CNPUE16 0000
61E0 CNPUE
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
DS61156C-page 89
PARALLEL MASTER PORT REGISTER MAP(1)
DS61156C-page 90
PIC32MX5XX/6XX/7XX
TABLE 4-38:
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
7000 PMCON
15:0 ON FRZ SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P — WRSP RDSP 0000
31:16 — — — — — — — — — — — — — — — — 0000
7010 PMMODE
15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
7020 PMADDR
15:0 CS2EN/A15 CS1EN/A14 ADDR<13:0> 0000
31:16 0000
7030 PMDOUT DATAOUT<31:0>
15:0 0000
31:16 0000
7040 PMDIN DATAIN<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
7050 PMAEN
15:0 PTEN<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
7060 PMSTAT
Preliminary
15:0 IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 0080
TABLE 4-39: PROGRAMMING AND DIAGNOSTICS REGISTER MAP

Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
F200 DDPCON
15:0 — — — — — — — — — — — — JTAGEN TROEN — — 0008
TABLE 4-40: PREFETCH REGISTER MAP
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — CHECOH 0000

4000 CHECON(1,2)
15:0 — — — — — — DCSZ<1:0> — — PREFEN<1:0> — PFMWS<2:0> 0000
(1) 31:16 CHEWEN — — — — — — — — — — — — — — — 0000
4010 CHEACC
15:0 — — — — — — — — — — — — CHEIDX<3:0> 0000
31:16 LTAGBOOT — — — — — — — LTAG<23:16> 00xx
4020 CHETAG(1)
15:0 LTAG<15:4> LVALID LLOCK LTYPE — xxx0
31:16 — — — — — — — — — — — — — — — — 0000
4030 CHEMSK(1)
15:0 LMASK<15:5> — — — — — 0000
31:16 xxxx
4040 CHEW0 CHEW0<31:0>
15:0 xxxx
31:16 xxxx
4050 CHEW1 CHEW1<31:0>
15:0 xxxx
31:16 xxxx
4060 CHEW2 CHEW2<31:0>
15:0 xxxx
Preliminary
31:16 xxxx
4070 CHEW3 CHEW3<31:0>
15:0 xxxx
31:16 — — — — — — — CHELRU<24:16> 0000
4080 CHELRU
PIC32MX5XX/6XX/7XX
15:0 CHELRU<15:0> 0000
31:16 xxxx
4090 CHEHIT CHEHIT<31:0>
15:0 xxxx
31:16 xxxx
40A0 CHEMIS CHEMIS<31:0>
15:0 xxxx
31:16 xxxx
40C0 CHEPFABT CHEPFABT<31:0>
15:0 xxxx
2: Reset value is dependent on DEVCFGx configuration.
DS61156C-page 91
RTCC REGISTER MAP(1)
DS61156C-page 92
PIC32MX5XX/6XX/7XX
TABLE 4-41:
Virtual Address
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — CAL<9:0> 0000

0200 RTCCON
15:0 ON FRZ SIDL — — — — — RTSECSEL RTCCLKON — — RTCWREN RTCSYNC HALFSEC RTCOE 0000
31:16 — — — — — — — — — — — — — — — — 0000
0210 RTCALRM
15:0 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000
31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
0220 RTCTIME
15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00
31:16 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> xxxx
0230 RTCDATE
15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx00
31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
0240 ALRMTIME
15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00
31:16 — — — — — — — — MONTH10<3:0> MONTH01<3:0> 00xx
0250 ALRMDATE
15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx0x
Preliminary
TABLE 4-42: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
Virtual Address
Bits
All Resets
Bit Range
(BFC0_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 FVBUSIO FUSBIDIO FSCMIO — — FCANIO FETHIO FMIIEN — — — — — FSRSSEL<2:0> xxxx

2FF0 DEVCFG3
15:0 USERID<15:0> xxxx
31:16 — — — — — — — — — — — — — FPLLODIV<2:0> xxxx
2FF4 DEVCFG2
15:0 FUPLLEN — — — — FUPLLIDIV<2:0> — FPLLMULT<2:0> — FPLLIDIV<2:0> xxxx
31:16 — — — — — — — — FWDTEN — — WDTPS<4:0> xxxx
2FF8 DEVCFG1
15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0> IESO — FSOSCEN — — FNOSC<2:0> xxxx
31:16 — — — CP — — — BWP — — — — PWP<7:4> xxxx
2FFC DEVCFG0
15:0 PWP<3:0> — — — — — — — — ICESEL — DEBUG<1:0> xxxx
TABLE 4-43: DEVICE AND REVISION ID SUMMARY(1)

Virtual Address
Bits
Preliminary
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
PIC32MX5XX/6XX/7XX
31:16 VER<3:0> DEVID<27:16> xxxx
F220 DEVID
15:0 DEVID<15:0> xxxx
Note 1: Reset values are dependent on the device variant. Refer to the “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80480) for more information.
DS61156C-page 93
DS61156C-page 94
PIC32MX5XX/6XX/7XX
TABLE 4-44:
Virtual Address USB REGISTER MAP
Bits
All Resets
Bit Range
(BF88_#)
Register
Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
5040 U1OTGIR
15:0 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5050 U1OTGIE
15:0 — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE 0000
31:16 — — — — — — — — — — — — — — — — 0000
5060 U1OTGSTAT
15:0 — — — — — — — — ID — LSTATE — SESVD SESEND — VBUSVD 0000
31:16 — — — — — — — — — — — — — — — — 0000
5070 U1OTGCON
15:0 — — — — — — — — DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000
31:16 — — — — — — — — — — — — — — — — 0000
5080 U1PWRC
15:0 — — — — — — — — UACTPND — — USLPGRD USBBUSY — USUSPEND USBPWR 0000
31:16 — — — — — — — — — — — — — — — — 0000
5200 U1IR URSTIF 0000
15:0 — — — — — — — — STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF
DETACHIF 0000
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
5210 U1IE URSTIE 0000
15:0 — — — — — — — — STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE
DETACHIE 0000
31:16 — — — — — — — — — — — — — — — — 0000
5220 U1EIR CRC5EF 0000
15:0 — — — — — — — — BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF PIDEF
EOFEF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5230 U1EIE CRC5EE 0000
15:0 — — — — — — — — BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE PIDEE
EOFEE 0000
31:16 — — — — — — — — — — — — — — — — 0000
5240 U1STAT
15:0 — — — — — — — — ENDPT<3:0> DIR PPBI — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
5250 U1CON PKTDIS USBEN 0000
15:0 — — — — — — — — JSTATE SE0 USBRST HOSTEN RESUME PPBRST
TOKBUSY SOFEN 0000
31:16 — — — — — — — — — — — — — — — — 0000
5260 U1ADDR
15:0 — — — — — — — — LSPDEN DEVADDR<6:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5270 U1BDTP1
15:0 — — — — — — — — BDTPTRL<7:1> — 0000
31:16 — — — — — — — — — — — — — — — — 0000
5280 U1FRML
15:0 — — — — — — — — FRML<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5290 U1FRMH
15:0 — — — — — — — — — — — — — FRMH<2:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52A0 U1TOK
15:0 — — — — — — — — PID<3:0> EP<3:0> 0000
TABLE 4-44: USB REGISTER MAP (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
52B0 U1SOF
15:0 — — — — — — — — CNT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52C0 U1BDTP2
15:0 — — — — — — — — BDTPTRH<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52D0 U1BDTP3
15:0 — — — — — — — — BDTPTRU<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52E0 U1CNFG1
15:0 — — — — — — — — UTEYE UOEMON USBFRZ USBSIDL — — — UASUSPND 0001
31:16 — — — — — — — — — — — — — — — — 0000
5300 U1EP0
15:0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5310 U1EP1
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5320 U1EP2
Preliminary
31:16 — — — — — — — — — — — — — — — — 0000
5330 U1EP3
31:16 — — — — — — — — — — — — — — — — 0000
5340 U1EP4
PIC32MX5XX/6XX/7XX
31:16 — — — — — — — — — — — — — — — — 0000
5350 U1EP5
31:16 — — — — — — — — — — — — — — — — 0000
5360 U1EP6
31:16 — — — — — — — — — — — — — — — — 0000
5370 U1EP7
31:16 — — — — — — — — — — — — — — — — 0000
5380 U1EP8
31:16 — — — — — — — — — — — — — — — — 0000
5390 U1EP9
31:16 — — — — — — — — — — — — — — — — 0000
53A0 U1EP10
31:16 — — — — — — — — — — — — — — — — 0000
53B0 U1EP11
31:16 — — — — — — — — — — — — — — — — 0000
53C0 U1EP12
DS61156C-page 95

31:16 — — — — — — — — — — — — — — — — 0000
53D0 U1EP13
TABLE 4-44: USB REGISTER MAP (CONTINUED)
DS61156C-page 96
PIC32MX5XX/6XX/7XX
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
53E0 U1EP14
31:16 — — — — — — — — — — — — — — — — 0000
53F0 U1EP15
Preliminary
TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L
DEVICES(1)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — ABAT REQOP<2:0> OPMOD<2:0> CANCAP — — — — 0400

B000 C1CON
15:0 ON — SIDLE — BUSY — — — — — — DNCNT<4:0> 0000
31:16 — — — — — — — — — WAKFIL — — — SEG2PH<2:0> 0000
B010 C1CFG
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — — — — — MODIE CTMRIE RBIE TBIE 0000
B020 C1INT
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF — — — — — — — MODIF CTMRIF RBIF TBIF 0000
31:16 — — — — — — — — — — — — — — — — 0000
B030 C1VEC
15:0 — — — FILHIT<4:0> — ICOD<6:0> 0000
31:16 — — — — — — — — — — TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
B040 C1TREC
15:0 TEC<7:0> REC<7:0> 0000
31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
Preliminary
B050 C1FSTAT
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
B060 C1RXOVF
31:16 CANTS<15:0>
PIC32MX5XX/6XX/7XX
0000
B070 C1TMR
15:0 CANTSPRE<15:0> 0000
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
B080 C1RXM0
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
B090 C1RXM1
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
B0A0 C1RXM2
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
B0B0 C1RXM3
15:0 EID<15:0> xxxx
31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000
B0C0 C1FLTCON0
B0D0 C1FLTCON1
B0E0 C1FLTCON2
DS61156C-page 97

B0F0 C1FLTCON3
B100 C1FLTCON4
15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000
information.
TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H,
DS61156C-page 98
PIC32MX5XX/6XX/7XX
PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L
DEVICES(1) (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

B110 C1FLTCON5
B120 C1FLTCON6
B130 C1FLTCON7
C1RXFn 31:16 SID<10:0> -— EXID — EID<17:16> xxxx
B140
(n = 0-31) 15:0 EID<15:0> xxxx
31:16 0000
B340 C1FIFOBA C1FIFOBA<31:0>
15:0 0000
C1FIFOCONn 31:16 — — — — — — — — — — — FSIZE<4:0> 0000
B350
Preliminary
(n = 0-31) 15:0 — FRESET UINC DONLY — — — — TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
RXN
31:16 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE — — — — RXOVFLIE RXFULLIE RXHALFIE 0000
C1FIFOINTn EMPTYIE
B360
(n = 0-31) RXN
15:0 — — — — — TXNFULLIF TXHALFIF TXEMPTYIF — — — — RXOVFLIF RXFULLIF RXHALFIF 0000
EMPTYIF
C1FIFOUAn 31:16 0000
B370 C1FIFOUA<31:0>
(n = 0-31) 15:0 0000
C1FIFOCIn 31:16 — — — — — — — — — — — — — — — — 0000
B380
(n = 0-31) 15:0 — — — — — — — — — — — C1FIFOCI<4:0> 0000
information.
TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — ABAT REQOP<2:0> OPMOD<2:0> CANCAP — — — — 0400

C000 C2CON
15:0 ON — SIDLE — BUSY — — — — — — DNCNT<4:0> 0000
31:16 — — — — — — — — — WAKFIL — — — SEG2PH<2:0> 0000
C010 C2CFG
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — — — — — MODIE CTMRIE RBIE TBIE 0000
C020 C2INT
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF — — — — — — — MODIF CTMRIF RBIF TBIF 0000
31:16 — — — — — — — — — — — — — — — — 0000
C030 C2VEC
15:0 — — — FILHIT<4:0> — ICOD<6:0> 0000
31:16 — — — — — — — — — — TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
C040 C2TREC
15:0 TEC<7:0> REC<7:0> 0000
C050 C2FSTAT
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0
Preliminary
0000
C060 C2RXOVF
31:16 CANTS<15:0> 0000
C070 C2TMR
PIC32MX5XX/6XX/7XX
15:0 CANTSPRE<15:0> 0000
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
C080 C2RXM0
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
C0A0 C2RXM1
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
C0B0 C2RXM2
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
C0B0 C2RXM3
15:0 EID<15:0> xxxx
C0C0 C2FLTCON0
C0D0 C2FLTCON1
C0E0 C2FLTCON2
DS61156C-page 99

C0F0 C2FLTCON3
information.
TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
DS61156C-page 100
PIC32MX5XX/6XX/7XX
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

C100 C2FLTCON4
15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000
C110 C2FLTCON5
C120 C2FLTCON6
C130 C2FLTCON7
C2RXFn 31:16 SID<10:0> -— EXID — EID<17:16> xxxx
C140
(n = 0-31) 15:0 EID<15:0> xxxx
31:16 0000
C340 C2FIFOBA C2FIFOBA<31:0>
Preliminary
15:0 0000
C2FIFOCONn 31:16 — — — — — — — — — — — FSIZE<4:0> 0000
C350
(n = 0-31) 15:0 — FRESET UINC DONLY — — — — TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
RXN 0000
31:16 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE — — — — RXOVFLIE RXFULLIE RXHALFIE
C2FIFOINTn EMPTYIE
C360
(n = 0-31) RXN 0000
15:0 — — — — — TXNFULLIF TXHALFIF TXEMPTYIF — — — — RXOVFLIF RXFULLIF RXHALFIF
EMPTYIF
C2FIFOUAn 31:16 0000
C370 C2FIFOUA<31:0>
(n = 0-31) 15:0 0000
C2FIFOCIn 31:16 — — — — — — — — — — — — — — — — 0000
C380
(n = 0-31) 15:0 — — — — — — — — — — — C2FIFOCI<4:0> 0000
information.
DS61156C-page 101
PIC32MX5XX/6XX/7XX
TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 PTV<15:0> 0000

9000 ETHCON1
15:0 ON FRZ SIDL — — — TXRTS RXEN AUTOFC — — MANFC — — — BUFCDEC 0000
31:16 — — — — — — — — — — — — — — — — 0000
9010 ETHCON2
15:0 — — — — — RXBUFSZ<6:0> — — — — 0000
31:16 TXSTADDR<31:16> 0000
9020 ETHTXST
15:0 TXSTADDR<15:2> — — 0000
31:16 RXSTADDR<31:16> 0000
9030 ETHRXST
15:0 RXSTADDR<15:2> — — 0000
31:16 0000
9040 ETHHT0 HT<31:0>
15:0 0000
31:16 0000
Preliminary
9050 ETHHT1 HT<63:32>

15:0 0000
31:16 0000
9060 ETHPMM0 PMM<31:0>
15:0 0000
31:16 0000
9070 ETHPMM1 PMM<63:32>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
9080 ETHPMCS
15:0 PMCS<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
9090 ETHPMO
15:0 PMO<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
90A0 ETHRXFC CRC CRC RUNT NOT
15:0 HTEN MPEN — NOTPM PMMODE<3:0> RUNTEN UCEN MCEN BCEN 0000
ERREN OKEN ERREN MEEN
31:16 — — — — — — — — RXFWM<7:0> 0000
90B0 ETHRXWM
15:0 — — — — — — — — RXEWM<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
90C0 ETHIEN TX RX EW FW RX PK RX TX TX RX RX
15:0 — — — — — 0000
BUSEIE BUSEIE MARKIE MARKIE DONEIE TPENDIE ACTIE DONEIE ABORTIE BUFNAIE OVFLWIE
31:16 — — — — — — — — — — — — — — — — 0000
90D0 ETHIRQ
15:0 — TXBUSE RXBUSE — — — EWMARK FWMARK RXDONE PKTPEND RXACT — TXDONE TXABORT RXBUFNA RXOVFLW 0000
Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
2: Reset values default to the factory programmed value.
DS61156C-page 102
PIC32MX5XX/6XX/7XX
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — BUFCNT<7:0> 0000

90E0 ETHSTAT
15:0 — — — — — — — — BUSY TXBUSY RXBUSY — — — — — 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9100
RXOVFLOW 15:0 RXOVFLWCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9110
FRMTXOK 15:0 FRMTXOKCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9120
SCOLFRM 15:0 SCOLFRMCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9130
MCOLFRM 15:0 MCOLFRMCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9140
Preliminary
FRMRXOK 15:0 FRMRXOKCNT<15:0> 0000

ETH 31:16 — — — — — — — — — — — — — — — — 0000
9150
FCSERR 15:0 FCSERRCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9160
ALGNERR 15:0 ALGNERRCNT<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
EMACx
9200 SOFT SIM RESET RESET RESET RESET
CFG1 15:0 — — — — — LOOPBACK TXPAUSE RXPAUSE PASSALL RXENABLE 800D
RESET RESET RMCS RFUN TMCS TFUN
31:16 — — — — — — — — — — — — — — — — 0000
EMACx
9210 EXCESS BP PAD CRC
CFG2 15:0 — NOBKOFF — — LONGPRE PUREPRE AUTOPAD VLANPAD DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
DFR NOBKOFF ENABLE ENABLE
EMACx 31:16 — — — — — — — — — — — — — — — — 0000
9220
IPGT 15:0 — — — — — — — — — B2BIPKTGP<6:0> 0012
EMACx 31:16 — — — — — — — — — — — — — — — — 0000
9230
IPGR 15:0 — NB2BIPKTGP1<6:0> — NB2BIPKTGP2<6:0> 0C12
EMACx 31:16 — — — — — — — — — — — — — — — — 0000

9240
CLRT 15:0 — — CWINDOW<5:0> — — — — RETX<3:0> 370F
EMACx 31:16 — — — — — — — — — — — — — — — — 0000
9250
MAXF 15:0 MACMAXF<15:0> 05EE

PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
EMACx
9260 RESET SPEED
SUPP 15:0 — — — — — — — — — — — — — — 1000
RMII RMII
EMACx 31:16 — — — — — — — — — — — — — — — — 0000
9270
TEST 15:0 — — — — — — — — — — — — — TESTBP TESTPAUSE SHRTQNTA 0000
31:16 — — — — — — — — — — — — — — — — 0000
EMACx
9280 RESET
MCFG 15:0 — — — — — — — — — CLKSEL<3:0> NOPRE SCANINC 0020
MGMT
EMACx 31:16 — — — — — — — — — — — — — — — — 0000
9290
MCMD 15:0 — — — — — — — — — — — — — — SCAN READ 0000
EMACx 31:16 — — — — — — — — — — — — — — — — 0000
92A0
MADR 15:0 — — — PHYADDR<4:0> — — — REGADDR<4:0> 0100
Preliminary
EMACx 31:16 — — — — — — — — — — — — — — — — 0000

92B0
MWTD 15:0 MWTD<15:0> 0000
EMACx 31:16 — — — — — — — — — — — — — — — — 0000
92C0
MRDD
PIC32MX5XX/6XX/7XX
15:0 MRDD<15:0> 0000
EMACx 31:16 — — — — — — — — — — — — — — — — 0000
92D0
MIND 15:0 — — — — — — — — — — — — LINKFAIL NOTVALID SCAN MIIMBUSY 0000
EMACx 31:16 — — — — — — — — — — — — — — — — xxxx
9300
SA0(2) 15:0 STNADDR6<7:0> STNADDR5<7:0> xxxx
EMACx 31:16 — — — — — — — — — — — — — — — — xxxx
9310
EMACx 31:16 — — — — — — — — — — — — — — — — xxxx
9320
DS61156C-page 103
PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
5.0 FLASH PROGRAM MEMORY PIC32MX5XX/6XX/7XX devices contain an internal
Flash program memory for executing user code. There
Note 1: This data sheet summarizes the features are three methods by which the user can program this
of the PIC32MX5XX/6XX/7XX family of memory:
devices. It is not intended to be a 1. Run-Time Self Programming (RTSP)
2. EJTAG Programming
complement the information in this data
sheet, refer to Section 5. “Flash Pro- 3. In-Circuit Serial Programming™ (ICSP™)
gram Memory” (DS61121) in the RTSP is performed by software executing from either
“PIC32MX Family Reference Manual”, Flash or RAM memory. Information about RTSP
which is available from the Microchip web techniques is available in Section 5. “Flash Program
site (www.microchip.com/PIC32). Memory” (DS61121) in the “PIC32MX Family
2: Some registers and associated bits Reference Manual”.
described in this section may not be avail- EJTAG is performed using the EJTAG port of the
able on all devices. Refer to Section 4.0 device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
information.
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32MX Flash Programming Specification”
(DS61145), which can be downloaded from the
Microchip web site.

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
6.0 RESETS The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
Note 1: This data sheet summarizes the features following is a list of device Reset sources:
of the PIC32MX5XX/6XX/7XX family of • POR: Power-on Reset
• MCLR: Master Clear Reset Pin
complement the information in this data • SWR: Software Reset
sheet, refer to Section 7. “Resets” • WDTR: Watchdog Timer Reset
(DS61118) in the “PIC32MX Family • BOR: Brown-out Reset
Reference Manual”, which is available • CMR: Configuration Mismatch Reset
from the Microchip web site
(www.microchip.com/PIC32). A simplified block diagram of the Reset module is
shown in Figure 6-1.
information.
FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM
MCLR
MCLR
Glitch Filter
Sleep or Idle WDTR

Voltage WDT
Time-out
Regulator
Enabled
Power-up POR
Timer SYSRST
VDD
VDD Rise
Detect
Brown-out BOR
Reset
Configuration
Mismatch
Reset CMR
SWR
Software Reset

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
7.0 INTERRUPT CONTROLLER The PIC32MX5XX/6XX/7XX interrupt module includes
the following features:
Note 1: This data sheet summarizes the features • Up to 96 Interrupt Sources
• Up to 64 Interrupt Vectors
comprehensive reference source. To • Single and Multi-Vector mode Operations
complement the information in this data • Five External Interrupts with Edge Polarity Control
sheet, refer to Section 8. “Interrupt • Interrupt Proximity Timer
Controller” (DS61108) in the “PIC32MX • Module Freeze in Debug mode
Family Reference Manual”, which is
• Seven User-Selectable Priority Levels for each
available from the Microchip web site
Vector
(www.microchip.com/PIC32).
• Four User-Selectable Subpriority Levels within
2: Some registers and associated bits each Priority
• Dedicated Shadow Set for User-Selectable
able on all devices. Refer to
Priority Level
4.0 “Memory Organization” in this data
sheet for device-specific register and bit • Software can Generate any Interrupt
information. • User-Configurable Interrupt Vector Table Location
• User-Configurable Interrupt Vector Spacing
PIC32MX5XX/6XX/7XX devices generate interrupt
requests in response to interrupt events from peripheral
modules. The interrupt control module exists externally
to the CPU logic and prioritizes the interrupt events
before presenting them to the CPU.
FIGURE 7-1: INTERRUPT CONTROLLER MODULE
Vector Number
Interrupt Requests
Interrupt Controller CPU Core

Priority Level
Shadow Set Number

PIC32MX5XX/6XX/7XX
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION
Vector Interrupt Bit Location
Interrupt Source(1) IRQ
Number Flag Enable Priority Sub-Priority
Highest Natural Order Priority
CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0>
CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8>
CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16>
INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24>
T1 – Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0>
IC1 – Input Capture 1 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8>
OC1 – Output Compare 1 6 6 IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16>
SPI1E – SPI1 Fault 23 23 IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24>
SPI1RX – SPI1 Receive Done 24 23 IFS0<24> IEC0<24> IPC5<28:26> IPC5<25:24>
SPI1TX – SPI1 Transfer Done 25 23 IFS0<25> IEC0<25> IPC5<28:26> IPC5<25:24>
U1AE – UART1A Error
SPI1AE – SPI1A Fault 26 24 IFS0<26> IEC0<26> IPC6<4:2> IPC6<1:0>
I2C1AB – I2C1A Bus Collision Event
U1ARX – UART1A Receiver
SPI1ARX – SPI1A Receive Done 27 24 IFS0<27> IEC0<27> IPC6<4:2> IPC6<1:0>
I2C1AS – I2C1A Slave Event
U1ATX – UART1A Transmitter
SPI1ATX – SPI1A Transfer Done 28 24 IFS0<28> IEC0<28> IPC6<4:2> IPC6<1:0>
I2C1AM – I2C1A Master Event
I2C1B – I2C1 Bus Collision Event 29 25 IFS0<29> IEC0<29> IPC6<12:10> IPC6<9:8>
I2C1S – I2C1 Slave Event 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8>
I2C1M – I2C1 Master Event 31 25 IFS0<31> IEC0<31> IPC6<12:10> IPC6<9:8>
CN – Input Change Interrupt 32 26 IFS1<0> IEC1<0> IPC6<20:18> IPC6<17:16>
AD1 – ADC1 Convert Done 33 27 IFS1<1> IEC1<1> IPC6<28:26> IPC6<25:24>
PMP – Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0>
Note 1: Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.

PIC32MX5XX/6XX/7XX
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
CMP1 – Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8>
CMP2 – Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16>
IC2AM – I2C2A Master Event
IC3AM – I2C3A Master Event
I2C2B – I2C2 Bus Collision Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8>
I2C2S – I2C2 Slave Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8>
I2C2M – I2C2 Master Event 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8>
FSCM – Fail-Safe Clock Monitor 46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16>
RTCC – Real-Time Clock 47 35 IFS1<15> IEC1<15> IPC8<28:26> IPC8<25:24>
DMA0 – DMA Channel 0 48 36 IFS1<16> IEC1<16> IPC9<4:2> IPC9<1:0>
FCE – Flash Control Event 56 44 IFS1<24> IEC1<24> IPC11<4:2> IPC11<1:0>
USB – USB Interrupt 57 45 IFS1<25> IEC1<25> IPC11<12:10> IPC11<9:8>
CAN1 – Control Area Network 1 58 46 IFS1<26> IEC1<26> IPC11<20:18> IPC11<17:16>
CAN2 – Control Area Network 2 59 47 IFS1<27> IEC1<27> IPC11<28:26> IPC11<25:24>
ETH – Ethernet Interrupt 60 48 IFS1<28> IEC1<28> IPC12<4:2> IPC12<1:0>
IC1E – Input Capture 1 Error 61 5 IFS1<29> IEC1<29> IPC1<12:10> IPC1<9:8>
PMPE – Parallel Master Port Error 66 28 IFS2<2> IEC2<2> IPC7<4:2> IPC7<1:0>
U1BE – UART1B Error 67 49 IFS2<3> IEC2<3> IPC12<12:10> IPC12<9:8>

PIC32MX5XX/6XX/7XX
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
U1BRX – UART1B Receiver 68 49 IFS2<4> IEC2<4> IPC12<12:10> IPC12<9:8>
U1BTX – UART1B Transmitter 69 49 IFS2<5> IEC2<5> IPC12<12:10> IPC12<9:8>
(Reserved) — — — — — —
Lowest Natural Order Priority

PIC32MX5XX/6XX/7XX
8.0 OSCILLATOR The PIC32MX5XX/6XX/7XX oscillator system has the
following modules and features:
CONFIGURATION
• A Total of Four External and Internal Oscillator
Note 1: This data sheet summarizes the features Options as Clock Sources
of the PIC32MX5XX/6XX/7XX family of • On-Chip PLL with User-Selectable Input Divider,
devices. It is not intended to be a Multiplier and Output Divider to Boost Operating
comprehensive reference source. To Frequency on Select Internal and External
complement the information in this data Oscillator Sources
sheet, refer to Section 6. “Oscillator • On-Chip User-Selectable Divisor Postscaler on
Configuration” (DS61112) in the Select Oscillator Sources
“PIC32MX Family Reference Manual”, • Software-Controllable Switching Between
which is available from the Microchip web Various Clock Sources
site (www.microchip.com/PIC32). • A Fail-Safe Clock Monitor (FSCM) that Detects
2: Some registers and associated bits Clock Failure and Permits Safe Application
described in this section may not be avail- Recovery or Shutdown
able on all devices. Refer to Section 4.0 • Dedicated On-Chip PLL for USB Peripheral
information.
FIGURE 8-1: PIC32MX5XX/6XX/7XX FAMILY CLOCK DIAGRAM

USB PLL
UFIN USB Clock (48 MHz)

div x PLL x24 div 2
UFRCEN
UFIN 4 MHz
FUPLLEN
Primary Oscillator FUPLLDIV<2:0>
(POSC)
C1(3) OSC1 XT, HS, EC
To Internal
RF(2) Logic 4 MHz FIN 5 MHz Postscaler Peripherals
XTAL XTPLL, HSPLL, div x
FIN ECPLL, FRCPLL PBCLK
Enable
div x PLL div y
RS(1) div 2
C2(3) PLL Input Divider PBDIV<2:0>
OSC2(4) PLL Output Divider
ADC FPLLIDIV<2:0> PLLODIV<2:0>
FRC PLL Multiplier

Oscillator COSC<2:0> PLLMULT<2:0>
8 MHz typical FRC CPU and Select Peripherals
div 16 FRC/16
TUN<5:0>
FRCDIV
Postscaler
FRCDIV<2:0> LPRC
LPRC
Oscillator 31.25 kHz typical
Secondary Oscillator (SOSC)

SOSCO 32.768 kHz SOSC
SOSCEN and FSOSCEN Clock Control Logic

Fail-Safe FSCM INT
SOSCI Clock
Monitor FSCM Event
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals.
NOSC<2:0>
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 M COSC<2:0>
3. Refer to Section 6. “Oscillator Configuration” (DS61112) in the
“PIC32MX Family Reference Manual” for help in determining the best FSCMEN<1:0> OSWEN
WDT, PWRT
oscillator components.
4. PBCLK out is available on the OSC2 pin in certain clock modes. Timer1, RTCC

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
9.0 PREFETCH CACHE Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
Note 1: This data sheet summarizes the features regions by implementing instruction caching, constant
of the PIC32MX5XX/6XX/7XX family of data caching and instruction prefetching.
comprehensive reference source. To 9.1 Features
sheet, refer to Section 4. “Prefetch • 16 Fully Associative Lockable Cache Lines
Cache” (DS61119) in the “PIC32MX • 16-Byte Cache Lines
Family Reference Manual”, which is • Up to Four Cache Lines Allocated to Data
available from the Microchip web site • Two Cache Lines with Address Mask to Hold
(www.microchip.com/PIC32). Repeated Instructions
2: Some registers and associated bits • Pseudo LRU Replacement Policy
described in this section may not be avail- • All Cache Lines are Software Writable
• 16-Byte Parallel Memory Fetch
sheet for device-specific register and bit • Predictive Instruction Prefetch
information.
FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM
FSM CTRL
Tag Logic Cache Line

BMX/CPU
CTRL
Bus Ctrl
BMX/CPU
Cache Ctrl
Prefetch Ctrl
Cache
Line RDATA
Hit LRU
Address
Encode
Miss LRU
Hit Logic
PreFetch
Prefetch PreFetch
Prefetch
Pre-Fetch Pre-Fetch
Tag
RDATA
CTRL
PFM

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
10.0 DIRECT MEMORY ACCESS • Automatic Word-Size Detection:
(DMA) CONTROLLER - Transfer granularity, down to byte level
- Bytes need not be word-aligned at source
Note 1: This data sheet summarizes the features and destination
of the PIC32MX5XX/6XX/7XX family of • Fixed Priority Channel Arbitration
devices. It is not intended to be a • Flexible DMA Channel Operating modes:
comprehensive reference source. To - Manual (software) or automatic (interrupt)
complement the information in this data DMA requests
sheet, refer to Section 31. “Direct
- One-Shot or Auto-Repeat Block Transfer
Memory Access (DMA) Controller” modes
(DS61117) in the “PIC32MX Family
- Channel-to-channel chaining
Reference Manual”, which is available
from the Microchip web site • Flexible DMA Requests:
(www.microchip.com/PIC32). - A DMA request can be selected from any of
the peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request
source
sheet for device-specific register and bit - A DMA transfer abort can be selected from
any of the peripheral interrupt sources
information.
- Pattern (data) match transfer termination
The PIC32MX Direct Memory Access (DMA) controller • Multiple DMA Channel Status Interrupts:
is a bus master module useful for data transfers - DMA channel block transfer complete
between different devices without CPU intervention. - Source empty or half empty
The source and destination of a DMA transfer can be
- Destination full or half full
any of the memory mapped modules existent in the
PIC32MX (such as Peripheral Bus (PBUS) devices: - DMA transfer aborted due to an external
SPI, UART, I2C™, etc.) or memory itself. event
- Invalid DMA address generated
Following are some of the key features of the DMA
• DMA Debug Support Features:
controller module:
- Most recent address accessed by a DMA
• Four Identical Channels, each Featuring: channel
- Auto-Increment Source and Destination - Most recent DMA channel to transfer data
Address registers • CRC Generation Module:
- Source and Destination Pointers - CRC module can be assigned to any of the
- Memory to memory and memory to available channels
peripheral transfers - CRC module is highly configurable
FIGURE 10-1: DMA BLOCK DIAGRAM
INT Controller System IRQ
SE
L
Peripheral Bus Address Decoder Channel 0 Control I0
Channel 1 Control I1 Y Bus Interface Device Bus + Bus Arbitration
I2
Global Control Channel n Control In

(DMACON) L
SE
Channel Priority
Arbitration

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
11.0 USB ON-THE-GO (OTG) The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communi-
Note 1: This data sheet summarizes the features cation. The voltage comparators monitor the voltage on
of the PIC32MX5XX/6XX/7XX family of the VBUS pin to determine the state of the bus. The
devices. It is not intended to be a transceiver provides the analog translation between
comprehensive reference source. To the USB bus and the digital logic. The SIE is a state
complement the information in this data machine that transfers data to and from the endpoint
sheet, refer to Section 27. “USB On- buffers and generates the hardware protocol for data
The-Go (OTG)” (DS61126) in the transfers. The USB DMA controller transfers data
“PIC32MX Family Reference Manual”, between the data buffers in RAM and the SIE. The inte-
which is available from the Microchip web grated pull-up and pull-down resistors eliminate the
site (www.microchip.com/PIC32). need for external signaling components. The register
2: Some registers and associated bits interface allows the CPU to configure and
described in this section may not be avail- communicate with the module.
able on all devices. Refer to Section 4.0 The PIC32MX USB module includes the following
“Memory Organization” in this data features:
sheet for device-specific register and bit • USB Full-Speed Support for Host and Device
information.
• Low-Speed Host Support
The Universal Serial Bus (USB) module contains • USB OTG Support
analog and digital components to provide a USB 2.0 • Integrated Signaling Resistors
full-speed and low-speed embedded host, full-speed • Integrated Analog Comparators for VBUS
device or OTG implementation with a minimum of Monitoring
external components. This module in Host mode is
• Integrated USB Transceiver
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller. • Transaction Handshaking Performed by
Hardware
The USB module consists of the clock generator, the
• Endpoint Buffering Anywhere in System RAM
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA control- • Integrated DMA to Access System RAM and
ler, pull-up and pull-down resistors, and the register Flash
interface. A block diagram of the PIC32MX USB OTG Note: IMPORTANT! The implementation and
module is presented in Figure 11-1. use of the USB specifications, as well as
other third party specifications or technol-
ogies, may require licensing; including,
but not limited to, USB Implementers
Forum, Inc. (also referred to as USB-IF).
The user is fully responsible for investigat-
ing and satisfying any applicable licensing
obligations.

PIC32MX5XX/6XX/7XX
FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM
USBEN
FRC
USB Suspend Oscillator
8 MHz Typical
CPU Clock Not POST
Sleep TUN<5:0>(4)
Primary Oscillator
(POST)
UFIN(5)
Div x PLL Div 2
OSC1 UFRCEN(3)
FUPLLIDIV(6) FUPLLEN(6)
USB Suspend To Clock Generator for Core and Peripherals
OSC2 Sleep or Idle
(PB Out)(1)
USB Module
USB
SRP Charge Voltage
Bus Comparators
SRP Discharge
48 MHz USB Clock(7)
Full Speed Pull-up
D+(2)
Registers
and
Control
Host Pull-down Interface
SIE
Transceiver
Low Speed Pull-up
D-(2)
DMA System
RAM
Host Pull-down
ID Pull-up
ID(8)
Vibes(8)
VUSB Transceiver Power 3.3V
Note 1: PB clock is only available on this pin for select EC modes.

2: Pins can be used as digital inputs when USB is not enabled.
3: This bit field is contained in the OSCCON register.
4: This bit field is contained in the OSCTRM register.
5: USB PLL UFIN requirements: 4 MHz.
6: This bit field is contained in the DEVCFG2 register.
7: A 48 MHz clock is required for proper USB operation.
8: Pins can be used as GPIO when the USB module is disabled.

PIC32MX5XX/6XX/7XX
12.0 I/O PORTS General purpose I/O pins are the simplest of peripher-
als. They allow the PIC® MCU to monitor and control
Note 1: This data sheet summarizes the features other devices. To add flexibility and functionality, some
of the PIC32MX5XX/6XX/7XX family of pins are multiplexed with alternate function(s). These
devices. It is not intended to be a functions depend on which peripheral features are on
comprehensive reference source. To the device. In general, when a peripheral is functioning,
complement the information in this data that pin may not be used as a general purpose I/O pin.
sheet, refer to Section 12. “I/O Ports” Following are some of the key features of this module:
(DS61120) in the “PIC32MX Family • Individual Output Pin Open-Drain Enable/Disable
• Individual Input Pin Weak Pull-up Enable/Disable
(www.microchip.com/PIC32). • Monitor Selective Inputs and Generate Interrupt
when Change in Pin State is Detected
2: Some registers and associated bits • Operation during CPU Sleep and Idle modes
• Fast Bit Manipulation using CLR, SET and INV
Registers
Figure 12-1 shows a block diagram of a typical
multiplexed I/O port.
information.
FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE

Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus D Q
SYSCLK CK ODC
EN Q
WR ODC
1 IO Cell
RD TRIS 0
0
1
D Q
TRIS 1
CK
EN Q 0
WR TRIS
Output Multiplexers
D Q
CK LAT IO Pin
EN Q
WR LAT
WR PORT
RD LAT
1
RD PORT
Q D Q D
0
Sleep Q CK Q CK
SYSCLK
Synchronization
Peripheral Input R
Peripheral Input Buffer
Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
 2010 Microchip Technology Inc. Preliminary DS61156C - page 121

PIC32MX5XX/6XX/7XX
12.1 Parallel I/O (PIO) Ports 12.1.2 DIGITAL INPUTS
All port pins have three registers (TRIS, LAT and Pins are configured as digital inputs by setting the cor-
PORT) that are directly associated with their operation. responding TRIS register bits = 1. When configured as
inputs, they are either TTL buffers or Schmitt Triggers.
TRIS is a Data Direction or Tri-State Control register Several digital pins share functionality with analog
that determines whether a digital pin is an input or an inputs and default to the analog inputs at POR. Setting
output. Setting a TRISx register bit = 1 configures the the corresponding bit in the AD1PCFG register = 1
corresponding I/O pin as an input; setting a TRISx enables the pin as a digital pin.
register bit = 0 configures the corresponding I/O pin as
an output. All port I/O pins are defined as inputs after a The maximum input voltage allowed on the input pins
device Reset. Certain I/O pins are shared with analog is the same as the maximum VIH specification. Refer to
peripherals and default to analog inputs after a device Section 31.0 “Electrical Characteristics” for VIH
Reset. specification details.
PORT is a register used to read the current state of the Note: Analog levels on any pin that is defined as
signal applied to the port I/O pins. Writing to a PORTx a digital input (including the ANx pins) may
register performs a write to the port’s latch, LATx cause the input buffer to consume current
register, latching the data to the port’s I/O pins. that exceeds the device specifications.
LAT is a register used to write data to the port I/O pins.
The LATx Latch register holds the data written to either 12.1.3 ANALOG INPUTS
the LATx or PORTx registers. Reading the LATx Latch Certain pins can be configured as analog inputs used
register reads the last value written to the by the ADC and comparator modules. Setting the cor-
corresponding PORT or Latch register. responding bits in the AD1PCFG register = 0 enables
Not all port I/O pins are implemented on some devices, the pin as an analog input pin and must have the corre-
therefore, the corresponding PORTx, LATx and TRISx sponding TRIS bit set = 1 (input). If the TRIS bit is
register bits will read as zeros. cleared = 0 (output), the digital output level (VOH or
VOL) will be converted. Any time a port I/O pin is config-
12.1.1 CLR, SET AND INV REGISTERS ured as analog, its digital input is disabled and the
corresponding PORTx register bit will read ‘0’. The
Every I/O module register has a corresponding CLR AD1PCFG register has a default value of ‘0x0000’;
(clear), SET (set) and INV (invert) register designed to therefore, all pins that share ANx functions are analog
provide fast atomic bit manipulations. As the name of (not digital) by default.
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation, 12.1.4 DIGITAL OUTPUTS
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’ Pins are configured as digital outputs by setting the
are not modified. corresponding TRIS register bits = 0. When configured
as digital outputs, these pins are CMOS drivers or can
Reading SET, CLR and INV registers returns undefined be configured as open-drain outputs by setting the cor-
values. To see the affects of a write operation to a SET, responding bits in the ODCx Open-Drain Configuration
CLR or INV register, the base register must be read. register.
To set PORTC bit 0, write to the LATSET register: The open-drain feature allows generation of outputs
LATCSET = 0x0001; higher than VDD (e.g., 5V) on any desired 5V tolerant
To clear PORTC bit 0, write to the LATCLR register: pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
LATCCLR = 0x0001;
maximum VIH specification.
To toggle PORTC bit 0, write to the LATINV register:
See the “Pin Diagrams” section for the available pins
LATCINV = 0x0001; and their functionality.
Note: Using a PORTxINV register to toggle a bit 12.1.5 ANALOG OUTPUTS

is recommended because the operation is Certain pins can be configured as analog outputs, such
performed in hardware atomically, using as the CVREF output voltage used by the comparator
fewer instructions, as compared to the module. Configuring the comparator reference module
traditional read-modify-write method to provide this output will present the analog output
shown below: voltage on the pin, independent of the TRIS register
PORTC ^= 0x0001; setting for the corresponding pin.
DS61156C - page 122 Preliminary  2010 Microchip Technology Inc.

PIC32MX5XX/6XX/7XX
13.0 TIMER1 This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can operate
Note 1: This data sheet summarizes the features of as a free-running interval timer for various timing applica-
the PIC32MX5XX/6XX/7XX family of tions and counting external events. This timer can also
devices. It is not intended to be a be used with the Low-Power Secondary Oscillator
comprehensive reference source. To (SOSC) for Real-Time Clock (RTC) applications. The
complement the information in this data following modes are supported:
sheet, refer to Section 14. “Timers” • Synchronous Internal Timer
(DS61105) in the “PIC32MX Family
• Synchronous Internal Gated Timer
from the Microchip web site • Synchronous External Timer
(www.microchip.com/PIC32). • Asynchronous External Timer
described in this section may not be avail- 13.1 Additional Supported Features
able on all devices. Refer to • Selectable Clock Prescaler
• Timer Operation during CPU Idle and Sleep mode
information. • Fast Bit Manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to Function as a Real-Time Clock (RTC).
FIGURE 13-1: TIMER1 BLOCK DIAGRAM(1)
PR1
Equal
16-Bit Comparator TSYNC (T1CON<2>)
1 Sync
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE (T1CON<7>)
Q
TCS (T1CON<1>)
TGATE (T1CON<7>)
ON (T1CON<15>)
SOSCO/T1CK x1
Gate Prescaler
SOSCEN
Sync 10 1, 8, 64, 256
SOSCI
PBCLK 00
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word, DEVCFG1.

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
14.0 TIMER2/3, TIMER4/5 Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
Note 1: This data sheet summarizes the features The 32-bit timers can operate in three modes:
of the PIC32MX5XX/6XX/7XX family of • Synchronous Internal 32-Bit Timer
• Synchronous Internal 32-Bit Gated Timer
complement the information in this data • Synchronous External 32-Bit Timer
sheet, refer to Section 14. “Timers” Note: In this chapter, references to registers,
(DS61105) of the “PIC32MX Family TxCON, TMRx and PRx, use ‘x’ to repre-
Reference Manual”, which is available sent Timer2 through 5 in 16-bit modes. In
from the Microchip web site 32-bit modes, ‘x’ represents Timer2 or 4;
(www.microchip.com/PIC32). ‘y’ represents Timer3 or 5.
described in this section may not be avail- 14.1 Additional Supported Features
4.0 “Memory Organization” in this data • Selectable Clock Prescaler
sheet for device-specific register and bit • Timers Operational during CPU Idle
information. • Time Base for Input Capture and Output Compare
This family of PIC32MX devices features four modules (Timer2 and Timer3 only)
synchronous 16-bit timers (default) that can operate as • ADC Event Trigger (Timer3 only)
a free-running interval timer for various timing applica- • Fast Bit Manipulation using CLR, SET and INV
tions and counting external events. The following registers
modes are supported:
• Synchronous Internal 16-Bit Timer
• Synchronous Internal 16-Bit Gated Timer
• Synchronous External 16-Bit Timer
FIGURE 14-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
TMRx Sync
ADC Event
Trigger(1) Comparator x 16
Equal
PRx
Reset
0
TxIF
Event Flag 1 Q D TGATE (TxCON<7>)
Q TCS (TxCON<1>)
TGATE (TxCON<7>)
ON (TxCON<15>)
TxCK(2) x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256
PBCLK 00
3
TCKPS (TxCON<6:4>)
Note 1: ADC event trigger is available on Timer3 only.

2: TxCK pins are not available on 64-pin devices.

PIC32MX5XX/6XX/7XX
FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1)
Reset
TMRy TMRx Sync
MS Half Word LS Half Word

ADC Event
Trigger(3) 32-Bit Comparator
Equal
PRy PRx
TyIF Event 0
Flag
1 Q D TGATE (TxCON<7>)
Q TCS (TxCON<1>)
TGATE (TxCON<7>)
ON (TxCON<15>)
TxCK(2) x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256
PBCLK 00
3
TCKPS (TxCON<6:4>)
Note 1: In this diagram, the use of “x’ in registers, TxCON, TMRx, PRx, TxCK, refers to either Timer2 or Timer4; the use of
‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is available only on the Timer2/3 pair.

PIC32MX5XX/6XX/7XX
15.0 INPUT CAPTURE 2. Capture timer value on every edge (rising and
falling)
Note 1: This data sheet summarizes the features 3. Capture timer value on every edge (rising and
of the PIC32MX5XX/6XX/7XX family of falling), specified edge first.
devices. It is not intended to be a 4. Prescaler Capture Event modes
- Capture timer value on every 4th rising
edge of input at ICx pin
sheet, refer to Section 15. “Input
Capture” (DS61122) of the “PIC32MX - Capture timer value on every 16th rising
Family Reference Manual”, which is edge of input at ICx pin
available from the Microchip web site Each input capture channel can select between one of
(www.microchip.com/PIC32). two 16-bit timers (Timer2 or Timer3) for the time base,
2: Some registers and associated bits or two 16-bit timers (Timer2 and Timer3) together to
described in this section may not be avail- form a 32-bit timer. The selected timer can use either
able on all devices. Refer to Section 4.0 an internal or external clock.
“Memory Organization” in this data Other operational features include:
• Device Wake-up from Capture Pin during CPU
information.
Sleep and Idle modes
The input capture module is useful in applications • Interrupt on Input Capture Event
requiring frequency (period) and pulse measurement. • 4-Word FIFO Buffer for Capture Values
The input capture module captures the 16-bit or 32-bit Interrupt Optionally Generated after 1, 2, 3 or 4
value of the selected Time Base registers when an Buffer Locations are Filled
event occurs at the ICx pin. The following events cause • Input Capture can also be used to Provide
capture events: Additional Sources of External Interrupts
1. Simple Capture Event modes
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM

ICx Input Timer3 Timer2
ICTMR
0 1
C32
FIFO Control
ICxBUF<31:16> ICxBUF<15:0>
Prescaler
Edge Detect
1, 4, 16
ICM<2:0>
ICM<2:0> FEDGE
ICBNE
ICOV
Interrupt
ICxCON Event
ICI<1:0> Generation
Data Space Interface
Interrupt Peripheral Data Bus

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
16.0 OUTPUT COMPARE The Output Compare module (OCMP) is used to gen-
erate a single pulse or a train of pulses in response to
Note 1: This data sheet summarizes the features selected time base events. For all modes of operation,
of the PIC32MX5XX/6XX/7XX family of the OCMP module compares the values stored in the
devices. It is not intended to be a OCxR and/or the OCxRS registers to the value in the
comprehensive reference source. To selected timer. When a match occurs, the OCMP
complement the information in this data module generates an event based on the selected
sheet, refer to Section 16. “Output mode of operation.
Capture” (DS61111) in the “PIC32MX The following are some of the key features:
Family Reference Manual”, which is
available from the Microchip web site • Multiple Output Compare Modules in a Device
(www.microchip.com/PIC32). • Programmable Interrupt Generation on Compare
Event
described in this section may not be avail- • Single and Dual Compare modes
able on all devices. Refer to Section 4.0 • Single and Continuous Output Pulse Generation
“Memory Organization” in this data • Pulse-Width Modulation (PWM) mode
sheet for device-specific register and bit • Hardware-Based PWM Fault Detection and
information. Automatic Output Disable
• Programmable Selection of 16-Bit or 32-Bit Time
Bases
• Can Operate from Either of Two Available 16-Bit
Time Bases or a Single 32-Bit Time Base
FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit

OCxIF(1)
OCxRS(1)
Output S Q
OCxR(1) OCx(1)
Logic R
3 Output Enable
OCM<2:0>
Mode Select OCFA or OCFB(2)
Comparator
0 1 OCTSEL 0 1
16 16
TMR Register Inputs Period Match Signals

from Time Bases(3) from Time Bases(3)
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
17.0 SERIAL PERIPHERAL The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
INTERFACE (SPI)
and other microcontroller devices. These peripheral
Note 1: This data sheet summarizes the features devices may be Serial EEPROMs, Shift registers, dis-
of the PIC32MX5XX/6XX/7XX family of play drivers, A/D Converters, etc. The PIC32MX SPI
devices. It is not intended to be a compre- module is compatible with Motorola® SPI and SIOP
hensive reference source. To complement interfaces.
the information in this data sheet, refer to Following are some of the key features of this module:
Section 23. “Serial Peripheral Interface
• Master and Slave modes Support
(SPI)” (DS61106) in the “PIC32MX
Family Reference Manual”, which is avail- • Four Different Clock Formats
able from the Microchip web site • Enhanced Framed SPI Protocol Support
(www.microchip.com/PIC32). • User-Configurable 8-Bit, 16-Bit and 32-Bit Data
2: Some registers and associated bits Width
described in this section may not be avail- • Separate SPI FIFO Buffers for Receive and
able on all devices. Refer to Section 4.0 Transmit
“Memory Organization” in this data - FIFO buffers act as 4/8/16-level deep FIFOs
sheet for device-specific register and bit based on 32/16/8-bit data width
information. • Programmable Interrupt Event on Every 8-Bit,
16-Bit and 32-Bit Data Transfer
• Operation during CPU Sleep and Idle mode
Registers
FIGURE 17-1: SPI MODULE BLOCK DIAGRAM

Internal
Data Bus
SPIxBUF
Read Write
FIFOs Share Address SPIxBUF
SPIxRXB FIFO SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx bit 0
SDOx Shift
Control
Slave Select Clock Edge
and Frame Control Select
Sync Control PBCLK
SSx/FSYNC
Baud Rate
Generator
SCKx
Enable Master Clock
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
18.0 INTER-INTEGRATED CIRCUIT The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
(I2C™)
communication standard. Figure 18-1 shows the I2C
Note 1: This data sheet summarizes the features module block diagram.
of the PIC32MX5XX/6XX/7XX family of Each I2C module has a 2-pin interface: the SCLx pin is
devices. It is not intended to be a clock and the SDAx pin is data.
Each I2C module offers the following key features:
sheet, refer to Section 24. “Inter- • I2C Interface Supporting both Master and Slave
Integrated Circuit” (DS61116) in the Operation
“PIC32MX Family Reference Manual”, • I2C Slave mode Supports 7 and 10-Bit Address
which is available from the Microchip web • I2C Master mode Supports 7 and 10-Bit Address
site (www.microchip.com/PIC32). • I2C Port allows Bidirectional Transfers between
2: Some registers and associated bits Master and Slaves
described in this section may not be avail- • Serial Clock Synchronization for I2C Port can be
able on all devices. Refer to Section 4.0 used as a Handshake Mechanism to Suspend
“Memory Organization” in this data and Resume Serial Transfer (SCLREL control)
sheet for device-specific register and bit • I2C Supports Multi-Master Operation; Detects Bus
information. Collision and Arbitrates Accordingly
• Provides Support for Address Bit Masking

PIC32MX5XX/6XX/7XX
FIGURE 18-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx Clock
I2CxRSR
LSB
SDAx Address Match

Match Detect Write
I2CxMSK
Write Read
I2CxADD
Read
Start and Stop

Bit Detect
Write
Start and Stop

Bit Generation I2CxSTAT
Control Logic
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSB
Shift Clock Read
Reload
Control
Write
BRG Down Counter I2CxBRG
Read
PBCLK

PIC32MX5XX/6XX/7XX
19.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are:
RECEIVER TRANSMITTER • Full-Duplex, 8-Bit or 9-Bit Data Transmission
(UART) • Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop Bits
Note 1: This data sheet summarizes the features • Hardware Auto-Baud Feature
• Hardware Flow Control Option
comprehensive reference source. To • Fully Integrated Baud Rate Generator (BRG) with
complement the information in this data 16-Bit Prescaler
sheet, refer to Section 21. “Universal • Baud Rates Ranging from 76 bps to 20 Mbps at
Asynchronous Receiver Transmitter 80 MHz
(UART)” (DS61107) in the “PIC32MX • 8-Level Deep First-In-First-Out (FIFO) Transmit
Family Reference Manual”, which is Data Buffer
available from the Microchip web site • 8-Level Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error
2: Some registers and associated bits Detection
described in this section may not be avail- • Support for Interrupt Only on Address Detect
able on all devices. Refer to Section 4.0 (9th bit = 1)
• Separate Transmit and Receive Interrupts
information. • Loopback mode for Diagnostic Support
• LIN 1.2 Protocol Support
The UART module is one of the serial I/O modules
available in PIC32MX5XX/6XX/7XX family devices. • IrDA Encoder and Decoder with 16x Baud Clock
The UART is a full-duplex, asynchronous communica- Output for External IrDA Encoder/Decoder
tion channel that communicates with peripheral Support
devices and personal computers through protocols, Figure 19-1 shows a simplified block diagram of the
such as RS-232, RS-485, LIN 1.2 and IrDA®. The UART.
module also supports the hardware flow control option,
with UxCTS and UxRTS pins, and also includes an
IrDA encoder and decoder.
FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA® BCLKx
UxRTS
Hardware Flow Control
UxCTS
UARTx Receiver UxRX
UARTx Transmitter UxTX
Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.

PIC32MX5XX/6XX/7XX
Figure 19-2 and Figure 19-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 19-2: UART RECEPTION
Char 1 Char 2-4 Char 5-10 Char 11-13
Read to
UxRXREG
UxRX Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 19-3: TRANSMISSION (8-BIT OR 9-BIT DATA)

8 into TxBUF
Write to
UxTXREG
TSR
BCLK/16 Pull from Buffer
(Shift Clock)
UxTX Start Bit 0 Bit 1 Stop Start Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10

PIC32MX5XX/6XX/7XX
20.0 PARALLEL MASTER PORT Key features of the PMP module include:
(PMP) • 8-Bit, 16-Bit Interface
• Up to 16 Programmable Address Lines
• Up to Two Chip Select Lines
devices. It is not intended to be a • Programmable Strobe Options
comprehensive reference source. To - Individual read and write strobes, or
complement the information in this data - Read/write strobe with enable strobe
sheet, refer to Section 13. “Parallel • Address Auto-Increment/Auto-Decrement
Master Port (PMP)” (DS61128) in the • Programmable Address/Data Multiplexing
“PIC32MX Family Reference Manual”,
• Programmable Polarity on Control Signals
which is available from the Microchip web
site (www.microchip.com/PIC32). • Parallel Slave Port Support
- Legacy addressable
described in this section may not be avail- - Address support
able on all devices. Refer to Section 4.0 - 4-byte deep auto-incrementing buffer
“Memory Organization” in this data • Programmable Wait States
sheet for device-specific register and bit • Operates during CPU Sleep and Idle modes
information.
The PMP is a parallel 8-bit/16-bit input/output module Registers
specifically designed to communicate with a wide • Freeze Option for In-Circuit Debugging
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and Note: On 64-pin devices, data pins, PMD<15:8>,
microcontrollers. Because the interface to parallel are not available.
peripherals varies significantly, the PMP module is
highly configurable.
FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
Control Lines
PIC32MX5XX/6XX/7XX PMA<0>
PMALL
Parallel
Master Port
PMA<1>
PMALH
Up to 16-Bit Address Flash
PMA<13:2> EEPROM
SRAM
PMA<14>
PMCS1
PMA<15>
PMCS2
PMRD
PMRD/PMWR
FIFO
PMWR Microcontroller LCD
PMENB Buffer
PMD<7:0>
PMD<15:8>(1)
16/8-Bit Data (with or without multiplexed addressing)
Note 1: On 64-pin devices, data pins, PMD<15:8>, are not available in 16-Bit Master modes.

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
21.0 REAL-TIME CLOCK AND Following are some of the key features of this module:
CALENDAR (RTCC) • Time: Hours, Minutes and Seconds
• 24-Hour Format (Military Time)
• Visibility of One Half Second Period
devices. It is not intended to be a • Provides Calendar: Weekday, Date, Month and
comprehensive reference source. To Year
complement the information in this data • Alarm Intervals are Configurable for Half of a
sheet, refer to Section 29. “Real-Time Second, One Second, 10 Seconds, One Minute,
Clock and Calendar (RTCC)” 10 Minutes, One Hour, One Day, One Week, One
(DS61125) in the “PIC32MX Family Month and One Year
Reference Manual”, which is available • Alarm Repeat with Decrementing Counter
from the Microchip web site • Alarm with Indefinite Repeat: Chime
(www.microchip.com/PIC32). • Year Range: 2000 to 2099
2: Some registers and associated bits • Leap Year Correction
described in this section may not be avail- • BCD Format for Smaller Firmware Overhead
• Optimized for Long-Term Battery Operation
sheet for device-specific register and bit • Fractional Second Synchronization
information. • User Calibration of the Clock Crystal Frequency
with Auto-Adjust
The PIC32MX RTCC module is intended for applica- • Calibration Range: 0.66 Seconds Error per
tions in which accurate time must be maintained for Month
extended periods of time with minimal or no CPU
• Calibrates up to 260 ppm of Crystal Error
intervention. Low-power optimization provides
extended battery lifetime while keeping track of time. • Requirements: External 32.768 kHz Clock Crystal
• Alarm Pulse or Seconds Clock Output on
RTCC Pin
FIGURE 21-1: RTCC BLOCK DIAGRAM
32.768 kHz Input

from Secondary
Oscillator (SOSC)
RTCC Prescalers
0.5s YEAR, MTH, DAY
RTCC Timer RTCVAL WKDAY
Alarm HR, MIN, SEC
Event
Comparator
MTH, DAY
Compare Registers ALRMVAL WKDAY
with Masks
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin
RTCOE

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
22.0 10-BIT ANALOG-TO-DIGITAL • One Unipolar, Differential Sample and Hold
Amplifier (SHA)
CONVERTER (ADC)
• Automatic Channel Scan mode
Note 1: This data sheet summarizes the features • Selectable Conversion Trigger Source
of the PIC32MX5XX/6XX/7XX family of • 16-word Conversion Result Buffer
devices. It is not intended to be a • Selectable Buffer Fill modes
comprehensive reference source. To • Eight Conversion Result Format Options
• Operation during CPU Sleep and Idle modes
sheet, refer to Section 17. “10-Bit
Analog-to-Digital Converter (ADC)” A block diagram of the 10-bit ADC is shown in
(DS61104) in the “PIC32MX Family Figure 22-1. The 10-bit ADC has up to 16 analog input
Reference Manual”, which is available pins, designated AN0-AN15. In addition, there are two
from the Microchip web site analog input pins for external voltage reference
(www.microchip.com/PIC32). connections. These voltage reference inputs may be
shared with other analog input pins and may be
2: Some registers and associated bits common to other analog module references.
The analog inputs are connected through two multi-
plexers (MUXs) to one SHA. The analog input MUXs
“Memory Organization” in this data can be switched between two sets of analog inputs
sheet for device-specific register and bit between conversions. Unipolar differential conversions
information. are possible on all channels, other than the pin used as
the reference, using a reference input pin (see
The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital
Figure 22-1).
(A/D) Converter (or ADC) includes the following
features: The Analog Input Scan mode sequentially converts
• Successive Approximation Register (SAR) user-specified channels. A control register specifies
Conversion which analog input channels will be included in the
scanning sequence.
• Up to 1 Msps Conversion Speed
• Up to 16 Analog Input Pins The 10-bit ADC is connected to a 16-word result buffer.
Each 10-bit result is converted to one of eight 32-bit
• External Voltage Reference Input Pins output formats when it is read from the result buffer.
FIGURE 22-1: ADC1 MODULE BLOCK DIAGRAM

VREF+(1) AVDD VREF-(1) AVSS
VCFG<2:0>
AN0 ADC1BUF0
ADC1BUF1
AN15 ADC1BUF2
S/H VREFH VREFL
Channel
Scan +
CH0SA<4:0> CH0SB<4:0> SAR ADC
-
CSCNA
AN1
ADC1BUFE
VREFL
ADC1BUFF
CH0NA CH0NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.

PIC32MX5XX/6XX/7XX
FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
FRC Div 2 0
TAD
ADCS<7:0> 1
ADC Conversion
Clock Multiplier
TPB
2, 4,..., 512

PIC32MX5XX/6XX/7XX
23.0 CONTROLLER AREA • Message Reception and Transmission:
NETWORK (CAN) - 32 message FIFOs
- Each FIFO can have up to 32 messages for a
Note 1: This data sheet summarizes the features total of 1024 messages
of the PIC32MX5XX/6XX/7XX family of - FIFO can be a transmit message FIFO or a
devices. It is not intended to be a receive message FIFO
- User-defined priority levels for message
FIFOs used for transmission
sheet, refer to Section 34. “Controller
Area Network (CAN)” in the “PIC32MX - 32 acceptance filters for message filtering
Family Reference Manual”, which is - Four acceptance filter mask registers for
available from the Microchip web site message filtering
(www.microchip.com/PIC32). - Automatic response to remote transmit request
2: Some registers and associated bits - DeviceNet™ addressing support
described in this section may not be avail- • Additional Features:
able on all devices. Refer to Section 4.0 - Loopback, Listen All Messages and Listen
“Memory Organization” in this data Only modes for self-test, system diagnostics
sheet for device-specific register and bit and bus monitoring
information. - Low-power operating modes
The Controller Area Network (CAN) module supports - CAN module is a bus master on the
the following key features: PIC32MX system bus
• Standards Compliance: - Use of DMA is not required
- Full CAN 2.0B compliance - Dedicated time-stamp timer
- Programmable bit rate up to 1 Mbps - Dedicated DMA channels
- Data Only Message Reception mode
Figure 23-1 illustrates the general structure of the CAN
module.
FIGURE 23-1: PIC32MX CAN MODULE BLOCK DIAGRAM
CxTX
32 Filters
4 Masks
CxRX CPU
CAN Module
System Bus
Message
Buffer Size
System RAM 2 or 4 Words
Up to 32 Message Buffers
Message Buffer 31 Message Buffer 31 Message Buffer 31

FIFO0 FIFO1 FIFO31
CAN Message FIFO (up to 32 FIFOs)

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
24.0 ETHERNET CONTROLLER Following are some of the key features of this module:
• Supports 10/100 Mbps Data Transfer Rates
• Supports Full-Duplex and Half-Duplex Operation
devices. It is not intended to be a • Supports RMII and MII PHY Interface
comprehensive reference source. To • Supports MIIM PHY Management Interface
complement the information in this data • Supports both Manual and Automatic Flow Control
sheet, refer to Section 35. “Ethernet • RAM Descriptor-Based DMA Operation for Both
Controller” in the “PIC32MX Family Receive and Transmit Path
• Fully Configurable Interrupts
(www.microchip.com/PIC32). • Configurable Receive Packet Filtering
- CRC Check
described in this section may not be avail- - 64-Byte Pattern Match
able on all devices. Refer to Section 4.0 - Broadcast, Multicast and Unicast packets
“Memory Organization” in this data - Magic Packet™
sheet for device-specific register and bit - 64-Bit Hash Table
information. - Runt Packet
The Ethernet controller is a bus master module that • Supports Packet Payload Checksum Calculation
interfaces with an off-chip Physical Layer (PHY) to • Supports Various Hardware Statistics Counters
implement a complete Ethernet node in a system. Figure 24-1 shows a block diagram of the Ethernet
controller.
FIGURE 24-1: ETHERNET CONTROLLER BLOCK DIAGRAM

FIFO
TX
TX DMA TX BM
TX Bus TX Function
Master
TX Flow Control
System Bus
MII/RMII
IF
RX Flow
Control
FIFO
RX
RX DMA RX BM
MAC External
PHY
RX Bus RX Filter RX Function
Master
Checksum MIIM
IF
MAC Control
Fast Peripheral
DMA
Control and
Registers Configuration
Ethernet DMA
Bus
Registers
Host IF
Ethernet Controller

PIC32MX5XX/6XX/7XX
Table 24-1, Table 24-2, Table 24-3 and Table 24-4
show four interfaces and the associated pins that can TABLE 24-3: MII MODE ALTERNATE
be used with the Ethernet Controller. INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 0)(1)
TABLE 24-1: MII MODE DEFAULT Pin Name Description
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 1) AEMDC Management Clock
AEMDIO Management IO
Pin Name Description
AETXCLK Transmit Clock
EMDC Management Clock
AETXEN Transmit Enable
EMDIO Management IO
AETXD0 Transmit Data
ETXCLK Transmit Clock
ETXEN Transmit Enable
ETXD0 Transmit Data
ETXD1 Transmit Data
AETXERR Transmit Error
ETXD2 Transmit Data
AERXCLK Receive Clock
ETXD3 Transmit Data
AERXDV Receive Data Valid
ETXERR Transmit Error
AERXD0 Receive Data
ERXCLK Receive Clock
AERXD1 Receive Data
ERXDV Receive Data Valid
AERXD2 Receive Data
ERXD0 Receive Data
AERXD3 Receive Data
ERXD1 Receive Data
AERXERR Receive Error
ERXD2 Receive Data
AECRS Carrier Sense
ERXD3 Receive Data
AECOL Collision Indication
ERXERR Receive Error
Note 1: MII Alternate Interface is not available on
ECRS Carrier Sense 64-pin devices.
ECOL Collision Indication
TABLE 24-4: RMII MODE ALTERNATE

TABLE 24-2: RMII MODE DEFAULT INTERFACE SIGNALS
INTERFACE SIGNALS (FMIIEN = 0, FETHIO = 0)
(FMIIEN = 0, FETHIO = 1) Pin Name Description
Pin Name Description
AEMDC Management Clock
EMDC Management Clock AEMDIO Management IO
EMDIO Management IO AETXEN Transmit Enable
ETXEN Transmit Enable AETXD0 Transmit Data
ETXD0 Transmit Data AETXD1 Transmit Data
ETXD1 Transmit Data AEREFCLK Reference Clock
EREFCLK Reference Clock AECRSDV Carrier Sense – Receive Data Valid
ECRSDV Carrier Sense – Receive Data Valid AERXD0 Receive Data
ERXDV Receive Data Valid AERXD1 Receive Data
ERXD0 Receive Data AERXERR Receive Error
ERXD1 Receive Data
ERXERR Receive Error

PIC32MX5XX/6XX/7XX
25.0 COMPARATOR The PIC32MX5XX/6XX/7XX analog comparator
module contains two comparators that can be
Note 1: This data sheet summarizes the features configured in a variety of ways.
of the PIC32MX5XX/6XX/7XX family of Following are some of the key features of this module:
comprehensive reference source. To • Selectable Inputs Available Include:
complement the information in this - Analog inputs multiplexed with I/O pins
data sheet, refer to Section 19. - On-chip internal absolute Voltage Reference
“Comparator” (DS61110) in the (IVREF)
“PIC32MX Family Reference Manual”, - Comparator Voltage Reference (CVREF)
which is available from the Microchip web
• Outputs can be Inverted
site (www.microchip.com/PIC32).
• Selectable Interrupt Generation
described in this section may not be avail- A block diagram of the comparator module is shown in
able on all devices. Refer to Section 4.0 Figure 25-1.
information.
FIGURE 25-1: COMPARATOR BLOCK DIAGRAM
Comparator 1
CREF COUT (CM1CON)

ON C1OUT (CMSTAT)
CPOL
C1IN+(1)
CVREF(2)
C1OUT
CCH<1:0> C1
C1IN-
COE
C1IN+
C2IN+
IVREF(2)
Comparator 2
CREF COUT (CM2CON)
ON C2OUT (CMSTAT)
CPOL
C2IN+
CVREF(2)
C2OUT
CCH<1:0> C2
C2IN-
COE
C2IN+
C1IN+
IVREF(2)
Note 1: On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module,
and therefore, is not available as a comparator input.
2: Internally connected.

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
26.0 COMPARATOR VOLTAGE The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
REFERENCE (CVREF)
its primary purpose is to provide a reference for the
Note 1: This data sheet summarizes the features analog comparators, it also may be used independently
of the PIC32MX5XX/6XX/7XX family of of them.
devices. It is not intended to be a compre- A block diagram of the module is shown in Figure 26-1.
hensive reference source. To complement The resistor ladder is segmented to provide two ranges
the information in this data sheet, refer to of voltage reference values and has a power-down
Section 20. “Comparator Voltage function to conserve power when the reference is not
Reference (CVREF)” (DS61109) in the being used. The module’s supply reference can be pro-
“PIC32MX Family Reference Manual”, vided from either device VDD/VSS or an external
which is available from the Microchip web voltage reference. The CVREF output is available for
site (www.microchip.com/PIC32). the comparators and typically available for pin output.
2: Some registers and associated bits The comparator voltage reference has the following
described in this section may not be avail- features:
• High and low range selection
sheet for device-specific register and bit • Sixteen output levels available for each range
information. • Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
FIGURE 26-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
AVDD
CVRSS = 0 8R
CVR<3:0>
CVREN R
R CVREF
R
16-to-1 MUX
16 Steps
CVREFOUT
CVRCON<CVROE>
R
R
R
CVRR 8R
CVRSS = 1
VREF-
AVSS
CVRSS = 0

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
27.0 POWER-SAVING FEATURES • SOSC Idle mode: the system clock is derived from
the SOSC.
Note 1: This data sheet summarizes the features Peripherals continue to operate, but can
of the PIC32MX5XX/6XX/7XX family of optionally be individually disabled.
devices. It is not intended to be a compre- • LPRC Idle mode: the system clock is derived from
hensive reference source. To complement the LPRC.
the information in this data sheet, refer to Peripherals continue to operate, but can option-
Section 10. “Power-Saving Features” ally be individually disabled. This is the lowest
(DS61130) in the “PIC32MX Family power mode for the device with a clock running.
• Sleep mode: the CPU, the system clock source
and any peripherals that operate from the system
clock source are Halted.
2: Some registers and associated bits Some peripherals can operate in Sleep using
described in this section may not be avail- specific clock sources. This is the lowest power
able on all devices. Refer to Section 4.0 mode for the device.
sheet for device-specific register and bit 27.3 Power-Saving Operation
information.
Peripherals and the CPU can be Halted or disabled to
This section describes power-saving features for the further reduce power consumption.
PIC32MX5XX/6XX/7XX. The PIC32MX devices offer a
total of nine methods and modes, organized into two 27.3.1 SLEEP MODE
categories, that allow the user to balance power Sleep mode has the lowest power consumption of the
consumption with device performance. In all of the device power-saving operating modes. The CPU and
methods and modes described in this section, power most peripherals are Halted. Select peripherals can
saving is controlled by software. continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual periph-
27.1 Power Saving with CPU Running eral module sections for descriptions of behavior in
Sleep.
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lower- Sleep mode includes the following characteristics:
ing the PBCLK and by individually disabling modules. • The CPU is Halted.
These methods are grouped into the following • The system clock source is typically shut down.
categories: See Section 27.3.3 “Peripheral Bus Scaling
• FRC Run mode: the CPU is clocked from the FRC Method” for specific information.
clock source with or without postscalers. • There can be a wake-up delay based on the
• LPRC Run mode: the CPU is clocked from the oscillator selection.
LPRC clock source. • The Fail-Safe Clock Monitor (FSCM) does not
• SOSC Run mode: the CPU is clocked from the operate during Sleep mode.
SOSC clock source. • The BOR circuit, if enabled, remains operative
during Sleep mode.
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable • The WDT, if enabled, is not automatically cleared
fraction of the CPU clock (SYSCLK). prior to entering Sleep mode.
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These periph-
27.2 CPU Halted Methods erals include I/O pins that detect a change in the
The device supports two power-saving modes, Sleep input signal, WDT, ADC, UART and peripherals
and Idle, both of which Halt the clock to the CPU. These that use an external clock input or the internal
modes operate with all clock sources, as listed below: LPRC oscillator (e.g., RTCC, Timer1 and Input
• POSC Idle mode: the system clock is derived from Capture).
the POSC. The system clock source continues to • I/O pins continue to sink or source current in the
operate. same manner as they do when the device is not in
Peripherals continue to operate, but can Sleep.
optionally be individually disabled. • The USB module can override the disabling of the
• FRC Idle mode: the system clock is derived from Posc or FRC. Refer to the USB section for
the FRC with or without postscalers. specific details.
Peripherals continue to operate, but can • Modules can be individually disabled by software
optionally be individually disabled. prior to entering Sleep in order to further reduce
consumption.

PIC32MX5XX/6XX/7XX
The processor will exit, or ‘wake-up’, from Sleep on one The processor will wake or exit from Idle mode on the
of the following events: following events:
• On any interrupt from an enabled source that is • On any interrupt event for which the interrupt
operating in Sleep. The interrupt priority must be source is enabled. The priority of the interrupt
greater than the current CPU priority. event must be greater than the current priority of
• On any form of device Reset. the CPU. If the priority of the interrupt event is
• On a WDT time-out. lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
If the interrupt priority is lower than or equal to the remain in Idle mode.
current priority, the CPU will remain Halted, but the
• On any form of device Reset
PBCLK will start running and the device will enter into
Idle mode. • On a WDT time-out interrupt
27.3.2 IDLE MODE 27.3.3 PERIPHERAL BUS SCALING

METHOD
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripher- Most of the peripherals on the device are clocked using
als to continue operation when the CPU is Halted. the PBCLK. The peripheral bus can be scaled relative to
Peripherals can be individually configured to Halt when the SYSCLK to minimize the dynamic power consumed
entering Idle by setting their respective SIDL bit. by the peripherals. The PBCLK divisor is controlled by
Latency, when exiting Idle mode, is very low due to the PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
CPU oscillator source remaining active. PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Notes: Changing the PBCLK divider ratio Peripherals, such as the interrupt controller, DMA, bus
requires recalculation of peripheral timing. matrix and prefetch cache, are clocked directly from
For example, assume the UART is config- SYSCLK. As a result, they are not affected by PBCLK
ured for 9600 baud with a PB clock ratio of divisor changes.
1:1 and a POSC of 8 MHz. When the PB
Most of the peripherals on the device are clocked using
clock divisor of 1:2 is used, the input
the PBCLK. The peripheral bus can be scaled relative to
frequency to the baud clock is cut in half;
the SYSCLK to minimize the dynamic power consumed
therefore, the baud rate is reduced to 1/2
by the peripherals. The PBCLK divisor is controlled by
its former value. Due to numeric truncation
PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
in calculations (such as the baud rate divi-
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
sor), the actual baud rate may be a tiny
using PBCLK are affected when the divisor is changed.
percentage different than expected. For
Peripherals such as USB, interrupt controller, DMA, bus
this reason, any timing calculation
matrix and prefetch cache are clocked directly from
required for a peripheral should be per-
SYSCLK. As a result, they are not affected by PBCLK
formed with the new PB clock frequency
divisor changes
instead of scaling the previous value
based on a change in the PB divisor ratio. Changing the PBCLK divisor affects:
Oscillator start-up and PLL lock delays • The CPU to peripheral access latency. The CPU
are applied when switching to a clock has to wait for next PBCLK edge for a read to
source that was disabled and that uses a complete. In 1:8 mode, this results in a latency of
crystal and/or the PLL. For example, one to seven SYSCLKs.
assume the clock source is switched from • The power consumption of the peripherals. Power
POSC to LPRC just prior to entering Sleep consumption is directly proportional to the fre-
in order to save power. No oscillator start- quency at which the peripherals are clocked. The
up delay would be applied when exiting greater the divisor, the lower the power consumed
Idle. However, when switching back to by the peripherals.
POSC, the appropriate PLL and or oscilla-
To minimize dynamic power, the PB divisor should be
tor start-up/lock delays would be applied.
chosen to run the peripherals at the lowest frequency
The device enters Idle mode when the SLPEN that provides acceptable system performance. When
(OSCCON<4>) bit is clear and a WAIT instruction is selecting a PBCLK divider, peripheral clock require-
executed. ments, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.

PIC32MX5XX/6XX/7XX
28.0 SPECIAL FEATURES PIC32MX5XX/6XX/7XX devices include several
features intended to maximize application flexibility and
Note: This data sheet summarizes the features of reliability, and minimize cost through elimination of
the PIC32MX5XX/6XX/7XX family family of external components. These are:
devices. It is not intended to be a compre- • Flexible Device Configuration
hensive reference source. To complement
• Watchdog Timer
the information in this data sheet, refer to
• JTAG Interface
the related section in the “PIC32MX Family
Reference Manual” (DS61132), which is • In-Circuit Serial Programming™ (ICSP™)
available from the Microchip web site
(www.microchip.com/PIC32). 28.1 Configuration Bits
The Configuration bits can be programmed to select
various device configurations.
REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0

r-0 r-1 r-1 R/P-1 r-1 r-1 r-1 R/P-1
— — — CP — — — BWP
bit 31 bit 24
r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1

— — — — PWP<7:4>
bit 23 bit 16
R/P-1 R/P-1 R/P-1 R/P-1 r-1 r-1 r-1 r-1

PWP<3:0> — — — —
bit 15 bit 8
r-1 r-1 r-1 r-1 R/P-1 r-1 R/P-1 R/P-1

— — — — ICESEL — DEBUG<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31 Reserved: Write ‘0’

bit 30-29 Reserved: Write ‘1’
bit 28 CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external
programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 24 BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable

PIC32MX5XX/6XX/7XX
REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 19-12 PWP<7:0>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution.
The PWP bits represent the one’s compliment of the number of write-protected program Flash
memory pages.
11111111 = Disabled
11111110 = 0xBD00_0FFF
11111101 = 0xBD00_1FFF
11111100 = 0xBD00_2FFF
11111011 = 0xBD00_3FFF
11111010 = 0xBD00_4FFF
11111001 = 0xBD00_5FFF
11111000 = 0xBD00_6FFF
11110111 = 0xBD00_7FFF
11110110 = 0xBD00_8FFF
11110101 = 0xBD00_9FFF
11110100 = 0xBD00_AFFF
11110011 = 0xBD00_BFFF
11110010 = 0xBD00_CFFF
11110001 = 0xBD00_DFFF
11110000 = 0xBD00_EFFF
11101111 = 0xBD00_FFFF
•
•
•
01111111 = 0xBD07_FFFF
bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = PGEC2/PGED2 pair is used
0 = PGEC1/PGED1 pair is used
bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger is disabled
10 = Debugger is enabled
01 = Reserved (same as ‘11’ setting)
00 = Reserved (same as ‘11’ setting)

PIC32MX5XX/6XX/7XX
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
bit 31 bit 24
R/P-1 r-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

FWDTEN — — WDTPS<4:0>
bit 23 bit 16
R/P-1 R/P-1 R/P-1 R/P-1 r-1 R/P-1 R/P-1 R/P-1

FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0>
bit 15 bit 8
R/P-1 r-1 R/P-1 r-1 r-1 R/P-1 R/P-1 R/P-1

IESO — FSOSCEN — — FNOSC<2:0>
bit 7 bit 0
Legend:

bit 23 FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
Note 1: Do not disable POSC (POSCMOD = 11) when using this oscillator source.

PIC32MX5XX/6XX/7XX
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
11 = PBCLK is SYSCLK divided by 8
bit 10 OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for
the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00)
0 = CLKO output disabled
bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits
11 = Primary oscillator disabled
10 = HS Oscillator mode selected
01 = XT Oscillator mode selected
00 = External Clock mode selected
bit 7 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 5 FSOSCEN: Secondary Oscillator Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 2-0 FNOSC<2:0>: Oscillator Selection bits
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010 = Primary Oscillator (XT, HS, EC)(1)
011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)
100 = Secondary Oscillator (SOSC)
101 = Low-Power RC Oscillator (LPRC)
110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
Note 1: Do not disable POSC (POSCMOD = 11) when using this oscillator source.

PIC32MX5XX/6XX/7XX
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
bit 31 bit 24
r-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1

— — — — — FPLLODIV<2:0>
bit 23 bit 16
R/P-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1

UPLLEN — — — — UPLLIDIV<2:0>
bit 15 bit 8
r-1 R/P-1 R/P-1 R/P-1 r-1 R/P-1 R/P-1 R/P-1

— FPLLMULT<2:0> — FPLLIDIV<2:0>
bit 7 bit 0
Legend:

bit 18-16 FPLLODIV<2:0>: Default Postscaler for PLL bits
111 = PLL output divided by 256
bit 15 UPLLEN: USB PLL Enable bit
1 = Enable USB PLL
0 = Disable and bypass USB PLL
bit 10-8 UPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider

PIC32MX5XX/6XX/7XX
bit 6-4 FPLLMULT<2:0>: PLL Multiplier bits
111 = 24x multiplier
bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider

PIC32MX5XX/6XX/7XX
R/P-1 R/P-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1
FVBUSONIO FUSBIDIO — — — FCANIO FETHIO FMIIEN
bit 31 bit 24
r-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1

— — — — — FSRSSEL<2:0>
bit 23 bit 16
R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x

USERID<15:8>
bit 15 bit 8
R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x

USERID<7:0>
bit 7 bit 0
Legend:
bit 31 FVBUSONIO: USB VBUS_ON Selection bit

1 = VBUSON pin is controlled by the USB module
0 = VBUSON pin is controlled by the port function
bit 30 FUSBIDIO: USB USBID Selection bit
1 = USBID pin is controlled by the USB module
0 = USBID pin is controlled by the port function
bit 26 FCANIO: CAN I/O Pin Selection bit
1 = Default CAN I/O Pins
0 = Alternate CAN I/O Pins
bit 25 FETHIO: Ethernet I/O Pin Selection bit
1 = Default Ethernet I/O Pins
0 = Alternate Ethernet I/O Pins
bit 24 FMIIEN: Ethernet MII Enable bit
1 = MII is enabled
0 = RMII is enabled
bit 18-16 FSRSSEL<2:0>: SRS Select bits
111 = Assign Interrupt Priority 7 to a shadow register set
•
•
•
000 = All interrupt priorities are assigned to a shadow register set
bit 15-0 USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG

PIC32MX5XX/6XX/7XX
REGISTER 28-5: DEVID: DEVICE AND REVISION ID REGISTER
R R R R R R R R
VER<3:0>(1) DEVID<27:24> (1)
bit 31 bit 24
R R R R R R R R
(1)
DEVID<23:16>
bit 23 bit 16
R R R R R R R R
(1)
DEVID<15:8>
bit 15 bit 8
R R R R R R R R
DEVID<7:0>(1)
bit 7 bit 0
Legend:
bit 31-28 VER<3:0>: Revision Identifier bits(1)

bit 27-0 DEVID<27:0>: Device ID(1)
Note 1: See the “PIC32MX Flash Programming Specification” (DS61145) for a list of Revision and Device ID values.

PIC32MX5XX/6XX/7XX
28.2 Watchdog Timer (WDT) The following are some of the key features of the WDT
module:
This section describes the operation of the WDT and
Power-up Timer of the PIC32MX5XX/6XX/7XX. • Configuration or software controlled
• User-configurable time-out period
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be • Can wake the device from Sleep or Idle
used to detect system software malfunctions by reset-
ting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
FIGURE 28-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable LPRC

WDT Enable Control
PWRT Enable
1:64 Output
LPRC PWRT
Oscillator
1
Clock
25-Bit Counter
WDTCLR = 1
WDT Enable 25
Wake 0 Device Reset
WDT Counter Reset
WDT Enable 1 NMI (Wake-up)
Reset Event
Power Save
Decoder
FWDTPS<4:0>(DEVCFG1<20:16>)

PIC32MX5XX/6XX/7XX
28.3 On-Chip Voltage Regulator 28.3.3 POWER-UP REQUIREMENTS
All PIC32MX5XX/6XX/7XX devices’ core and digital The on-chip regulator is designed to meet the power-up
logic are designed to operate at a nominal 1.8V. To requirements for the device. If the application does not
simplify system designs, most devices in the use the regulator, then strict power-up conditions must
PIC32MX5XX/6XX/7XX family incorporate an on-chip be adhered to. While powering up, VDDCORE must
regulator providing the required core logic voltage from never exceed VDD by 0.3 volts.
VDD.
A low-ESR capacitor (such as tantalum) must be con- FIGURE 28-2: CONNECTIONS FOR THE
nected to the VCAP/VDDCORE pin (see Figure 28-2). ON-CHIP REGULATOR
This helps to maintain the stability of the regulator.
The recommended value for the filter capacitor is
3.3V(1)
provided in Section 31.1 “DC Characteristics”.
PIC32MX
Note: It is important that the low-ESR capacitor VDD
is placed as close as possible to the
VCAP/VDDCORE pin.
VCAP/VDDCORE
28.3.1 ON-CHIP REGULATOR AND POR CEFC(2)
VSS
It takes a fixed delay for the on-chip regulator to generate (10 F typ)
an output. During this time, designated as TPU, code exe-
cution is disabled. TPU is applied every time the device Note 1: These are typical operating voltages. Refer
resumes operation after any power-down, including to Section 31.1 “DC Characteristics” for
Sleep mode. the full operating ranges of VDD and
If the regulator is disabled, a separate Power-up Timer VDDCORE.
(PWRT) is automatically enabled. The PWRT adds a 2: It is important that the low-ESR capacitor
is placed as close as possible to the
fixed delay of TPWRT at device start-up. See
VCAP/VDDCORE pin.
Section 31.0 “Electrical Characteristics” for more
information on TPU AND TPWRT.
28.3.2 ON-CHIP REGULATOR AND BOR

PIC32MX5XX/6XX/7XX devices also have a simple
brown-out capability. If the voltage supplied to the reg-
ulator is inadequate to maintain a regulated level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON<1>). The brown-out voltage levels are specific
in Section 31.1 “DC Characteristics”.

PIC32MX5XX/6XX/7XX
28.4 Programming and Diagnostics PIC32MX devices incorporate two programming and
diagnostic modules, and a trace controller, that provide
PIC32MX5XX/6XX/7XX devices provide a complete a range of functions to the application developer.
range of programming and diagnostic features that can
increase the flexibility of any application using them.
These features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
FIGURE 28-3: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS
PGEC1
PGED1
ICSP™
Controller
PGEC2
PGED2
ICESEL
TDI
TDO JTAG
Controller Core
TCK
TMS
JTAGEN DEBUG<1:0>
TRCLK
TRD0
Instruction Trace
TRD1
Controller
TRD2
TRD3
DEBUG<1:0>

PIC32MX5XX/6XX/7XX
REGISTER 28-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
— — — — — — — —
bit 31 bit 24
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0

— — — — — — — —
bit 23 bit 16
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0

— — — — — — — —
bit 15 bit 8
r-0 r-0 r-0 r-0 R/W-1 R/W-0 r-0 r-0

— — — — JTAGEN TROEN — —
bit 7 bit 0
Legend:
bit 31-4 Reserved: Write ‘0’; ignore read

bit 3 JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2 TROEN: Trace Output Enable bit
1 = Enable the trace port
0 = Disable the trace port
bit 1-0 Reserved: Write ‘1’; ignore read

PIC32MX5XX/6XX/7XX
29.0 INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction set
complies with the MIPS32 Release 2 instruction set
architecture. PIC32MX does not support the following
features:
• Core Extend Instructions
• Coprocessor 1 Instructions
• Coprocessor 2 Instructions
Note: Refer to “MIPS32® Architecture for Pro-
grammers Volume II: The MIPS32®
Instruction Set” at www.mips.com for more
information.

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
30.0 DEVELOPMENT SUPPORT 30.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software The MPLAB IDE software brings an ease of software
and hardware development tools: development previously unseen in the 8/16/32-bit
• Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools
- MPLAB C Compiler for Various Device - Simulator
Families - Programmer (sold separately)
- HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately)
- MPASMTM Assembler - In-Circuit Debugger (sold separately)
- MPLINKTM Object Linker/ • A full-featured editor with color-coded context
MPLIBTM Object Librarian • A multiple project manager
- MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of
Various Device Families contents
• Simulators • High-level source code debugging
- MPLAB SIM Software Simulator • Mouse over variable inspection
• Emulators • Drag and drop variables from source to watch
- MPLAB REAL ICE™ In-Circuit Emulator windows
• In-Circuit Debuggers • Extensive on-line help
- MPLAB ICD 3 • Integration of select third party tools, such as
- PICkit™ 3 Debug Express IAR C Compilers
• Device Programmers The MPLAB IDE allows you to:
- PICkit™ 2 Programmer • Edit your source files (either C or assembly)
- MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to
• Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically
Evaluation Kits, and Starter Kits updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

PIC32MX5XX/6XX/7XX
30.2 MPLAB C Compilers for Various 30.5 MPLINK Object Linker/
Device Families MPLIB Object Librarian
The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable
are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the
PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects
dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a
lers. These compilers provide powerful integration linker script.
capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and
use. modification of library files of precompiled code. When
For easy source level debugging, the compilers provide a routine from a library is called from a source file, only
symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in
debugger. with the application. This allows large libraries to be
used efficiently in many different applications.
30.3 HI-TECH C for Various Device The object linker/library features include:
Families • Efficient linking of single libraries instead of many
The HI-TECH C Compiler code development systems smaller files
are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping
family of microcontrollers and the dsPIC family of digital related modules together
signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module
integration capabilities, omniscient code generation listing, replacement, deletion and extraction
and ease of use.
For easy source level debugging, the compilers provide 30.6 MPLAB Assembler, Linker and
symbol information that is optimized to the MPLAB IDE Librarian for Various Device
debugger. Families
The compilers include a macro assembler, linker, pre-
MPLAB Assembler produces relocatable machine
processor, and one-step driver, and can run on multiple
code from symbolic assembly language for PIC24,
platforms.
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
30.4 MPASM Assembler generates relocatable object files that can then be
The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and
macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set
files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data
reference, absolute LST files that contain source lines • Command line interface
and generated machine code and COFF files for • Rich directive set
debugging.
• Flexible macro language
The MPASM Assembler features include: • MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process

PIC32MX5XX/6XX/7XX
30.7 MPLAB SIM Software Simulator 30.9 MPLAB ICD 3 In-Circuit Debugger
The MPLAB SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro-
ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig-
examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU)
a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon-
logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy-
buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated
the simulator to record and track program execution, Development Environment (IDE).
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger probe is con-
The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed
symbolic debugging using the MPLAB C Compilers, USB 2.0 interface and is connected to the target with a
and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB
ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers.
ronment, making it an excellent, economical software
development tool. 30.10 PICkit 3 In-Circuit Debugger/
Programmer and
30.8 MPLAB REAL ICE In-Circuit
PICkit 3 Debug Express
Emulator System
The MPLAB PICkit 3 allows debugging and program-
MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a
Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical
Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development
programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected
with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB
the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an
included with each kit. Microchip debug (RJ-11) connector (compatible with
The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector
using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple-
to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro-
circuit debugger systems (RJ11) or with the new high- gramming™.
speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo
(LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM
The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and
downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software.
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.

PIC32MX5XX/6XX/7XX
30.11 PICkit 2 Development 30.13 Demonstration/Development
Programmer/Debugger and Boards, Evaluation Kits, and
PICkit 2 Debug Express Starter Kits
The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and
a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC
face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func-
families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for
Windows® programming interface supports baseline adding custom circuitry and provide application firmware
(PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification.
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232
microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional
products. With Microchip’s powerful MPLAB Integrated EEPROM memory.
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be
trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom
steps the program while the PIC microcontroller is circuits and for learning about various microcontroller
embedded in the application. When halted at a break- applications.
point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon-
The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip
board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software
with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN,
MPLAB IDE software. IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
30.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually
CE compliant device programmer with programmable includes a single application and debug capability, all
voltage verification at VDDMIN and VDDMAX for on one board.
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu- Check the Microchip web page (www.microchip.com)
lar, detachable socket assembly to support various for the complete list of demonstration, development
package types. The ICSP™ cable assembly is included and evaluation kits.
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.

PIC32MX5XX/6XX/7XX
31.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(1)

Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3) ......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD  2.3V (Note 3) ........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3) ............................. -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2) ....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.

PIC32MX5XX/6XX/7XX
31.1 DC Characteristics
TABLE 31-1: OPERATING MIPS VS. VOLTAGE

VDD Range Temp. Range Max. Frequency
Characteristic
(in Volts) (in °C) PIC32MX5XX/6XX/7XX
DC5 2.3-3.6V -40°C to +85°C 80 MHz (Note 1)
Note 1: 40 MHz maximum for PIC32MX 40 MHz family variants.
TABLE 31-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typical Max. Unit
PIC32MX5XX/6XX/7XX
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 31-3: THERMAL PACKAGING CHARACTERISTICS

Characteristics Symbol Typical Max. Unit Notes
Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm) JA 40 — °C/W 1
Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm) JA 43 — °C/W 1
Package Thermal Resistance, 64-Pin QFN (9x9x0,9 mm) JA 28 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 31-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.3V to 3.6V
DC CHARACTERISTICS (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Param.
Symbol Characteristics Min. Typical Max. Units Conditions
No.
Operating Voltage
DC10 Supply Voltage
VDD 2.3 — 3.6 V
DC12 VDR RAM Data Retention Voltage 1.75 — — V
(Note 1)
DC16 VPOR VDD Start Voltage 1.75 — 1.95 V
to Ensure Internal
Power-on Reset Signal
DC17 SVDD VDD Rise Rate 0.00005 — 0.115 V/s
to Ensure Internal
Power-on Reset Signal
Note 1: This is the limit to which VDD can be lowered without losing RAM data.

PIC32MX5XX/6XX/7XX
TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Parameter
Typical(3) Max. Units Conditions
No.
Operating Current (IDD)(1,2)
DC20 6 9 mA Code executing from Flash —
4 MHz
DC20c 4 — mA Code executing from SRAM —
DC21 37 40 mA Code executing from Flash — 25 MHz
DC21c 25 — mA Code executing from SRAM — (Note 4)
DC22 64 70 mA Code executing from Flash — 60 MHz
DC22c 61 — mA Code executing from SRAM — (Note 4)
DC23 85 98 mA Code executing from Flash —
80 MHz
DC23c 85 — mA Code executing from SRAM —
LPRC (31 kHz)
DC25a 125 150 µA +25°C 3.3V
(Note 4)
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by
external square wave from rail-to-rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data
memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are dis-
abled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and
FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: This parameter is characterized, but not tested in manufacturing.

PIC32MX5XX/6XX/7XX
TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Parameter
No.
Idle Current (IIDLE): Core Off, Clock On Base Current (Note 1)
DC30 4.5 6.5 mA 4 MHz
DC31 13 15 mA 25 MHz (Note 3)
DC32 28 30 mA 60 MHz (Note 3)
DC33 36 42 mA 80 MHz
DC34 — 40 µA -40°C
DC34a — 75 µA +25°C 2.3V
DC34b — 800 µA +85°C
DC35 35 — µA -40°C
LPRC (31 kHz)
DC35a 65 — µA +25°C 3.3V
(Note 3)
DC35b 600 — µA +85°C
DC36 — 43 µA -40°C
DC36a — 106 µA +25°C 3.6V
DC36b — 800 µA +85°C
Note 1: The test conditions for base IDLE current measurements are as follows: System clock is enabled and
PBCLK divisor = 1:8. CPU in Idle mode (CPU core Halted). Only digital peripheral modules are enabled
(ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and
pulled to VSS. MCLR = VDD.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.

PIC32MX5XX/6XX/7XX
TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Parameter
No.
Power-Down Current (IPD) (Note 1)
DC40 10 40 A -40°C
DC40a 36 100 A +25°C 2.3V Base Power-Down Current (Note 6)
DC40b 400 720 A +85°C
DC40c 41 120 A +25°C 3.3V Base Power-Down Current
DC40d 22 80 A -40°C
DC40e 42 120 A +25°C
3.6V Base Power-Down Current
DC40g 315 400 A +70°C
DC40f 410 800 A +85°C
Module Differential Current
DC41 — 10 A 2.3V Watchdog Timer Current: IWDT (Notes 3, 6)
DC41c 5 — A 3.3V Watchdog Timer Current: IWDT (Note 3)
DC41d — 20 A 3.6V Watchdog Timer Current: IWDT (Note 3)
DC42 — 40 A RTCC + Timer1 w/32 kHz Crystal: IRTCC
2.3V
(Notes 3, 6)
DC42c 23 — A 3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC
(Note 3)
DC42e — 50 A RTCC + Timer1 w/32 kHz Crystal: IRTCC
3.6V
(Note 3)
DC43 — 1300 A 2.5V ADC: IADC (Notes 3, 4, 6)
DC43c 1100 — A 3.3V ADC: IADC (Notes 3, 4)
DC43e — 1300 A 3.6V ADC: IADC (Notes 3, 4)
Note 1: Base IPD is measured with all digital peripheral modules and being clocked, CPU clock is disabled. All I/Os
are configured as inputs and pulled low. WDT and FSCM are disabled.
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
3: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.

PIC32MX5XX/6XX/7XX
TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
DC CHARACTERISTICS stated)
Param.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
No.
VIL Input Low Voltage
DI10 I/O Pins:
with TTL Buffer VSS — 0.15 VDD V (Note 4)
with Schmitt Trigger Buffer VSS — 0.2 VDD V (Note 4)
(2)
DI15 MCLR VSS — 0.2 VDD V (Note 4)
DI16 OSC1 (XT mode) VSS — 0.2 VDD V (Note 4)
DI17 OSC1 (HS mode) VSS — 0.2 VDD V (Note 4)
DI18 SDAx, SCLx VSS — 0.3 VDD V SMBus disabled
(Note 4)
DI19 SDAx, SCLx VSS — 0.8 V SMBus enabled
(Note 4)
VIH Input High Voltage
DI20 I/O Pins:
with Analog Functions 0.8 VDD — VDD V (Note 4)
Digital Only 0.8 VDD — V (Note 4)
with TTL Buffer 0.25 VDD + 0.8V — 5.5 V (Note 4)
with Schmitt Trigger Buffer 0.8 VDD — 5.5 V (Note 4)
DI25 MCLR(2) 0.8 VDD — VDD V (Note 4)
DI26 OSC1 (XT mode) 0.7 VDD — VDD V (Note 4)
DI27 OSC1 (HS mode) 0.7 VDD — VDD V (Note 4)
DI28 SDAx, SCLx 0.7 VDD — 5.5 V SMBus disabled
(Note 4)
DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled,
2.3V  VPIN  5.5
(Note 4)
DI30 ICNPU CNxx Pull up Current 50 250 400 A VDD = 3.3V, VPIN = VSS
IIL Input Leakage Current
(Note 3)
DI50 I/O Ports — — +1 A VSS  VPIN  VDD,
Pin at high-impedance
DI51 Analog Input Pins — — +1 A VSS  VPIN  VDD,
Pin at high-impedance
DI55 MCLR(2) — — +1 A VSS VPIN VDD
DI56 OSC1 — — +1 A VSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.

PIC32MX5XX/6XX/7XX
TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
DC CHARACTERISTICS stated)
Param.
No.
VOL Output Low Voltage
DO10 I/O Ports — — 0.4 V IOL = 7 mA, VDD = 3.6V
— — 0.4 V IOL = 6 mA, VDD = 2.3V
DO16 OSC2/CLKO — — 0.4 V IOL = 3.5 mA, VDD = 3.6V
— — 0.4 V IOL = 2.5 mA, VDD = 2.3V
VOH Output High Voltage
DO20 I/O Ports 2.4 — — V IOH = -12 mA, VDD = 3.6V
1.4 — — V IOH = -12 mA, VDD = 2.3V
DO26 OSC2/CLKO 2.4 — — V IOH = -12 mA, VDD = 3.6V
1.4 — — V IOH = -12 mA, VDD = 2.3V
TABLE 31-10: DC CHARACTERISTICS: PROGRAM MEMORY(3)

(unless otherwise stated)
DC CHARACTERISTICS
Programming temperature 0°C  TA  +70°C (25°C recommended)
Param.
No.
Program Flash Memory
D130 EP Cell Endurance 1000 — — E/W -40°C to +85°C
D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating
voltage
D132 VPEW VDD for Erase or Write 3.0 — 3.6 V 0°C to +40°C
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications
are violated
D135 IDDP Supply Current during — 10 — mA 0°C to +40°C
Programming
TWW Word Write Cycle Time 20 — 40 s 0°C to +40°C
D136 TRW Row Write Cycle Time 3 4.5 — ms 0°C to +40°C
(Note 2)
(128 words per row)
D137 TPE Page Erase Cycle Time 20 — — ms 0°C to +40°C
TCE Chip Erase Cycle Time 80 — — ms 0°C to +40°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
3: Refer to the “PIC32MX Flash Programming Specification” (DS61145) for operating conditions during
programming and erase cycles.

PIC32MX5XX/6XX/7XX
TABLE 31-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
Required Flash Wait States SYSCLK Units Comments
0 Wait State 0 to 30 MHz
1 Wait State 31 to 60
2 Wait States 61 to 80
TABLE 31-12: COMPARATOR SPECIFICATIONS

Param.
Symbol Characteristics Min. Typical Max. Units Comments
No.
D300 VIOFF Input Offset Voltage — ±7.5 ±25 mV AVDD = VDD,
AVSS = VSS
D301 VICM Input Common Mode Voltage 0 — VDD V AVDD = VDD,
AVSS = VSS
(Note 2)
D302 CMRR Common Mode Rejection Ratio 55 — — dB Max VICM = (VDD – 1)V
(Note 2)
D303 TRESP Response Time — 150 400 ns AVDD = VDD,
AVSS = VSS
(Notes 1, 2)
D304 ON2OV Comparator Enabled to Output — — 10 s Comparator module is
Valid configured before setting
the comparator ON bit.
(Note 2)
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
2: These parameters are characterized but not tested.

PIC32MX5XX/6XX/7XX
TABLE 31-13: VOLTAGE REFERENCE SPECIFICATIONS
Param.
No.
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy — — 1/2 LSb
(1)
D312 TSET Settling Time — — 10 s
D313 VIREF Internal Voltage Reference — 0.6 — V
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter is
characterized, but not tested in manufacturing.
TABLE 31-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Param.
No.
D320 VDDCORE Regulator Output Voltage 1.62 1.80 1.98 V
D321 CEFC External Filter Capacitor Value 8 10 — F Capacitor must be low series
resistance (1 ohm)
D322 TPWRT Power-up Timer Period — 64 — ms

PIC32MX5XX/6XX/7XX
31.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX5XX/6XX/7XX AC characteristics and timing
parameters.
TABLE 31-15: AC CHARACTERISTICS

(unless otherwise stated)
AC CHARACTERISTICS
Operating voltage VDD range.
FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins
VSS 50 pF for OSC2 pin (EC mode)
TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

AC CHARACTERISTICS (unless otherwise stated)
Param.
No.
DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode
DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 31-2: EXTERNAL CLOCK TIMING
OS20 OS30 OS31
OSC1
OS30 OS31

PIC32MX5XX/6XX/7XX
TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
OS10 FOSC External CLKI Frequency DC — 50 (Note 3) MHz EC (Note 5)
(External clocks allowed only 4 — 50 (Note 5) MHz ECPLL (Note 4)
in EC and ECPLL modes)
OS11 Oscillator Crystal Frequency 3 — 10 MHz XT (Note 5)
OS12 4 — 10 MHz XTPLL
(Notes 4, 5)
OS13 10 — 25 MHz HS (Note 5)
OS14 10 — 25 MHz HSPLL
(Notes 4, 5)
OS15 32 32.768 100 kHz SOSC (Note 5)
OS20 TOSC TOSC = 1/FOSC = TCY (Note 2) — — — — See parameter
OS10 for FOSC
value
OS30 TOSL, External Clock In (OSC1) 0.45 x TOSC — — ns EC (Note 5)
TOSH High or Low Time
OS31 TOSR, External Clock In (OSC1) — — 0.05 x TOSC ns EC (Note 5)
TOSF Rise or Fall Time
OS40 TOST Oscillator Start-up Timer Period — 1024 — TOSC (Note 5)
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
OS41 TFSCM Primary Clock Fail Safe — 2 — ms (Note 5)
Time-out Period
OS42 GM External Oscillator — 12 — mA/V VDD = 3.3V,
Transconductance TA = +25°C
(Note 5)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not
tested.
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
3: 40 MHz maximum for PIC32MX 40 MHz family variants.
4: PLL input requirements: 4 MHZ  FPLLIN  5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but tested at 10 MHz only at manufacturing.

PIC32MX5XX/6XX/7XX
TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
Param.
Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions
No.
OS50 FPLLI PLL Voltage Controlled 4 — 5 MHz ECPLL, HSPLL, XTPLL,
Oscillator (VCO) Input FRCPLL modes
Frequency Range
OS51 FSYS On-Chip VCO System 60 — 120 MHz
Frequency
OS52 TLOCK PLL Start-up Time (Lock Time) — — 2 ms
OS53 DCLK CLKO Stability -0.25 — +0.25 % Measured over 100 ms
(Period Jitter or Cumulative) period
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 31-19: INTERNAL FRC ACCURACY

Operating temperature -40°C  TA +85°C for industrial
Param.
Characteristics Min. Typical Max. Units Conditions
No.
Internal FRC Accuracy @ 8.00 MHz (Note 1)
F20 FRC -2 — +2 %
Note 1: Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 31-20: INTERNAL RC ACCURACY

Param.
Characteristics Min. Typical Max. Units Conditions
No.
LPRC @ 31.25 kHz (Note 1)
F21 LPRC -15 — +15 %
Note 1: Change of LPRC frequency as VDD changes.

PIC32MX5XX/6XX/7XX
FIGURE 31-3: I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-21: I/O TIMING REQUIREMENTS

Param.
No.
DO31 TIOR Port Output Rise Time — 5 15 ns VDD < 2.5V
— 5 10 ns VDD > 2.5V
DO32 TIOF Port Output Fall Time — 5 15 ns VDD < 2.5V
— 5 10 ns VDD > 2.5V
DI35 TINP INTx Pin High or Low Time 10 — — ns
DI40 TRBP CNx High or Low Time (input) 2 — — TSYSCLK
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

PIC32MX5XX/6XX/7XX
FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled

Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code

SY00
(TPU)
(Note 1)

Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR (TSYSDLY)
SY02
Power-up Sequence
(Note 2)

SY00 SY10
(TPU) (TOST)
(Note 1)
External VDDCORE Provided

VDD
VPOR VDDCORE
(TSYSDLY)
SY02
Power-up Sequence
(Note 3)
SY01
(TPWRT)
(Note 1)
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.
3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.

PIC32MX5XX/6XX/7XX
FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR (TSYSDLY)
(SY30) SY02
Reset Sequence
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY)

SY02
Reset Sequence

TOST
(SY10)
TABLE 31-22: RESETS TIMING

Param.
No.
SY00 TPU Power-up Period — 400 600 s -40°C to +85°C
SY01 TPWRT Power-up Period 48 64 80 ms -40°C to +85°C
External VDDCORE Applied
(Power-up timer active)
SY02 TSYSDLY System Delay Period: — s + — — -40°C to +85°C
Time Required to Reload Device 8 SYSCLK
Configuration Fuses plus SYSCLK cycles
Delay before First instruction is
Fetched.
SY20 TMCLR MCLR Pulse Width (low) — 2 — s -40°C to +85°C
SY30 TBOR BOR Pulse Width (low) — 1 — s -40°C to +85°C
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.

PIC32MX5XX/6XX/7XX
FIGURE 31-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

Param.
Symbol Characteristics(2) Min. Typical Max. Units Conditions
No.
TA10 TTXH TxCK Synchronous, [(12.5 ns or 1 TPB)/N] — — ns Must also meet
High Time with prescaler + 25 ns parameter TA15
Asynchronous, 10 — — ns
with prescaler
TA11 TTXL TxCK Synchronous, [(12.5 ns or 1 TPB)/N] — — ns Must also meet
Low Time with prescaler + 25 ns parameter TA15
Asynchronous, 10 — — ns
with prescaler
TA15 TTXP TxCK Synchronous, [(Greater of 25 ns or — — ns VDD > 2.7V
Input Period with prescaler 2 TPB)/N] + 30 ns
[(Greater of 25 ns or — — ns VDD < 2.7V
2 TPB)/N] + 50 ns
Asynchronous, 20 — — ns VDD > 2.7V
with prescaler (Note 3)
50 — — ns VDD < 2.7V
(Note 3)
OS60 FT1 SOSC1/T1CK Oscillator 32 — 100 kHz
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON<1>))
TA20 TCKEXTMRL Delay from External TxCK — 1 TPB
Clock Edge to Timer
Increment
Note 1: Timer1 is a Type A.
3: N = Prescale Value (1, 8, 64, 256)

PIC32MX5XX/6XX/7XX
TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
TB10 TTXH TxCK Synchronous, with [(12.5 ns or 1 TPB)/N] — ns Must also meet N = prescale
High Time prescaler + 25 ns parameter TB15 value
TB11 TTXL TxCK Synchronous, with [(12.5 ns or 1 TPB)/N] — ns Must also meet (1, 2, 4, 8, 16,
Low Time prescaler + 25 ns parameter TB15 32, 64, 256)
TB15 TTXP TxCK Input Synchronous, with [(Greater of [(25 ns or — ns VDD > 2.7V
Period prescaler 2 TPB)/N] + 30 ns
[(Greater of [(25 ns or — ns VDD < 2.7V
2 TPB)/N] + 50 ns
TB20 TCKEXTMRL Delay from External TxCK Clock — 1 TPB
Edge to Timer Increment
FIGURE 31-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICx
IC10 IC11
IC15
TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS

Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
IC10 TCCL ICx Input Low Time [(12.5 ns or 1 TPB)/N] — ns Must also N = prescale
+ 25 ns meet value (1, 4, 16)
parameter
IC15.
IC11 TCCH ICx Input High Time [(12.5 ns or 1 TPB)/N] — ns Must also
+ 25 ns meet
parameter
IC15.
IC15 TCCP ICx Input Period [(25 ns or 2 TPB)/N] — ns
+ 50 ns

PIC32MX5XX/6XX/7XX
FIGURE 31-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode) OC11 OC10
TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Param.
No.
OC10 TCCF OCx Output Fall Time — — — ns See parameter DO32
OC11 TCCR OCx Output Rise Time — — — ns See parameter DO31
and are not tested.
FIGURE 31-9: OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS

Param
Symbol Characteristics(1) Min Typical(2) Max Units Conditions
No.
OC15 TFD Fault Input to PWM I/O Change — — 50 ns
OC20 TFLT Fault Input Pulse Width 50 — — ns
and are not tested.

PIC32MX5XX/6XX/7XX
FIGURE 31-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11 SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SDOx MSb Bit 14 - - - - - -1 LSb
SP31 SP30
SDIx MSb In Bit 14 - - - -1 LSb In
SP40 SP41
TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Param.
No.
SP10 TSCL SCKx Output Low Time TSCK/2 — — ns
(Note 3)
SP11 TSCH SCKx Output High Time TSCK/2 — — ns
(Note 3)
SP20 TSCF SCKx Output Fall Time — — — ns See parameter DO32
(Note 4)
SP21 TSCR SCKx Output Rise Time — — — ns See parameter DO31
(Note 4)
SP30 TDOF SDOx Data Output Fall Time — — — ns See parameter DO32
(Note 4)
SP31 TDOR SDOx Data Output Rise Time — — — ns See parameter DO31
(Note 4)
SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V
TSCL2DOV SCKx Edge — — ns VDD < 2.7V
20
SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns
TDIV2SCL to SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns
TSCL2DIL to SCKx Edge
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.

PIC32MX5XX/6XX/7XX
FIGURE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11 SP10 SP21 SP20
SCKX
(CKP = 1)
SP35
SP20 SP21
SDOX MSb Bit 14 - - - - - -1 LSb
SP30,SP31
SDIX MSb In Bit 14 - - - -1 LSb In

SP40 SP41
TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Operating temperature -40°C  TA  +85°Cfor Industrial
Param.
Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions
No.
SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 — — ns
SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 — — ns
SP20 TSCF SCKx Output Fall Time (Note 4) — — — ns See parameter DO32
SP21 TSCR SCKx Output Rise Time (Note 4) — — — ns See parameter DO31
(Note 4)
(Note 4)
TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V
SP36 TDOV2SC, SDOx Data Output Setup to 15 — — ns
TDOV2SCL First SCKx Edge
SP40 TDIV2SCH, Setup Time of SDIx Data Input to 15 — — ns VDD > 2.7V
TDIV2SCL SCKx Edge 20 — — ns VDD < 2.7V
SP41 TSCH2DIL, Hold Time of SDIx Data Input 15 — — ns VDD > 2.7V
TSCL2DIL to SCKx Edge 20 — — ns VDD < 2.7V
and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.

PIC32MX5XX/6XX/7XX
FIGURE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP50 SP52
SCKX
(CKP = 0)
SP71 SP70
SP73 SP72
SCKX
(CKP = 1)
SP72 SP73
SP35
SDOX MSb Bit 14 - - - - - -1 LSb
SP30,SP31 SP51
SDIX MSb In Bit 14 - - - -1 LSb In

SP40 SP41
TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Param.
Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions
No.
SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 — — ns
SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 — — ns
SP72 TSCF SCKx Input Fall Time — — — ns See parameter DO32
SP73 TSCR SCKx Input Rise Time — — — ns See parameter DO31
SP30 TDOF SDOx Data Output Fall Time (Note 4) — — — ns See parameter DO32
SP31 TDOR SDOx Data Output Rise Time (Note 4) — — — ns See parameter DO31
SP50 TSSL2SCH, SSx  to SCKx  or SCKx Input 175 — — ns
TSSL2SCL
SP51 TSSH2DOZ SSx  to SDOx Output 5 — 25 ns
High-Impedance (Note 3)
SP52 TSCH2SSH SSx after SCKx Edge TSCK + 20 — — ns
TSCL2SSH
and are not tested.
3: The minimum clock period for SCKx is 40 ns.

PIC32MX5XX/6XX/7XX
FIGURE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP50 SP52
SCKx
(CKP = 0)
SP71 SP70 SP73 SP72
SCKx
(CKP = 1)
SP35
SP72 SP73
SDOx MSb Bit 14 - - - - - -1 LSb
SP30,SP31 SP51
SDIx
SDI
MSb In Bit 14 - - - -1 LSb In
SP40 SP41
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

Param.
No.
SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 — — ns
SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 — — ns
SP72 TSCF SCKx Input Fall Time — 5 10 ns
SP73 TSCR SCKx Input Rise Time — 5 10 ns
(Note 4)
(Note 4)
SP50 TSSL2SCH, SSx  to SCKx  or SCKx  Input 175 — — ns
TSSL2SCL
and are not tested.

PIC32MX5XX/6XX/7XX
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Param.
No.
SP51 TSSH2DOZ SSx  to SDOX Output 5 — 25 ns
High-Impedance
(Note 4)
SP52 TSCH2SSH SSx  after SCKx Edge TSCK + — — ns
TSCL2SSH 20
SP60 TSSL2DOV SDOx Data Output Valid after — — 25 ns
SSx Edge
and are not tested.

PIC32MX5XX/6XX/7XX
FIGURE 31-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Stop
Condition Condition
FIGURE 31-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20 IM11 IM21

IM10
SCLx
IM11 IM26
IM10 IM25 IM33
SDAx
In
IM40 IM40 IM45
SDAx
Out

PIC32MX5XX/6XX/7XX
TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Param.
Symbol Characteristics Min.(1) Max. Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) — s
400 kHz mode TPB * (BRG + 2) — s
1 MHz mode TPB * (BRG + 2) — s
(Note 2)
IM11 THI:SCL Clock High Time 100 kHz mode TPB * (BRG + 2) — s
400 kHz mode TPB * (BRG + 2) — s
(Note 2)
IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode — 100 ns
(Note 2)
IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
(Note 2)
IM25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode 100 — ns
(Note 2)
IM26 THD:DAT Data Input 100 kHz mode 0 — s
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode 0 0.3 s
(Note 2)
IM30 TSU:STA Start Condition 100 kHz mode TPB * (BRG + 2) — s Only relevant for
Setup Time 400 kHz mode TPB * (BRG + 2) — s Repeated Start
condition
(Note 2)
IM31 THD:STA Start Condition 100 kHz mode TPB * (BRG + 2) — s After this period, the
Hold Time 400 kHz mode TPB * (BRG + 2) — s first clock pulse is
generated
(Note 2)
IM33 TSU:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — s
Setup Time 400 kHz mode TPB * (BRG + 2) — s
(Note 2)
IM34 THD:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — ns
Hold Time 400 kHz mode TPB * (BRG + 2) — ns
1 MHz mode TPB * (BRG + 2) — ns
(Note 2)
Note 1: BRG is the value of the I2C™ Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC32MX5XX/6XX/7XX
TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Param.
Symbol Characteristics Min.(1) Max. Units Conditions
No.
IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns
From Clock 400 kHz mode — 1000 ns
(Note 2)
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s The amount of time the
400 kHz mode 1.3 — s bus must be free
before a new
1 MHz mode 0.5 — s
transmission can start
(Note 2)
IM50 CB Bus Capacitive Loading — 400 pF
Note 1: BRG is the value of the I2C™ Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC32MX5XX/6XX/7XX
FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
FIGURE 31-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20 IS11 IS21

IS10
SCLx
IS30 IS26
IS31 IS25 IS33
SDAx
In
IS40 IS40 IS45
SDAx
Out

PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Param.
Symbol Characteristics Min. Max. Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s PBCLK must operate at a
minimum of 800 kHz
400 kHz mode 1.3 — s PBCLK must operate at a
minimum of 3.2 MHz
(Note 1)
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s PBCLK must operate at a
minimum of 800 kHz
400 kHz mode 0.6 — s PBCLK must operate at a
minimum of 3.2 MHz
(Note 1)
IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
(Note 1)
IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
(Note 1)
IS25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode 100 — ns
(Note 1)
IS26 THD:DAT Data Input 100 kHz mode 0 — ns
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode 0 0.3 s
(Note 1)
IS30 TSU:STA Start Condition 100 kHz mode 4700 — s Only relevant for Repeated
Setup Time 400 kHz mode 600 — s Start condition
1 MHz mode 250 — s
(Note 1)
IS31 THD:STA Start Condition 100 kHz mode 4000 — s After this period, the first
Hold Time 400 kHz mode 600 — s clock pulse is generated
(Note 1)
IS33 TSU:STO Stop Condition 100 kHz mode 4000 — s
Setup Time 400 kHz mode 600 — s
(Note 1)
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Param.
Symbol Characteristics Min. Max. Units Conditions
No.
IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 — ns
1 MHz mode 250 ns
(Note 1)
IS40 TAA:SCL Output Valid From 100 kHz mode 0 3500 ns
Clock 400 kHz mode 0 1000 ns
1 MHz mode 0 350 ns
(Note 1)
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s The amount of time the bus
400 kHz mode 1.3 — s must be free before a new
transmission can start
(Note 1)
IS50 CB Bus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC32MX5XX/6XX/7XX
FIGURE 31-18: CAN MODULE I/O TIMING CHARACTERISTICS
CiTx Pin Old Value New Value

(output)
CA10 CA11
CiRx Pin
(input)
CA20
TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS

Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
CA10 TioF Port Output Fall Time — — — ns See parameter D032
CA11 TioR Port Output Rise Time — — — ns See parameter D031
CA20 Tcwf Pulse Width to Trigger 500 — — ns —
CAN Wake-up Filter
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.

PIC32MX5XX/6XX/7XX
TABLE 31-35: ETHERNET MODULE SPECIFICATIONS
Param.
Characteristic Min. Typical Max. Units Conditions
No.
Device Supply
ET20a Module VDD Supply 2.5 — 3.6 V
ET20b Module VDD Supply 2.7 — 3.6 V For RMII mode only
MIIM Timing Requirements
ET1 MDC Duty Cycle 40 — 60 %
ET2 MDC Period 400 — — ns
ET3 MDIO Output Delay 10 — 10 ns
ET4 MDIO Input Delay 0 — 300 ns
MII Timing Requirements
ET5 TX Clock Frequency — 25 — MHz
ET6 TX Clock Duty Cycle 35 — 65 %
ET7 ETXDx, ETEN, ETXERR 0 — 25 ns
Delay
ET8 RX Clock Frequency — 25 — MHz
ET9 RX Clock Duty Cycle 35 — 65 %
ET10 ERXDx, ERXDV, ERXERR 10 — 30 ns
Delay
RMII Timing Requirements
ET11 Reference Clock Frequency — 50 — MHz
ET12 Reference Clock Duty Cycle 35 — 65 %
ET13 ETXDx, ETEN, Delay 2 — 16 ns
ET14 ERXDx, ERXDV, ERXERR 2 — 16 ns
Delay

PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS
Param.
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of — Lesser of V
VDD – 0.3 VDD + 0.3
or 2.5 or 3.6
AD02 AVSS Module VSS Supply VSS — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 2.0 — AVDD V (Note 1)
AD05a 2.5 — 3.6 V VREFH = AVDD (Note 3)
AD06 VREFL Reference Voltage Low AVSS — VREFH – 2.0 V (Note 1)
AD07 VREF Absolute Reference 2.0 — AVDD V (Note 3)
Voltage (VREFH – VREFL)
AD08 IREF Current Drain — 250 400 A ADC operating
— 3 A ADC off
Analog Input
AD12 VINH-VINL Full-Scale Input Span VREFL — VREFH V
VINL Absolute VINL Input AVSS – 0.3 — AVDD/2 V
Voltage
VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V
Leakage Current — +/- 0.001 +/-0.610 A VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10 k
AD17 RIN Recommended — — 5K  (Note 1)
Impedance of Analog
Voltage Source
ADC Accuracy – Measurements with External VREF+/VREF-
AD20c Nr Resolution 10 data bits bits
AD21c INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL Differential Nonlinearity > -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
(Note 2)
AD23c GERR Gain Error > -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD24n EOFF Offset Error > -1 — <1 LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c — Monotonicity — — — — Guaranteed
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sinewave.

PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS (CONTINUED)
Param.
No.
ADC Accuracy – Measurements with Internal VREF+/VREF-
AD20d Nr Resolution 10 data bits bits (Note 3)
AD21d INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD22d DNL Differential Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Notes 2, 3)
AD23d GERR Gain Error > -4 — <4 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD24d EOFF Offset Error > -2 — <2 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD25d — Monotonicity — — — — Guaranteed
Dynamic Performance
AD31b SINAD Signal to Noise and 55 58.5 — dB (Notes 3, 4)
Distortion
AD34b ENOB Effective Number of Bits 9.0 9.5 — bits (Notes 3, 4)
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
4: Characterized with a 1 kHz sinewave.

PIC32MX5XX/6XX/7XX
TABLE 31-37: 10-BIT CONVERSION RATE PARAMETERS
PIC32MX 10-Bit A/D Converter Conversion Rates(2)
TAD Sampling
ADC Speed RS Max VDD Temperature ADC Channels Configuration
Minimum Time Min
1 Msps to 65 ns 132 ns 500 3.0V to -40°C to
400 ksps(1) 3.6V +85°C
VREF- VREF+
CHX
ANx
SHA ADC
Up to 400 ksps 200 ns 200 ns 5.0 k 2.5V to -40°C to

3.6V +85°C VREF- VREF+
or or
AVSS AVDD
ANx CHX
SHA ADC
ANx or VREF-
Up to 300 ksps 200 ns 200 ns 5.0 k 2.5V to -40°C to

3.6V +85°C VREF- VREF+
or or
AVSS AVDD
ANx CHX
SHA ADC
ANx or VREF-
Note 1: External VREF- and VREF+ pins must be used for correct operation.

PIC32MX5XX/6XX/7XX
TABLE 31-38: A/D CONVERSION TIMING REQUIREMENTS
Param.
No.
Clock Parameters
AD50 TAD A/D Clock Period(2) 65 — — ns See Table 31-37
Conversion Rate
AD55 TCONV Conversion Time — 12 TAD — —
AD56 FCNV Throughput Rate — — 1000 ksps AVDD = 3.0V to 3.6V
(Sampling Speed) — — 400 ksps AVDD = 2.5V to 3.6V
AD57 TSAMP Sample Time 1 — 31 TAD TSAMP must be  132 ns
Timing Parameters
AD60 TPCS Conversion Start from Sample — 1.0 TAD — — Auto-Convert Trigger
Trigger(3) (SSRC<2:0> = 111)
not selected
AD61 TPSS Sample Start from Setting 0.5 TAD — 1.5 TAD —
Sample (SAMP) bit
AD62 TCSS Conversion Completion to — 0.5 TAD — —
Sample Start (ASAM = 1)(3)
AD63 TDPU Time to Stabilize Analog Stage — — 2 s
from A/D Off to A/D On(3)
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3: Characterized by design but not tested.

PIC32MX5XX/6XX/7XX
FIGURE 31-19: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution Set SAMP Clear SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
TSAMP AD55 AD55
CONV
ADxIF
Buffer(0)
Buffer(1)
1 2 3 4 5 6 7 8 5 6 7 8
1 – Software sets ADxCON. SAMP to start sampling.

2 – Sampling starts after discharge period. TSAMP is described in the “PIC32MX Family Reference Manual” (DS61132).
3 – Software clears ADxCON. SAMP to start conversion.

4 – Sampling ends, conversion sequence starts.
5 – Convert bit 9.
8 – One TAD for end of conversion.

PIC32MX5XX/6XX/7XX
FIGURE 31-20: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Execution Set ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP TSAMP
AD55 AD55 TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1 2 3 4 5 6 7 3 4 5 6 8 3 4
1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0.
2 – Sampling starts after discharge period. 6 – One TAD for end of conversion.
TSAMP is described in the “PIC32MX
Family Reference Manual” (DS61132). 7 – Begin conversion of next channel.
3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>.

PIC32MX5XX/6XX/7XX
FIGURE 31-21: PARALLEL SLAVE PORT TIMING
CS
PS5
RD
PS6
WR
PS4 PS7
PMD<7:0>
PS1
PS3
PS2
TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS

Param.
No.
PS1 TdtV2wrH Data In Valid before WR or CS Inactive 20 — — ns
(setup time)
PS2 TwrH2dtI WR or CS Inactive to Data–In Invalid 40 — — ns
(hold time)
PS3 TrdL2dtV RD and CS Active to Data–Out Valid — — 60 ns
PS4 TrdH2dtI RD Activeor CS Inactive to Data–Out 0 — 10 ns
Invalid
PS5 Tcs CS Active Time TPB + 40 — — ns
PS6 TWR WR Active Time TPB + 25 — — ns
PS7 TRD RD Active Time TPB + 25 — — ns

PIC32MX5XX/6XX/7XX
FIGURE 31-22: PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PM4
PMA<13:18> Address
PM6
PMD<7:0> Address<7:0>
Address<7:0> Data
Data
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS

Param.
No.
PM1 TLAT PMALL/PMALH Pulse Width — 1 TPB — —
PM2 TADSU Address Out Valid to PMALL/PMALH — 2 TPB — —
Invalid (address setup time)
PM3 TADHOLD PMALL/PMALH Invalid to Address Out — 1 TPB — —
Invalid (address hold time)
PM4 TAHOLD PMRD Inactive to Address Out Invalid 5 — — ns
(address hold time)
PM5 TRD PMRD Pulse Width — 1 TPB — —
PM6 TDSU PMRD or PMENB Active to Data In 15 — — ns
Valid (data setup time)
PM7 TDHOLD PMRD or PMENB Inactive to Data In — 80 — ns
Invalid (data hold time)

PIC32MX5XX/6XX/7XX
FIGURE 31-23: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PMA<13:18> Address
PM2 + PM3
PMD<7:0> Address<7:0> Data
PM12
PM13
PMRD
PM11
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS

Param.
No.
PM11 TWR PMWR Pulse Width — 1 TPB — —
PM12 TDVSU Data Out Valid before PMWR or — 2 TPB — —
PMENB goes Inactive (data setup time)
PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out — 1 TPB — —
Invalid (data hold time)

PIC32MX5XX/6XX/7XX
TABLE 31-42: OTG ELECTRICAL SPECIFICATIONS
Param.
No.
USB313 VUSB USB Voltage 3.0 — 3.6 V Voltage on bus must
be in this range for
proper USB operation
USB315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V
USB316 VIHUSB Input High Voltage for USB Buffer 2.0 — — V
USB318 VDIFS Differential Input Sensitivity — — 0.2 V
USB319 VCM Differential Common Mode Range 0.8 — 2.5 V The difference
between D+ and D-
must exceed this value
while VCM is met
USB320 ZOUT Driver Output Impedance 28.0 — 44.0 
USB321 VOL Voltage Output Low 0.0 — 0.3 V 14.25 k load
connected to 3.6V
USB322 VOH Voltage Output High 2.8 — 3.6 V 14.25 k load
connected to ground

PIC32MX5XX/6XX/7XX
FIGURE 31-24: EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold Trf

Trf
TDO
TRST*
TTRST*low
TTDOout TTDOzstate
Defined Undefined
Trf
TABLE 31-43: EJTAG TIMING REQUIREMENTS

Param.
Symbol Description(1) Min. Max. Units Conditions
No.
EJ1 TTCKCYC TCK Cycle Time 25 — ns
EJ2 TTCKHIGH TCK High Time 10 — ns
EJ3 TTCKLOW TCK Low Time 10 — ns
EJ4 TTSETUP TAP Signals Setup Time Before 5 — ns
Rising TCK
EJ5 TTHOLD TAP Signals Hold Time After 3 — ns
Rising TCK
EJ6 TTDOOUT TDO Output Delay Time From — 5 ns
Falling TCK
EJ7 TTDOZSTATE TDO 3-State Delay Time From — 5 ns
Falling TCK
EJ8 TTRSTLOW TRST Low Time 25 — ns
EJ9 TRF TAP Signals Rise/Fall Time, All — — ns
Input and Output

PIC32MX5XX/6XX/7XX
32.0 PACKAGING INFORMATION
32.1 Package Marking Information
64-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX PIC32MX575F
XXXXXXXXXX 512H-80I/PT
XXXXXXXXXX e3
YYWWNNN 0510017
XXXXXXXXXXXX PIC32MX575F
XXXXXXXXXXXX 512L-80I/PF e3
YYWWNNN 0510017
XXXXXXXXXXXX PIC32MX575F
XXXXXXXXXXXX 512L-80I/PT e3
YYWWNNN 0510017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e) 3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

PIC32MX5XX/6XX/7XX
32.1 Package Marking Information (Continued)
64-Lead QFN (9x9x0.9 mm) Example
XXXXXXXXXX 512H-80I/MR
XXXXXXXXXX e3
YYWWNNN 0510017
121-Lead XBGA (10x10x1.1 mm) Example
XXXXXXXXXX 512H-80I/BG
XXXXXXXXXX e3
YYWWNNN 0510017

PIC32MX5XX/6XX/7XX
32.2 Package Details
The following sections give the technical details of the packages.

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

PIC32MX5XX/6XX/7XX

PIC32MX5XX/6XX/7XX

PIC32MX5XX/6XX/7XX

PIC32MX5XX/6XX/7XX

PIC32MX5XX/6XX/7XX

PIC32MX5XX/6XX/7XX
APPENDIX A: MIGRATING FROM A.3 Pin Assignments
PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX devices have the same pin
PIC32MX5XX/6XX/7XX assignment for peripherals as PIC32MX4XX devices
DEVICES with the following exceptions:
• Pins associated with the UART1 and UART2
This appendix provides an overview of considerations
modules on PIC32MX4XX devices are now
for migrating from PIC32MX3XX/4XX devices to the
associated with the UART1A and UART3A
PIC32MX5XX/6XX/7XX family of devices. The code
modules, respectively on PIC32MX5XX/6XX/7XX
developed for the PIC32MX3XX/4XX devices can be
devices
ported to the PIC32MX5XX/6XX/7XX devices after
making the appropriate changes outlined below. • Pins associated with the SPI2 module on
PIC32MX4XX devices are now associated with
the SPI2A module on PIC32MX5XX/6XX/7XX
A.1 DMA devices
PIC32MX5XX/6XX/7XX devices do not support
stopping DMA transfers in Idle mode.
A.2 Interrupts
PIC32MX5XX/6XX/7XX devices have persistent inter-
rupts for some of the peripheral modules. This means
that the interrupt condition for these peripherals must
be cleared before the interrupt flag can be cleared.
For example, to clear a UART receive interrupt, the
user application must first read the UART Receive reg-
ister to clear the interrupt condition and then clear the
associated UxIF flag to clear the pending UART inter-
rupt. In other words, the UxIF flag cannot be cleared by
software until the UART Receive register is read.
Table A-1 outlines the peripherals and associated
interrupts that are implemented differently on
PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX
devices.
In addition, on the SPI module, the IRQ numbers for the
receive done interrupts were changed from 25 to 24
and the transfer done interrupts were changed from 24
to 25.
TABLE A-1: PIC32MX3XX/4XX vs. PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION

DIFFERENCES
Module Interrupt Implementation
Input Capture To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of
capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
SPI Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF
register to obtain the number of data to receive/transmit below the level specified by the
SRXISEL<1:0> and STXISEL<1:0> bits.
UART TX interrupt will be generated as soon as the UART module is enabled.
Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or
UxTXREG registers to obtain the number of data to receive/transmit below the level specified by
the URXISEL<1:0> and UTXISEL<1:0> bits.
ADC All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
PMP To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)
register.

PIC32MX5XX/6XX/7XX
APPENDIX B: REVISION HISTORY Revision B (November 2009)
The revision includes the following global update:
Revision A (August 2009)
• Added Note 2 to the shaded table that appears at
This is the initial revision of this document. the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
Other major changes are referenced by their respective
chapter/section in Table B-1.
TABLE B-1: MAJOR SECTION UPDATES

Section Name Update Description
“High-Performance, USB, CAN and Added the following devices:
Ethernet 32-Bit Flash - PIC32MX575F256L
Microcontrollers”
- PIC32MX695F512L
- PIC32MX695F512H
The 100-pin TQFP pin diagrams have been updated to reflect the current pin
name locations (see the “Pin Diagrams” section).
Added the 121-pin Ball Grid Array (XBGA) pin diagram.
Updated Table 1: “PIC32MX Features”
Added the following tables:
- Table 2: “Pin Names: PIC32MX575F256L and PIC32MX575F512L
Devices”,
- Table 3: “Pin Names: PIC32MX675F256L, PIC32MX675F512L and
PIC32MX695F512L Devices”
- Table 4: “Pin Names: PIC32MX775F256L, PIC32MX775F512L,
PIC32MX795F512L and Devices”
Updated the following pins as 5V tolerant:
- 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2)
Section 2.0 “Guidelines for Getting Removed the last sentence of Section 2.3.1 “Internal Regulator Mode”.
Started with 32-Bit Removed Section 2.3.2 “External Regulator Mode”
Microcontrollers”

PIC32MX5XX/6XX/7XX
TABLE B-1: MAJOR SECTION UPDATES (CONTINUED)
Section 4.0 “Memory Updated all register tables to include the Virtual Address and All Resets
Organization” columns.
Updated the title of Figure 4-1 to include the PIC32MX575F256L device.
Updated the title of Figure 4-3 to include the PIC32MX695F512L and
PIC32MX695F512H devices. Also changed PIC32MX795F512L to
PIC32MX795F512H.
Updated the title of Table 4-3 to include the PIC32MX695F512H device.
Updated the title of Table 4-5 to include the PIC32MX575F5256L device.
Reversed the order of Table 4-11 and Table 4-12.
Reversed the order of Table 4-14 and Table 4-15.
Updated the title of Table 4-15 to include the PIC32MX575F256L and
PIC32MX695F512L devices.
Updated the title of Table 4-47 to include the PIC32MX695F512H and
PIC32MX695F512L devices.
Section 12.0 “I/O Ports” Updated the second paragraph of Section 12.1.2 “Digital Inputs” and
removed Table 12-1.
Section 22.0 “10-Bit Analog-to- Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2).
Digital Converter (ADC)”
Section 28.0 “Special Features” Removed references to the ENVREG pin in Section 28.3 “On-Chip Voltage
Regulator”.
Updated the first sentence of Section 28.3.1 “On-Chip Regulator and
POR” and Section 28.3.2 “On-Chip Regulator and BOR”.
Updated the Connections for the On-Chip Regulator (see Figure 28-2).
Section 31.0 “Electrical Updated the Absolute Maximum Ratings and added Note 3.
Characteristics” Added Thermal Packaging Characteristics for the 121-pin XBGA package
(see Table 31-3).
Updated the Operating Current (IDD) DC Characteristics (see Table 31-5).
Updated the Idle Current (IIDLE) DC Characteristics (see Table 31-6).
Updated the Power-Down Current (IPD) DC Characteristics (see Table 31-7).
Removed Note 1 from the Program Flash Memory Wait State Characteristics
(see Table 31-11).
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics,
changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see
Figure 31-13).
Section 32.0 “Packaging Added the 121-pin XBGA package marking information and package details.
Information”
“Product Identification System” Added the definition for BG (121-lead 10x10x1.1 mm, XBGA).
Added the definition for Speed.

PIC32MX5XX/6XX/7XX
Revision C (February 2010)
The revision includes the following updates, as
described in Table B-2:
TABLE B-2: MAJOR SECTION UPDATES

“High-Performance, USB, CAN Added the following devices:
and Ethernet 32-Bit Flash • PIC32MX675F256H
Microcontrollers”
• PIC32MX775F256H
• PIC32MX775F512H
• PIC32MX675F256L
• PIC32MX775F256L
• PIC32MX775F512L
Added the following pins:
• EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV
Added the EREFCLK and ECRSDV pins to Table 3 and Table 4.
Section 1.0 “Device Overview” Updated the pin number pinout I/O descriptions for the following pin names in
Table 1-1:
• SCL1A • TMS • C1IN-

• SDA1A • TCK • C1IN+
• SCL2 • TDI • C1OUT
• SDA2 • TDO • C2IN-
• SCL2A • RTCC • C2IN+
• SDA2A • CVREF- • C2OUT
• SCL3A • CVREF+ • PMA0
• SDA3A • CVREFOUT • PMA1
Added the following pins to the Pinout I/O Descriptions table (Table 1-1):
• EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV

PIC32MX5XX/6XX/7XX
TABLE B-2: MAJOR SECTION UPDATES (CONTINUED)
Section 4.0 “Memory Added new devices and updated the virtual and physical memory map values in
Organization” Figure 4-1.
Added new devices to Figure 4-2.
Added new devices to the following register maps:
• Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps)
• Table 4-12 (I2C2 Register Map)
• Table 4-15 (SPI1 Register Map)
• Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps)
• Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps)
• Table 4-45 (CAN1 Register Map)
• Table 4-46 (CAN2 Register Map)
• Table 4-47 (Ethernet Controller Register Map)
Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device
Configuration Word Summary).
Section 28.0 “Special Changed all references of POSCMD to POSCMOD in the Device Configuration
Features” Word 1 register (see Register 28-2).
Appendix A: “Migrating from Added the new section A.3 “Pin Assignments”.
PIC32MX3XX/4XX to
PIC32MX5XX/6XX/7XX
Devices”

PIC32MX5XX/6XX/7XX
NOTES:

PIC32MX5XX/6XX/7XX
INDEX
A D
AC Characteristics ............................................................ 180 DC Characteristics............................................................ 172
10-Bit Conversion Rate Parameters ......................... 204 I/O Pin Input Specifications ...................................... 176
A/D Conversion Requirements ................................. 205 I/O Pin Output Specifications.................................... 177
ADC Specifications ................................................... 202 Idle Current (IIDLE) .................................................... 174
EJTAG Timing Requirements ................................... 212 Operating Current (IDD) ............................................ 173
Ethernet .................................................................... 201 Power-Down Current (IPD)........................................ 175
Internal FRC Accuracy.............................................. 182 Program Memory...................................................... 177
Internal RC Accuracy ................................................ 182 Temperature and Voltage Specifications.................. 172
OTG Electrical Specifications ................................... 211 Development Support ....................................................... 167
Parallel Master Port Read Requirements ................. 209 Direct Memory Access (DMA) Controller.......................... 117
Parallel Master Port Write ......................................... 210
Parallel Master Port Write Requirements.................. 210 E
Parallel Slave Port Requirements ............................. 208 Electrical Characteristics .................................................. 171
PLL Clock Timing...................................................... 182 AC............................................................................. 180
Assembler Errata .................................................................................. 21
MPASM Assembler................................................... 168 Ethernet Controller............................................................ 145
External Clock
B Timer1 Timing Requirements ................................... 186
Block Diagrams Timer2, 3, 4, 5 Timing Requirements ....................... 187
A/D Module ............................................................... 141 Timing Requirements ............................................... 181
Comparator I/O Operating Modes............................. 147
Comparator Voltage Reference ................................ 149 F
Connections for On-Chip Voltage Regulator............. 162 Flash Program Memory .................................................... 105
Core and Peripheral Modules ..................................... 23 RTSP Operation ....................................................... 105
DMA .......................................................................... 117
Ethernet Controller.................................................... 145
I
I2C Circuit ................................................................. 134 I/O Ports ........................................................................... 121
Input Capture ............................................................ 127 Parallel I/O (PIO) ...................................................... 122
Interrupt Controller .................................................... 109 Instruction Set................................................................... 165
JTAG Programming, Debugging and Inter-Integrated Circuit (I2C .............................................. 133
Trace Ports ....................................................... 163 Internal Voltage Reference Specifications........................ 179
MCU............................................................................ 39 Interrupt Controller............................................................ 109
Output Compare Module........................................... 129 IRG, Vector and Bit Location .................................... 110
PIC32MX CAN Module ............................................. 143
M
PMP Pinout and Connections to External
Devices ............................................................. 137 MCU
Prefetch Module........................................................ 115 Architecture Overview ................................................ 40
Reset System............................................................ 107 Coprocessor 0 Registers ............................................ 42
RTCC ........................................................................ 139 Core Exception Types ................................................ 43
SPI Module ............................................................... 131 EJTAG Debug Support............................................... 44
Timer1....................................................................... 123 Power Management ................................................... 44
Timer2/3/4/5 (16-Bit) ................................................. 125 MCU Module....................................................................... 39
Typical Multiplexed Port Structure ............................ 121 Memory Maps ............................................................... 46–48
UART ........................................................................ 135 Memory Organization ......................................................... 45
WDT and Power-up Timer ........................................ 161 Layout......................................................................... 45
Brown-out Reset (BOR) Migration
and On-Chip Voltage Regulator................................ 162 PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 227
MPLAB ASM30 Assembler, Linker, Librarian ................... 168
C MPLAB Integrated Development
C Compilers Environment Software .............................................. 167
MPLAB C18 .............................................................. 168 MPLAB PM3 Device Programmer .................................... 170
Clock Diagram .................................................................. 113 MPLAB REAL ICE In-Circuit Emulator System ................ 169
Comparator MPLINK Object Linker/MPLIB Object Librarian ................ 168
Specifications............................................................ 178
O
Comparator Module .......................................................... 147
Comparator Voltage Reference (CVREF ........................... 149 Open-Drain Configuration................................................. 122
Configuration Bit ............................................................... 153 Oscillator Configuration .................................................... 113
Controller Area Network (CAN)......................................... 143 Output Compare ............................................................... 129
CPU Module........................................................................ 35

PIC32MX5XX/6XX/7XX
P Timing Requirements
Packaging ......................................................................... 213 CLKO and I/O ........................................................... 183
Details ....................................................................... 215 Timing Specifications
CAN I/O Requirements ............................................. 200
Marking ..................................................................... 213
Parallel Master Port (PMP) ............................................... 137 I2Cx Bus Data Requirements (Master Mode)........... 195
PIC32MX Family USB Interface Diagram ......................... 120 I2Cx Bus Data Requirements (Slave Mode)............. 198
Input Capture Requirements..................................... 187
Pinout I/O Descriptions (table) ............................................ 24
Power-on Reset (POR) Output Compare Requirements................................ 188
and On-Chip Voltage Regulator ................................ 162 Simple OCx/PWM Mode Requirements ................... 188
SPIx Master Mode (CKE = 0) Requirements............ 189
Power-Saving Features..................................................... 151
CPU Halted Methods ................................................ 151 SPIx Master Mode (CKE = 1) Requirements............ 190
Operation .................................................................. 151 SPIx Slave Mode (CKE = 1) Requirements.............. 192
SPIx Slave Mode Requirements (CKE = 0).............. 191
with CPU Running..................................................... 151
Prefetch Cache ................................................................. 115 U
Program Flash Memory
UART ................................................................................ 135
Wait State Characteristics......................................... 178
USB On-The-Go (OTG) .................................................... 119
R
V
Real-Time Clock and Calendar (RTCC)............................ 139
VCAP/VDDCORE pin............................................................ 162
Register Maps ............................................................. 49–103
Voltage Reference Specifications..................................... 179
Registers
Voltage Regulator (On-Chip) ............................................ 162
DDPCON (Debug Data Port Control)........................ 164
DEVCFG0 (Device Configuration Word 0 ................. 153 W
DEVCFG1 (Device Configuration Word 1 ................. 155 Watchdog Timer (WDT).................................................... 161
DEVCFG2 (Device Configuration Word 2 ................. 157
WWW, On-Line Support ..................................................... 21
DEVCFG3 (Device Configuration Word 3 ................. 159
DEVID (Device and Revision ID) .............................. 160
Resets ............................................................................... 107
Revision History ................................................................ 228
S
Serial Peripheral Interface (SPI) ....................................... 131
Software Simulator (MPLAB SIM)..................................... 169
Special Features ............................................................... 153
T
Timer1 Module .................................................................. 123
Timer2/3, Timer4/5 Modules ............................................. 125
Timing Diagrams
10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) .................................. 206
10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 1, SSRC = 111, SAMC = 00001)........ 207
CAN I/O..................................................................... 200
EJTAG ...................................................................... 212
External Clock ........................................................... 180
I/O Characteristics .................................................... 183
I2Cx Bus Data (Master Mode) .................................. 194
I2Cx Bus Data (Slave Mode) .................................... 197
I2Cx Bus Start/Stop Bits (Master Mode) ................... 194
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 197
Input Capture (CAPx)................................................ 187
OCx/PWM ................................................................. 188
Output Compare (OCx) ............................................. 188
Parallel Master Port Read ......................................... 209
Parallel Master Port Write ......................................... 210
Parallel Slave Port .................................................... 208
SPIx Master Mode (CKE = 0).................................... 189
SPIx Master Mode (CKE = 1).................................... 190
SPIx Slave Mode (CKE = 0)...................................... 191
SPIx Slave Mode (CKE = 1)...................................... 192
Timer1, 2, 3, 4, 5 External Clock............................... 186
UART Reception ....................................................... 136
UART Transmission (8-Bit or 9-Bit Data) .................. 136

PIC32MX5XX/6XX/7XX
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Example:

PIC32MX575F256H-80I/PT:
Microchip Brand General purpose PIC32MX,
Architecture 256 KB program memory,
64-pin, Industrial temperature,
Product Groups TQFP package.
Flash Memory Family
Program Memory Size (KB)
Pin Count
Tape and Reel Flag (if applicable)
Speed
Temperature Range
Package
Pattern
Flash Memory Family

Architecture MX = 32-bit RISC MCU core
Product Groups 5XX = General purpose microcontroller family

6XX = General purpose microcontroller family
7XX = General purpose microcontroller family
Flash Memory Family F = Flash program memory
Program Memory Size 256 = 256K

512 = 512K
Pin Count H = 64-pin

L = 100-pin
Speed 80 = 80 MHz
Temperature Range I = -40°C to +85°C (Industrial)
Package PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)

PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
BG = 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array)
Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)

ES = Engineering Sample

WORLDWIDE SALES AND SERVICE
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Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://support.microchip.com Fax: 852-2401-3431
India - Pune France - Paris
Web Address:
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
www.microchip.com
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
Atlanta Fax: 61-2-9868-6755
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Tel: 678-957-9614 Tel: 81-45-471- 6166
Tel: 86-10-8528-2100 Fax: 49-89-627-144-44
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Fax: 86-10-8528-2104 Italy - Milan
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Tel: 86-28-8665-5511 Fax: 39-0331-466781
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Cleveland
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Tel: 216-447-0464 China - Nanjing Tel: 44-118-921-5869
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Fax: 216-447-0643 Tel: 86-25-8473-2460 Fax: 44-118-921-5820
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Fax: 248-538-2260
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Kokomo Tel: 86-24-2334-2829 Tel: 886-3-6578-300
Kokomo, IN Fax: 86-24-2334-2393 Fax: 886-3-6578-370
Tel: 765-864-8360
Fax: 765-864-8387 China - Shenzhen Taiwan - Kaohsiung
Tel: 86-755-8203-2660 Tel: 886-7-536-4818
Los Angeles Fax: 86-755-8203-1760 Fax: 886-7-536-4803
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Fax: 949-462-9608 Tel: 86-27-5980-5300 Tel: 886-2-2500-6610
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Canada Fax: 86-592-2388130
Tel: 905-673-0699 China - Zhuhai
Fax: 905-673-6509 Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10

PIC32MX5XX/6XX/7XX Family Data Sheet: High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

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PIC32MX5XX/6XX/7XX

Family Data Sheet

 2010 Microchip Technology Inc. Preliminary DS61156C

Information contained in this publication regarding device Trademarks

DS61156C-page 2 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 3

10-Bit 1 Msps ADC

DS61156C-page 4 Preliminary  2010 Microchip Technology Inc.

64-Pin QFN = Pins are up to 5V tolerant

 2010 Microchip Technology Inc. Preliminary DS61156C-page 5

VSS 9 PIC32MX675F512H 40 OSC2/CLKO/RC15

VDD 10 PIC32MX695F512H 39 OSC1/CLKI/RC12

DS61156C-page 6 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 7

64-Pin TQFP = Pins are up to 5V tolerant

DS61156C-page 8 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 9

DS61156C-page 10 Preliminary  2010 Microchip Technology Inc.

100-Pin TQFP = Pins are up to 5V tolerant

 2010 Microchip Technology Inc. Preliminary DS61156C-page 11

121-Pin XBGA(1) = Pins are up to 5V tolerant

DS61156C-page 14 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 15

DS61156C-page 16 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 17

DS61156C-page 18 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 19

DS61156C-page 20 Preliminary  2010 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

 2010 Microchip Technology Inc. Preliminary DS61156C-page 21

DS61156C-page 22 Preliminary  2010 Microchip Technology Inc.

FIGURE 1-1: BLOCK DIAGRAM(1,2)

Peripheral Bus Clocked by SYSCLK

Peripheral Bus Clocked by PBCLK

MIPS32® M4K™ IC1-5

PORTF 10-Bit ADC

PORTG Program Flash Memory RTCC

 2010 Microchip Technology Inc. Preliminary DS61156C-page 23

DS61156C-page 24 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 25

DS61156C-page 26 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 27

DS61156C-page 28 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 29

DS61156C-page 30 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 31

DS61156C-page 32 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 33

DS61156C-page 34 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 35

2.3 Capacitor on Internal Voltage

DS61156C-page 36 Preliminary  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Preliminary DS61156C-page 37

DS61156C-page 38 Preliminary  2010 Microchip Technology Inc.

FIGURE 3-1: MCU BLOCK DIAGRAM