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    Activity 3: The or Gate Objective:: A B (A) Y A+B

    Uploaded by

    Christian Allan Lumakin
    1) The document describes a laboratory activity to demonstrate and simulate the basic function of an OR gate and its application using an OR gate IC. 2) The student is asked to construct an OR gate circuit using an IC, resistors, LEDs, and a power supply. Various input combinations are tested and the outputs are recorded. 3) Key observations include that the output of an OR gate is 1 if any input is 1, and only 0 if all inputs are 0. Tying inputs together results in the same output. A 3-input OR gate is also demonstrated.

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    © All Rights Reserved
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    Activity 3: The or Gate Objective:: A B (A) Y A+B

    Uploaded by

    Christian Allan Lumakin
    93 views3 pages
    1) The document describes a laboratory activity to demonstrate and simulate the basic function of an OR gate and its application using an OR gate IC. 2) The student is asked to construct an OR gate circuit using an IC, resistors, LEDs, and a power supply. Various input combinations are tested and the outputs are recorded. 3) Key observations include that the output of an OR gate is 1 if any input is 1, and only 0 if all inputs are 0. Tying inputs together results in the same output. A 3-input OR gate is also demonstrated.

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    Original Title

    OR GATE

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    1) The document describes a laboratory activity to demonstrate and simulate the basic function of an OR gate and its application using an OR gate IC. 2) The student is asked to construct an OR gate circuit using an IC, resistors, LEDs, and a power supply. Various input combinations are tested and the outputs are recorded. 3) Key observations include that the output of an OR gate is 1 if any input is 1, and only 0 if all inputs are 0. Tying inputs together results in the same output. A 3-input OR gate is also demonstrated.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    93 views3 pages

    Activity 3: The or Gate Objective:: A B (A) Y A+B

    Uploaded by

    Christian Allan Lumakin
    1) The document describes a laboratory activity to demonstrate and simulate the basic function of an OR gate and its application using an OR gate IC. 2) The student is asked to construct an OR gate circuit using an IC, resistors, LEDs, and a power supply. Various input combinations are tested and the outputs are recorded. 3) Key observations include that the output of an OR gate is 1 if any input is 1, and only 0 if all inputs are 0. Tying inputs together results in the same output. A 3-input OR gate is also demonstrated.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 3

    MINDANAO STATE UNIVERSITY

    ILIGAN INSTITUTE OF TECHNOLOGY


    COLLEGE OF ENGINEERING AND TECHNOLOGY
    DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING AND TECHNOLOGY

    NAME: Christian Allan G. Lumakin YEAR AND COURSE: BS-EsE 3


    INSTRUCTOR: ENGR. KRESIL JOY P. JIMENEZ 1st Semester S.Y. 2021-2022

    EEE 180.1 LABORATORY ACTIVITY


    ACTIVITY 3: THE OR GATE

    Objective:

    To demonstrate and simulate the basic function of OR gate and its application.

    Material Needed:

    1 unit 5V Power Supply Hook-up Wires (AWG #22)


    1 pc 74LS32 IC 6 pcs 2kΩ ¼-watt Resistors
    Breadboard 6 pcs LEDs

    Introduction:

    The OR gate is a logic gate that produces high (logic “1”) output when at least one (1) of
    its input is at high (logic “1”). The symbol, truth table, and the pin configuration of the
    OR gate IC are illustrated in Figure 4-1.

    input
    A output

    B Y = A+B
    (a)

    input output
    A B Y
    0 0 0
    0 1 1
    1 0 1
    1 1 1
    (b) (c)
    Figure 4-1. The OR gate (a) logic symbol, (b) truth table, and (c) 74LS32 IC pin configuration.

    Procedures:

    1. Construct the circuit shown in Figure 4-2. Make sure that all the positions of Data
    Switches are in logic LO. Remember to connect the supply of the IC.
    Video File: double click

    Figure 4-2. Example of an OR gate circuit configuration.

    2. Set all Data Switches (D0 – D2) to logic “0” or LO. What happen to the LED indicators?
    When all data switches to logic 0 then all LED indicators are also logic “0” and is turned off.

    3. Fill-up the equivalent output of the given input in the table below.

    INPUT OUTPUT
    D0 D1 D2 L1 L2 L3 L4 L5 L6
    0 0 0 0 0 0 0 0 0
    0 0 1 0 0 1 0 0 1
    0 1 0 0 1 0 1 1 1
    0 1 1 0 1 1 1 1 1
    1 0 0 1 0 0 1 1 1
    1 0 1 1 0 1 1 1 1
    1 1 0 1 1 0 1 1 1
    1 1 1 1 1 1 1 1 1

    Based on the above table, what did you observe from the result data?
    Based on the table above, I have observed that there is a pattern from L1, L2, and, L3 and its output is taken
    before the logic gates. In L4 and L5, it has the same output but and the only different among them is the L6.

    4. Again, fill-up the table below to verify the OR gate truth table using D0 and D1 as input.
    The output signal can be monitored in the LED indicators L1, L2, L4, and L5.

    INPUT OUTPUT
    D0 D1 L1 L2 L4 L5
    0 0 0 0 0 0
    0 1 0 1 1 1
    1 0 1 0 1 1
    1 1 1 1 1 1

    5. Notice that the input of OR gate B are tied together. What did you observe on the behavior of
    gate based on the result from L4 and L5?
    Since the input of OR gate B are tied together, I have observed that the behavior of gate based on the result from L4 and L5
    is that the output of L4 should be the same for L5 since the OR gate only becomes logic 0 when both inputs are 0. This means
    that the behavior of gate is normally functioning.

    6. The second group of gate is composed of gates C and D. Note in the figure that it will form a 3 –
    input OR gate. Fill up the result in the table below.

    INPUT OUTPUT
    D0 D1 D2 L1 L2 L3 L6
    0 0 0 0 0 0 0
    0 0 1 0 0 1 1
    0 1 0 0 1 0 1
    0 1 1 0 1 1 1
    1 0 0 1 0 0 1
    1 0 1 1 0 1 1
    1 1 0 1 1 0 1
    1 1 1 1 1 1 1

    Based from the above table, what did you observe from the result data? Observed the result of
    L1, L2, and L3 and compare the inputs D0, D1, and D2.
    Based from the table above, I have observed from the result data that it is the same with the 3 rd procedure but it is like
    a big OR gate. The results of L1, L2, and L3 and the inputs D0, D1, and D2 are the same. This means that the OR gate
    was not applied up until the L6 output.

    Observation:
    If the delay of each gate in Figure 4-2 is 15 ns, draw the signal waveform as indicated.

    Conclusion:

    In conclusion, I have learned that if the OR gate C is removed but the inputs are still
    connected to the OR gate D, the result would be the same. Also in OR gate, the result will only be
    logic “0” if all the inputs are logic “0”.

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