96 KHZ Digital Audio Receiver: Cs8413 Cs8414
96 KHZ Digital Audio Receiver: Cs8413 Cs8414
96 KHZ Digital Audio Receiver: Cs8413 Cs8414
CS8414
96 kHz Digital Audio Receiver
Features Description
l Sample Rates to >100 kHz The CS8413 and CS8414 are monolithic CMOS devices
l Low-Jitter, On-Chip Clock Recovery which receive and decode audio data up to 96kHz ac-
cording to the AES/EBU, IEC958, S/PDIF, and EIAJ
256xFs Output clock Provided CP340/1201 interface standards. The CS8413 and
l Supports: AES/EBU, IEC 958, S/PDIF, & CS8414 receive data from a transmission line, recover
EIAJ CP340/1201 Professional and the clock and synchronization signals, and de-multiplex
Consumer Formats the audio and digital data. Differential or single ended in-
l Extensive Error Reporting puts can be decoded.
Repeat Last Sample on Error Option The CS8413 has a configurable internal buffer memory,
l On-Chip RS422 Line Receiver read through a parallel port, which may be used to buffer
channel status, auxiliary data, and/or user data.
l Configurable Buffer Memory (CS8413)
l Pin Compatible with CS8411 and CS8412 The CS8414 de-multiplexes the channel, user, and va-
lidity data directly to serial output pins with dedicated
output pins for the most important channel status bits.
ORDERING INFORMATION
CS8413-CS 0° to 70° C 28-pin Plastic SOIC
CS8414-CS 0° to 70° C 28-pin Plastic SOIC
I
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ............................................................ 3
RECOMMENDED OPERATING CONDITIONS .......................................... 3
DIGITAL CHARACTERISTICS.................................................................... 3
DIGITAL CHARACTERISTICS - RS422 RECEIVERS................................ 4
SWITCHING CHARACTERISTICS - CS8413 PARALLEL PORT............... 4
SWITCHING CHARACTERISTICS - SERIAL PORTS................................ 5
GENERAL DESCRIPTION .................................................................................. 7
Line Receiver .............................................................................................. 7
Clocks and Jitter Attenuation ...................................................................... 7
CS8413 DESCRIPTION ....................................................................................... 8
Parallel Port ................................................................................................ 8
Status and IEnable Registers ..................................................................... 9
Control Registers ...................................................................................... 11
Audio Serial Port ....................................................................................... 14
Normal Modes .................................................................................... 14
Special Modes .................................................................................... 14
Buffer Memory .......................................................................................... 15
Buffer Mode 0 ..................................................................................... 16
Buffer Mode 1 ..................................................................................... 17
Buffer Mode 2 ..................................................................................... 18
Buffer Updates and Interrupt Timing ......................................................... 19
ERF Pin Timing ......................................................................................... 19
CS8414 DESCRIPTION ..................................................................................... 20
Audio Serial Port ....................................................................................... 20
Normal Modes (M3 = 0) ..................................................................... 21
Special Modes (M3 = 1) ..................................................................... 21
C, U, VERF, ERF, and CBL Serial Outputs .............................................. 23
Multifunction Pins ...................................................................................... 24
Error and Frequency Reporting .......................................................... 24
Channel Status Reporting .................................................................. 24
Professional Channel Status (C0 = 0) ................................................ 25
Consumer Channel Status (C0 = 1) ................................................... 25
SCMS ................................................................................................. 25
PIN DESCRIPTIONS: CS8413 .......................................................................... 27
PIN DESCRIPTIONS: CS8414 .......................................................................... 30
PACKAGE DIMENSIONS ................................................................................. 33
APPENDIX A: RS422 RECEIVER INFORMATION .......................................... 34
Professional Interface ............................................................................... 34
Consumer Interface .................................................................................. 35
TTL/CMOS Levels .................................................................................... 35
Transformers ............................................................................................ 35
APPENDIX B: SUGGESTED RESET CIRCUIT FOR CS8414 ........................ 36
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance
product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts
to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this
information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no
license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval sys-
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2 DS240F1
CS8413 CS8414
CHARACTERISTICS/SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (GND = 0V, all voltages with respect to ground)
Parameters Symbol Min Max Units
Power Supply Voltage VD+, VA+ - 6.0 V
Input Current, Any Pin Except Supply (Note 1) Iin - ±10 mA
Input Voltage, Any Pin Except RXP, RXN VIN -0.3 (VD+) + 0.3 V
Input Voltage, RXP and RXN VIN -12 12 V
Ambient Operating Temperature (power applied) TA -55 125 °C
Storage Temperature Tstg -65 150 °C
RECOMMENDED OPERATING CONDITIONS (GND = 0V, all voltages with respect to ground)
Parameters Symbol Min Typ Max Units
Power Supply Voltage VD+, VA+ 4.75 5.0 5.25 V
Supply Current VA+ IA - 20 30 mA
VD+ ID - 20 30 mA
Ambient Operating Temperature: (Note 2) TA 0 25 70 °C
Power Consumption PD - 175 315 mW
Notes: 2. The ‘-CS’ parts are specified to operate over 0 to 70 °C but are tested at 25 °C only.
DS240F1 3
CS8413 CS8414
A4 - A0
t adcss t csadh
CS
t csl
t rwcss t csrwi
RD/WR
D7 - D0
RD/WR
D7 - D0
4 DS240F1
CS8413 CS8414
Notes: 6. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part.
(A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods in
one audio sample. In Slave mode, exactly 32 SCK periods per audio sample must be provided in most
serial port formats. Therefor, if SCK is 128 x Fs, then SCK must be gated to provide exactly 32 periods
per audio sample.
7. In Master mode, SCK and FSYNC are outputs. In Slave mode, they are inputs. In the CS8413, control
reg. 2 bit 1, MSTR, selects master. In the CS8414, formats 1, 3 and 9 are slaves.
8. The table above assumes data is output on the falling edge and latched on the rising edge. With the
CS8413 the edge is selectable. The table is defined for the CS8413 with control reg. 2 bit 0, SCED, set
to one, and for the CS8414 in formats 2, 3, 5, 6 and 7. For the other formats, the table and figure edges
must be reversed (i.e. “rising” to “falling” and vice versa.)
FSYNC MCK
t sfds t fss t mfd
t sckl t sckh
FSYNC
SCK
FSYNC Generated From
t ssv Received Data
SDATA MSB
(Mode 1) C, U
t cuvf
FSYNC FSYNC
t sfds t fss t sckl t sckh t sfdm
SCK SCK
(Modes 2,3,5,6, t ssv
t ssv
7,10,12, and 13)
SDATA MSB
SCK
(Mode 3) (Modes 0,1,4,
8,9, and 11)
Serial Output Timing - Slave Mode SDATA
DS240F1 5
CS8413 CS8414
D0-D7 Microcontroller
0.068 µF
DGND
8
0.1 µF 0.1 µF
22 7
VA+ VD+
21 19
AGND MCK
28
VERF Audio
12
9 SCK Data
Receiver RXP 26 Processor
SDATA
Circuit 11
10 FSYNC
(See Appendix A) RXN
CS8414
13
CS12/FCK Microcontroller
Channel Status 16
and/or SEL 1
C
Error/Frequency 25 14 or
ERF U
Reporting 27, 2-6 15
6 C/E-F bits CBL Logic
20
FILT
470 Ω DGND
8
0.068 µF
6 DS240F1
CS8413 CS8414
DS240F1 7
CS8413 CS8414
-5
Jitter Attenuation (dB)
-10
-15
-20
-25
-30 2 3 4 5 6
10 10 10 10 10
Jitter Frequency (Hz)
8 DS240F1
CS8413 CS8414
22 20 21 19
9
RXP Clock & Data Bi-phase 11
10 Recovery FSYNC
RXN Decoder
Audio
12
Serial SCK
Port
26
De-Multiplexor SDATA
Control
Registers
7 2X8
VD+
8 aux
DGND
Buffer
user Memory
crc
check C.S. 28 X 8
slipped
parity 14
INT
validity 25
ERF
crc IEnable
&
coding Status
no lock 4X8 24
CS
23
RD/WR
Frequency
Comparator
4 8
13
A4/ A0- D0-
FCK A3 D7
Figure 4. CS8413 Block Diagram
Status and IEnable Registers used to monitor the ram buffer. These bits continu-
The status and interrupt enable registers occupy the ally change and indicate the position of the buffer
same address space. The IER/SR bit in control reg- pointer which points to the buffer memory location
ister 1 selects whether the status registers currently being written. Each flag has a corre-
(IER/SR = 0) or the IEnable registers (IER/SR = 1) sponding interrupt enable bit in IEnable register 1
occupy addresses 0 and 1. Upon power-up, the con- which, when set, allows a transition on the flag to
trol and IEnable registers contain all zeros; there- generate a pulse on the interrupt pin. FLAG0 and
fore, the status registers are visible and all FLAG1 cause interrupts on both edges whereas
interrupts are disabled. The IER/SR bit must be set FLAG2 causes an interrupt on the rising edge only.
to make the IEnable registers visible. Further information, including timing, on the flags
can be found in the Buffer Memory section.
Status register 1 (SR1), shown in Figure 6, reports
all the conditions that can generate a low pulse four The next five bits; ERF, SLIP, CCHG,
SCLK cycles wide on the interrupt pin (INT). The CRCE/CRC1, and CSDIF/CRC2, are latches
three least significant bits, FLAG2-FLAG0, are which are set when their corresponding conditions
occur, and are reset when SR1 is read. Interrupt
DS240F1 9
CS8413 CS8414
10 DS240F1
CS8413 CS8414
status register 1 to generate an interrupt pulse. A The upper three bits in SR2, FREQ2-FREQ0, can
“0” masks that particular status bit from causing an report the receiver frequency when the receiver is
interrupt. locked. These bits are only valid when FCEN in
Status register 2 (SR2) reports all the conditions control register 1 is set, and a 6.144 MHz clock is
that can affect the error flag bit in SR1 and the error applied to the FCK pin. When FCEN is set, the
pin (ERF), and can specify the received clock fre- A4/FCK pin is used as FCK and A4 is internally set
quency. As previously mentioned, the first five bits to zero; therefore, only the lower half of the buffer
of SR2 are AND’ed with their interrupt enable bits can be accessed. Table 1 lists the frequency ranges
(in IER2) and then OR’ed to create ERF. The V, reported. The FREQ bits are updated three times
PARITY, CODE and LOCK bits are latches which per block and the clock on the FCK pin must be val-
are set when their corresponding conditions occur, id for two thirds of a block for the FREQ bits to be
and are reset when SR2 is read. The ERF pin is as- accurate. The FREQ bits are invalid when the PLL
serted each time the error occurs assuming the in- is out of lock.
terrupt enable bit in IER2 is set for that particular FREQ2 FREQ1 FREQ0 Sample Frequency
error. When the ERF pin is asserted, the ERF bit in 0 0 0 Out of Range
SR1 is set. If the ERF bit was not set prior to the 0 0 1 reserved
ERF pin assertion, an interrupt will be generated 0 1 0 reserved
(assuming bit 3 in IER1 is set). Although the ERF 0 1 1 96 kHz ± 4%
pin is asserted for each occurrence of an enabled er- 1 0 0 88.2 kHz ± 4%
ror condition, the ERF bit will only cause an inter- 1 0 1 48 kHz ± 4%
rupt once if SR1 is not read. 1 1 0 44.1 kHz ± 4%
X:01 7 6 5 4 3 2 1 0 1 1 1 32 kHz ± 4%
SR2. FREQ2 FREQ1 FREQ0 Reserved LOCK CODE PARITY V
IER2. TEST1 TEST0 INT. ENABLE BITS Table 1. Incoming Sample Frequency Bits
FOR ABOVE
IEnable register 2 has corresponding interrupt en-
SR2: FREQ2: The 3 FREQ bits indicate incoming sample frequency. able bits for the first five bits in SR2. A “1” enables
FREQ1: (must have 6.144 MHz clock on FCK pin and FCEN
FREQ0: must be “1”) the condition in SR2 to cause ERF to go high, while
LOCK: Out-of-Lock error
CODE: Coding violation a “0” masks that condition. Bit 5 is unused and bits
PARITY: Parity error
V: Validity bit high 6 and 7, the two most significant bits, are factory
IER2: TEST1,0: (0 on power-up) Must stay at “0”. test bits and must be set to zero when writing to this
INT. ENABLES: Enables the corresponding bit in SR2.
A “1” enables the interrupt. A “0” masks the interrupt. register. The CS8413 sets these bits to zero on pow-
Figure 7. Status/IEnable Register 2 er-up.
V is the validity status bit which is set any time the Control Registers
received validity bit is high. PARITY is set when a The CS8413 contains two control registers. Control
parity error is detected. CODE is set when a bi- register 1 (CR1), at address 2, selects system level
phase coding error is detected. LOCK is asserted features, while control register 2 (CR2), at address
when the receiver PLL is not locked and occurs 3, configures the audio serial port.
when there is no input on RXP/RXN, or if the re- In control register 1, when RST is low, all outputs
ceived frequency is out of the receiver lock range are reset except MCK (FSYNC and SCLK are high
(28.4 kHz to 100 kHz). impedance). The CS8413 should be reset imediate-
ly after power-up and any time the user performs a
DS240F1 11
CS8413 CS8414
system-wide reset. After the user sets RST high, the easy interface to most DSPs and other audio pro-
CS8413 comes fully out of reset when the block cessors. SDATA is normally just audio data, but
boundary is found. The serial port, in master mode, special modes are provided that output received bi-
will begin to operate as soon as RST goes high. B0 phase data, or received NRZ data with zeros substi-
and B1 select one of three buffer modes listed in tuted for preamble. Another special mode allows an
Table and illustrated in Figure 5. In all modes four asynchronous SCK input to read audio data from
bytes of user data are stored. In mode 0, one entire the serial port without slipping samples. In this
block of channel status is stored. In mode 1 eight mode FSYNC and SDATA are outputs synchro-
bytes of channel status and sixteen bytes of auxilia- nized to the SCK input. Since SCK is asynchronous
ry data are stored. In mode 2, eight bytes of channel to the received clock, the number of SCK cycles
status from each sub-frame are stored. The buffer between FSYNC edges will vary.
modes are discussed in more detail in the Buffer
B1 B0 Mode Buffer Memory Contents
Memory section. The next bit, CS2/CS1, selects the
0 0 0 Channel Status
particular sub-frame of channel status to buffer in
0 1 1 Auxiliary Data
modes 0 and 1, and has no effect in mode 2. When
1 0 2 Independent Channel Status
CS2/CS1 is low, sub-frame 1 is buffered, and when
1 1 3 Reserved
CS2/CS1 is high, sub-frame 2 is buffered. IER/SR
selects which set of registers, either IEnable or sta- Table 2. Buffer Memory Modes
tus, occupy addresses 0 and 1. When IER/SR is
X:02 7 6 5 4 3 2 1 0
low, the status registers occupy the first two ad-
CR1. FPLL FCEN IER/SR CS2/CS1 B1 B0 RST
dresses, and when IER/SR is high, the IEnable reg-
CR1: FPLL: 0 - FSYNC from RXP/RXN, 1 - FSYNC from PLL
isters occupy those addresses. FCEN enables the FCEN: enables freq. comparator (FCK must be 6.144 MHz).
IER/SR: [X:00,01] 0 - status, 1 - interrupt enable registers.
internal frequency counter. A 6.144 MHz clock CS2/CS1: ch. status to buffer; 0 - sub-frame 1, 1 - sub-frame 2.
must be connected to the FCK pin as a reference. B1:
B0:
with B0, selects the buffer memory mode.
with B1, selects the buffer memory mode.
The value of the FREQ bits in SR2 are not valid un- RST: Resets internal counters. Set to “1” for normal operation.
til two thirds of a block of data is received. Since Figure 8. Control Register 1
FCK and A4, the most significant address bit, oc-
cupy the same pin, A4 is internally set to zero when
FCEN is high. Since A4 is forced to zero, the upper
X:03 7 6 5 4 3 2 1 0
half of the buffer is not accessible while using the
CR2. ROER SDF2 SDF1 SDF0 FSF1 FSF0 MSTR SCED
frequency compare feature. FPLL determines how
CR2: ROER: Repeat previous value on error (audio data)
FSYNC is derived. When FPLL is low, FSYNC is SDF2: with SDF0 & SDF1, select serial data format.
SDF1: with SDF0 & SDF2, select serial data format.
derived from the incoming data, and when FPLL is SDF0: with SDF1 & SDF2, select serial data format.
high, it is derived from the internal phase-locked FSF1:
FSF0:
with FSF0, select FSYNC format.
with FSF1, select FSYNC format.
loop. MSTR: When set, SCK and FSYNC are output
SCED: When set, falling edge of SCK outputs data.
When clear, rising edge of SCK outputs data.
Control Register 2 configures the serial port which
consists of three pins: SCK, SDATA, and FSYNC. Figure 9. Control Register 2
SDATA is always an output, but SCK and FSYNC
can be configured as inputs or outputs. FSYNC and
SDATA can have a variety of relationships to each ROER, when set, causes the last audio sample to be
other, and the polarity of SCK can be controlled. reread if the error pin, ERF, is active. When out of
The large variety of audio data formats provides an lock, the CS8413 will output zeros if ROER is set
12 DS240F1
CS8413 CS8414
and output random data if ROER is not set. The data can be read twice or missed if the device con-
conditions that activate ERF are those reported in trolling FSYNC and SCK is on a different time-
SR2 and enabled in IER2. Figure 10 illustrates the base than the CS8413. If the audio data is read
modes selectable by SDF2-SDF0 and FSF1-FSF0. twice or missed, the SLIP bit in SR1 is set. SCED
MSTR, which in most applications will be set to selects the SCK edge to output data on. SCED high
one, determines whether FSYNC and SCK are out- causes data to be output on the falling edge, and
puts (MSTR = 1) or inputs (MSTR = 0). When SCED low causes data to be output on the rising
FSYNC and SCK are inputs (slave mode) the audio edge.
01 0 FSYNC Input
10 0 FSYNC Input
11 0 FSYNC Input
SPECIAL MODES:
SDF
210 MSTR Name 24 Bits, Incl. Aux 24 Bits, Incl. Aux
100 0 Async SCK MSB LSB MSB LSB MSB
24 Bits, Incl. Aux 24 Bits, Incl. Aux
110 0 MSB First - 24 MSB LSB MSB LSB MSB
16 Bits 16 Bits
010 0 MSB First - 16 MSB LSB MSB LSB MSB
32 Bits 32 Bits
010*† 1 NRZ Data AUX LSB MSB VUCP AUX LSB MSB VUCP AUX
DS240F1 13
CS8413 CS8414
Audio Serial Port SDATA can take on five formats in the normal se-
The audio serial port outputs the audio data portion rial port modes. The first format (see Figure 10),
from the received data and consists of three pins: MSB First, has the MSB aligned with the start of a
SCK, SDATA, and FSYNC. SCK clocks the data sample frame. Twenty-four audio bits are output
out on the SDATA line. The edge that SCK uses to including the auxiliary bits. This mode is compati-
output data is programmable from CR2. FSYNC ble with many DSPs. If the auxiliary bits are used
delineates the audio samples and may indicate the for something other than audio data, they must be
particular channel, left or right. Figure 10 illus- masked off. The second format, MSB Last, outputs
trates the multitude of formats that SDATA and data LSB first with the MSB aligned to the end of
FSYNC can take. the sample frame. This format is conducive to seri-
al arithmetic. Both of the above formats output all
Normal Modes audio bits from the received data. The last three for-
SCK and FSYNC can be inputs (MSTR = 0) or out- mats are LSB Last formats that output the most sig-
puts (MSTR = 1), and are usually programmed as nificant 16, 18, and 20 bits respectively, with the
outputs. As outputs, SCK contains 32 periods for LSB aligned to the end of the sample frame. These
each sample and FSYNC has four formats. The formats are used by many interpolation filters.
first two output formats of FSYNC (shown in Fig- Special Modes
ure 10) delineate each word and the identification
of the particular channel must be kept track of ex- Five special modes are included for unique applica-
ternally. This may be done using the rising edge of tions. In these modes, the master bit, MSTR, must
FLAG2 to indicate the next data word is left chan- be defined as shown in Figure 10. In the first mode,
nel data. The last two output formats of FSYNC Asynchronous SCK, FSYNC (which is an output in
also delineate each channel with the polarity of this mode) is aligned to the incoming SCK. This
FSYNC indicating the particular channel. The last mode is useful when the SCK is locked to an exter-
format has FSYNC change one SCK cycle before nal event and cannot be derived from MCK. Since
the frame containing the data and may be used to SCK is asynchronous, the number of SCK cycles
generate an I2S compatible interface. per sample frame will vary. The data output will be
MSB first, 24 bits, and aligned to the beginning of
When SCK is programmed as an input, 32 SCK cy- a sample frame. The second and third special
cles per sample must be provided. (There are two modes are unique in that they contain 24 and 16
formats in the Special Modes section where SCK SCK cycles respectively per sample frame, where-
can have 16 or 24 clocks per sample.) The four as all normal modes contain 32 SCK cycles. In
modes where FSYNC is an input are similar to the these two modes, the data is MSB first and fills the
FSYNC output modes. The first two require a tran- entire frame. The fourth special mode outputs NRZ
sition of FSYNC to start the sample frame, whereas data including the V, U, C, and P bits and the pre-
the last two are identical to the corresponding amble replaced with zeros. SCK is an output with
FSYNC output modes. If the circuit generating 32 SCK cycles per sample frame. The fifth mode
SCK and FSYNC is not locked to the master clock outputs the biphase data recovered from the trans-
of the CS8413, the serial port will eventually be re- mission line with 64 SCK cycles output per sample
read or a sample will be missed. When this occurs, frame, with data changing on the rising edge.
the SLIP bit in SR1 will be set.
Normally, data recovered by the CS8413 is delayed
by two frames in propagating through the part, but
14 DS240F1
CS8413 CS8414
in the fourth and fifth special modes, the data is de- which two bytes the part will write next, thereby in-
layed only a few bit periods before being output. dicating which two bytes are free to be read.
However, error codes, and the C, U and V bits fol- FLAG1 is buffer mode dependent and is discussed
low the normal pathway with a two frame delay (so in the individual buffer mode sections. A transition
that the error code would be output with the offend- of FLAG1 will generate an interrupt if the appro-
ing data in the other modes). As a result, in special priate interrupt enable bit is set.
modes four and five, the error codes are nearly two
frames behind the data output on SDATA. FLAG2 is set high after channel status byte 23, the
last byte of the block, is written and set low after
Buffer Memory channel status byte 3 is written to the buffer mem-
In all buffer modes, the status, mask, and control ory. FLAG2 is unique in that only the rising edge
registers are located at addresses 0-3, and the user can cause an interrupt if the appropriate interrupt
data is buffered at locations 4 through 7. The paral- enable bit in IER1 is set.
lel port can access any location in the user data Figure 11 illustrates the flag timing for an entire
buffer at any time; however, care should be taken channel status block which includes 24 bytes of
not to read a location when that location is being channel status data per channel and 384 audio sam-
updated internally. This internal writing is done ples. The lower portion of Figure 11 expands the
through a second port of the buffer and is done in a first byte of channel status showing eight pairs of
cyclic manner. As data is received, the bits are as- data, with a pair defined as a frame. This is further
sembled in an internal 8-bit shift register which, expanded showing the first sub-frame (A0) to con-
when full, is loaded into the buffer memory. The tain 32 bits defined as per the digital audio stan-
first bit received is stored in D0 and, after D7 is re- dards. When receiving stereo, channel A is left and
ceived, the byte is written into the proper buffer channel B is right.
memory location.
For all three buffer modes, the three most signifi-
The user data is received one bit per sub-frame. At cant bits in SR1, shown in Figure 6, can be used to
the channel status block boundary, the internal monitor the channel status data. In buffer mode 2,
pointer for writing user data is initialized to 04H bits 7 and 6 change definition and are described in
(Hex). After receiving eight user bits, the byte is that section. Channel status data, as described in the
written to the address indicated by the user pointer standards, is independent for each channel. Each
which is then incremented to point to the next ad- channel contains its own block of channel status
dress. After receiving all four bytes of user data, 32 data, and in most systems, both channels will con-
audio samples, the user pointer is set to 04H again tain the same channel status data. Buffer modes 0
and the cycle repeats. FLAG0, in SR1 can be used and 1 operate on one block of channel status with
to monitor the user data buffer. When the last byte the particular block selected by the CS2/CS1 bit in
of the user buffer, location 07H, is written, FLAG0 CR1. CSDIF, bit 7 in SR1, indicates when the
is set low and when the second byte, location 05H, channel status data for each channel is not the same
is written, FLAG0 is set high. If the corresponding even though only one channel is being buffered.
bit in the interrupt enable register (IER1, bit 0) is CRCE, bit 6 in SR1, indicates a CRC error oc-
set, a transition of FLAG0 will generate a low pulse curred in the buffered channel. CCHG, bit 5 in
on the interrupt pin. The level of FLAG0 indicates SR1, is set when any bit in the buffered channel sta-
tus bytes 0 to 3, change from one block to the next.
DS240F1 15
CS8413 CS8414
Block
(384 Audio Samples)
Flag 2
Flag 1
Mode 0
Flag 1
Modes 1 & 2
Flag 0
23 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1
Channel Status Byte
(Expanded)
Frame
A0 B0 A1 B1 A2 B2 A7 B7
(Expanded)
Sub-frame
bit 0 3 4 7 8 27 28 29 30 31
Preamble Aux Data LSB Audio Data MSB V U C P
Validity
User Data
Channel Status Data
Parity Bit
16 DS240F1
CS8413 CS8414
FLAG1 in status register 1, SR1, can be used to cyclic buffer for the last 20 bytes of channel status
monitor the channel status buffer. In mode 0, data. The channel status buffer is divided in this
FLAG1 is set low after channel status byte 23 (the fashion because the first four bytes are the most im-
last byte) is written, and is set high when channel portant ones; whereas, the last 20 bytes are often
status byte 15, location 17H is written. If the corre- not used (except for byte 23, CRC).
sponding interrupt enable bit in IER1 is set, a tran- FLAG1 and FLAG2 can be used to monitor this
sition of FLAG1 will generate a pulse on the buffer as shown in Figure 13. FLAG1 is set high
interrupt pin. Figure 12 illustrates the memory when CS byte 1, location 09H, is written and is tog-
write sequence for buffer mode 0 along with flag gled when every other byte is written. FLAG2 is set
timing. The arrows on the flag timing indicate high after CS byte 23 is written and set low after CS
when an interrupt will occur if the appropriate in- byte 3, location 0BH, is written. FLAG2 deter-
terrupt enable bit is set. FLAG0 can cause an inter- mines whether the channel status pointer is writing
rupt on either edge, which is only shown in the to the first four-byte section of the channel status
expanded portion of the figure for clarity. buffer or the second four-byte section, while
Buffer Mode 1 FLAG1 indicates which two bytes of the section
are free to update.
In buffer mode 1, eight bytes are allocated for chan-
nel status data and sixteen bytes for auxiliary data The auxiliary data buffer, locations 10H to 1FH, is
as shown in Figure 5. The user data buffer is the written to in a cyclic manner similar to the other
same for all modes. The channel status buffer, loca- buffers. Four auxiliary data bits are received per
tions 08H to 0FH, is divided into two sections. The audio sample (sub-frame) and, since the auxiliary
first four locations always contain the first four data is four times larger than the user data, the aux-
bytes of channel status, identical to mode 0, and are iliary data buffer on the CS8413 is four times larger
written once per channel status block. The second allowing FLAG0 to be used to monitor both.
four locations, addresses 0CH to 0FH, provide a
Block
(384 Audio Samples)
FLAG2
FLAG1
FLAG0
C.S. Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1
C.S. Address 08 0B 0C 1F 08
(Expanded)
FLAG0
C.S. Addr. 1F 08 09 0A 0B (Addresses are in Hex)
User Addr. 07 04 05 06 07 04 05 06 07
DS240F1 17
CS8413 CS8414
Block
(384 Audio Samples)
FLAG2
FLAG1
FLAG0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1
C.S. Byte
C.S. Address 08 0B 0C 0F 0C 0F 0C 0F 0C 0F 0C 0F 08
FLAG1
FLAG0
C.S. Addr. 0F 08 09 0A 0B
User Addr. 07 04 05 06 07 04 05 06 07
Aux. Addr. 1F 10 13,14 17 18 1B,1C 1F 10 13,14 17 18 1B,1C 1F
Figure 13. CS8413 Buffer Memory Write Sequence - MODE 1
Block
(384 Audio Samples)
FLAG2
FLAG1
FLAG0
C.S. Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1
Left C.S. Ad. 08 0B 0C 0F 0C 0F 0C 0F 0C 0F 0C 0F 08
Right C.S. Ad. 10 13 14 17 14 17 14 17 14 17 14 17 10
FLAG1
FLAG0
Left C.S. Ad. 08 09 0A 0B
Right C.S. Ad. 10 11 12 13
User Address 04 05 06 07 04 05 06 07
Figure 14. CS8413 Buffer Memory Write Sequence - MODE 2
18 DS240F1
CS8413 CS8414
The two most significant bits in SR1 change defini- rupt line, flags, and the RAM write line. SCK is 64
tion for buffer mode 2. These two bits, when set, in- times the incoming sample frequency, and is the
dicate CRC errors for their respective channels. A same SCK output in master mode. The FSYNC
CRC error occurs when the internal calculated shown is valid for all master modes except the I2S
CRC for channel status bytes 0 through 22 does not compatible mode. The interrupt pulse is shown to
match channel status byte 23. CCHG, bit 5 in SR1, be 4 SCK periods wide and goes low 5 SCK peri-
is set when any bit in the first four channel status ods after the RAM is written. Using the above in-
bytes of either channel changes from one block to formation, the entire data buffer may be read
the next. Since channel status doesn’t change very starting with the next byte to be updated by the in-
often, this bit may be monitored rather than check- ternal pointer.
ing all the bits in the first four bytes. These bits are
illustrated in Figure 6.
ERF Pin Timing
ERF signals that an error occurred while receiving
Buffer Updates and Interrupt Timing the audio sample that is currently being read from
As mentioned previously in the buffer mode sec- the serial port. ERF changes with the active edge of
tions, conflicts between externally reading the FSYNC and is high during the erroneous sample.
buffer RAM and the CS8413 internally writing to it ERF is affected by the error conditions reported in
may be averted by using the flag levels to avoid the SR2: LOCK, CODE, PARITY, and V. Any of
section currently being addressed by the part. How- these conditions may be masked off using the cor-
ever, if the interrupt line, along with the flags, is responding bits in IER2. The ERF pin will go high
utilized, the actual byte that was just updated can be for each error that occurs. The ERF bit in SR1 is
determined. In this way, the entire buffer can be different from the ERF pin in that it only causes an
read without concern for internal updates. interrupt the first time an error occurs until SR1 is
Figure 15 shows the detailed timing for the inter- read. More information on the ERF pin and bit is
SCK
IWRITE
INT (FLAG0,1)
INT (FLAG2)
FSF1,0 = 1 0
MSTR =1
SCED =1
Figure 15. RAM/Buffer - Write and Interrupt Timing
DS240F1 19
CS8413 CS8414
contained at the end of the Status and IEnable Reg- with the ERF flag to provide a single pin, VERF,
isters section. indicating that the audio output may not be valid.
This pin may be used by interpolation filters that
CS8414 DESCRIPTION provide error correction. A block diagram of the
The CS8414 does not need a microprocessor to CS8414 is illustrated in Figure 16.
handle the non-audio data (although a micro may
The line receiver and jitter performance are de-
be used with the C and U serial ports). Instead, ded-
scribed in the sections directly preceding the
icated pins are available for the most important
CS8413 sections in the beginning of this data sheet.
channel status bits. The CS8414 is a monolithic
CMOS circuit that receives and decodes digital au- Audio Serial Port
dio data which was encoded according to the digital The audio serial port is used primarily to output au-
audio interface standards. It contains an RS422 line dio data and consists of three pins: SCK, FSYNC,
receiver and clock and data recovery utilizing an and SDATA. These pins are configured via four
on-chip phase-locked loop. The audio data is out- control pins: M0, M1, M2, and M3. M3 selects be-
put through a configurable serial port that supports tween eight normal serial formats (M3 = 0), and six
14 formats. The channel status and user data have special formats (M3 = 1).
their own serial pins and the validity flag is OR’ed
22 20 21 19 17 18 24 23
9 Timing
RXP Clock & Data
Recovery
RXN 11
FSYNC
10
Audio 12
Bi-phase SCK
Serial
Decoder
Port
and De-Multiplexer
Frame 26
SDATA
Sync
1
7 C
VD+
CRC
8 Parity check R 14
DGND e U
Check
g 28
CS12/ 13 i VERF
FCK s
Channel t
Frequency Error
Status e 15
Comparator Encoder CBL
Latch r
3 3 s
25
6 ERF
6
16
SEL Multiplexer
6 5 4 3 2 27
C0/ Ca/ Cb/ Cc/ Cd/ Ce/
E0 E1 E2 F0 F1 F2
20 DS240F1
CS8413 CS8414
Normal Modes (M3 = 0) M0. In formats 8, 9, and 10, SCK, FSYNC, and
SDATA are the same as in formats 0, 1, and 2 re-
When M3 is low, the normal serial port formats
spectively; however, the recovered data is output as
shown in Figure 17 are selected using M2, M1, and
is even if ERF is high, indicating an error. (In
M0. These formats are also listed in Table 3,
modes 0-2 the previous valid sample is output.)
wherein the first word past the format number
Similarly, when out of lock, the CS8414 will still
(Out-In) indicates whether FSYNC and SCK are
output all the recovered data, which should be ze-
outputs from the CS8414 or are inputs. The next
ros if there is no input to the RXP, RXN pins. For-
word (L/R-WSYNC) indicates whether FSYNC in-
mat 11 is similar to format 0 except that SCK is an
dicates the particular channel or just delineates
input and FSYNC is an output. In this mode
each word. If an error occurs (ERF = 1) while using
FSYNC and SDATA are synchronized to the in-
one of these formats, the previous valid audio data
coming SCK, and the number of SCK periods be-
for that channel will be output. As long as ERF is
tween FSYNC edges will vary since SCK is not
high, that same data word will be output. If the
synchronous to received data stream. This mode
CS8414 is not locked, it will output all zeroes. In
may be useful when writing data to storage.
some modes FSYNC and SCK are outputs and in
others they are inputs. In Table 3, LSBJ is short for M2 M1 M0 Format
LSB justified where the LSB is justified to the end 0 0 0 8 - Format 0 - No repeat on error
of the audio frame and the MSB varies with word 0 0 1 9 - Format 1 - No repeat on error
length. As outputs the CS8414 generates 32 SCK 0 1 0 10 - Format 2 - No repeat on error
periods per audio sample (64 per stereo sample) 0 1 1 11 - Format 0 - Async. SCK input
and, as inputs, 32 SCK periods must be provided 1 0 0 12 - Received NRZ Data
per audio sample. When FSYNC and SCK are in- 1 0 1 13 - Received Bi-phase Data
puts, one stereo sample is double buffered. For 1 1 0 14 - Reserved
those modes which output 24 bits of audio data, the 1 1 1 15 - CS8414 Reset
auxiliary bits will be included. If the auxiliary bits
Table 4. Special Audio Port Modes (M3 = 1)
are not used for audio data, they must be masked
Format 12 is similar to format 7 except that SDA-
off.
TA is the entire data word received from the trans-
M2 M1 M0 Format mission line including the C, U, V, and P bits, with
0 0 0 0 - Out, L/R, 16-24 Bits zeros in place of the preamble. In format 13 SDA-
0 0 1 1 - In, L/R, 16-24 Bits TA contains the entire biphase encoded data from
0 1 0 2 - Out, L/R, I2S Compatible the transmission line including the preamble, and
0 1 1 3 - In, L/R, I2S Compatible SCK is twice the normal frequency. The normal
1 0 0 4 - Out, WSYNC, 16-24 Bits two frame delay of data from input to output is re-
1 0 1 5 - Out, L/R, 16 Bits LSBJ duced to only a few bit periods in formats 12 and
1 1 0 6 - Out, L/R, 18 Bits LSBJ 13. However, the C, U, V bits and error codes fol-
1 1 1 7 - Out, L/R, MSB Last low their normal pathways and therefore follow the
output data by nearly two frames. Figure 18 illus-
Table 3. Normal Audio Port Modes (M3 = 0) trates formats 12 and 13. Format 14 is reserved and
Special Modes (M3 = 1) not presently used, and format 15 causes the
CS8414 to go into a reset state. While in reset all
When M3 is high, the special audio modes de- outputs will be inactive except MCK. The CS8414
scribed in Table 4 are selected via M2, M1, and comes out of reset at the first block boundary after
DS240F1 21
CS8413 CS8414
FMT
No. M2 M1 M0
FSYNC (out) Left Right
0 0 0 0
SCK (out)
16 Bits 16 Bits
18 Bits 18 Bits
22 DS240F1
CS8413 CS8414
No.
12* FSYNC (out) Left Right
SCK (out)
SCK (out)
CBL
C0,
Ca-Ce
SDATA Right 191 Left 0 Right 0 Left 1 Right 31 Left 32 Right 191 Left 0
FSYNC
ERF,
VERF
C, U
DS240F1 23
CS8413 CS8414
24 DS240F1
CS8413 CS8414
upon the C0 professional/consumer bit. The infor- Consumer Channel Status (C0 = 1)
mation reported is shown in Table 7. When C0 is high, the received channel status block
Pin Professional Consumer
is encoded according to the consumer format. In
this case Ca through Ce are defined differently as
C0 0 (low) 1 (high)
shown in Table 7. Ca is the inverse of channel sta-
Ca C1 C1
tus bit 1, C1, indicating audio (C1 = 1) or non-audio
Cb EM0 C2 (C1 = 0). Cb is defined as the inverse of channel
Cc EM1 C3 status bit 2, C2, which indicates copy inhibit/copy-
Cd C9 ORIG right information. Cc, defined as C3, is the empha-
Ce CRCE IGCAT sis bit of channel status, with C3 low indicating the
data has had pre-emphasis added.
Table 7. Channel Status Pins
The audio standards, in consumer mode, describe
Professional Channel Status (C0 = 0) bit 15, L, as the generation status which indicates
whether the audio data is an original work or a copy
When C0 is low, the received channel status block
(1st generation or higher). The definition of the L
is encoded according to the professional/broadcast
bit is reversed for three category codes: two broad-
format. The Ca through Ce pins are defined for
cast codes, and laser-optical (CD’s). Therefore, to
some of the more important professional bits. As
interpret the L bit properly, the category code must
listed in Table 7, Ca is the inverse of channel status
be decoded. The CS8414 does this decoding inter-
bit 1. Therefore, if the incoming channel status bit
nally and provides the ORIG signal that, when low,
1 is 1, Ca, defined as C1, will be 0. C1 indicates indicates that the audio data is original over all cat-
whether audio (C1 = 1) or non-audio (C1 = 0) data egory codes.
is being received. Cb and Cc, defined as EM0 and
EM1 respectively, indicate emphasis and are en- SCMS
coded versions of channel status bits 2, 3, and 4. The consumer audio standards also mention a serial
The decoding is listed in Table 8. Cd, defined as copy management system, SCMS, for dealing with
C9, is the inverse of channel status bit 9, which copy protection of copyrighted works. SCMS is de-
gives some indication of channel mode. (Bit 9 is signed to allow unlimited duplication of the origi-
also defined as bit 1 of byte 1.) When Ce, defined nal work, but no duplication of any copies of the
as CRCE, is low, the CS8414 calculated CRC value original. This system utilizes the channel status bit
does not match the received CRC value. This signal 2, Copy, and channel status bit 15, L or generation
may be used to qualify Ca through Cd. If Ca status, along with the category codes. If the Copy
through Ce are being displayed, Ce going low can bit is 0, copyright protection is asserted over the
indicate not to update the display. material. Then, the L bit is used to determine if the
material is an original or a duplication. (As men-
EM1 EM0 C2 C3 C4 Emphasis
tioned in the previous paragraph, the definition of
0 0 1 1 1 CCITT J.17 emphasis
the L bit can be reversed based on the category
0 1 1 1 0 50/15 µs emphasis
codes.) There are two category codes that get spe-
1 0 1 0 0 No Emphasis
cial attention: general and A/D converters without
1 1 0 0 0 Not Indicated
C or L bit information. For these two categories the
Table 8. Emphasis Encoding SCMS standard requires that equipment interfacing
to these categories set the C bit to 0 (copyright pro-
DS240F1 25
CS8413 CS8414
26 DS240F1
CS8413 CS8414
DS240F1 27
CS8413 CS8414
Parallel Interface
28 DS240F1
CS8413 CS8414
Receiver Interface
DS240F1 29
CS8413 CS8414
30 DS240F1
CS8413 CS8414
M0, M1, M2, M3 - Serial Port Mode Select, PINS 23, 24, 18, 17.
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. M3 selects
between eight normal modes (M3 = 0), and six special modes (M3 = 1).
Control Pins
DS240F1 31
CS8413 CS8414
C0, Ca, Cb, Cc, Cd, Ce - Channel Status Output Bits, PINS 2-6, 27.
These pins are dual function with the ‘C’ bits selected when SEL is high. Channel status
information is displayed for the channel selected by CS12. C0, which is channel status bit 0,
defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the definition of
the Ca-Ce pins. These pins are updated with the rising edge of CBL.
Receiver Interface
32 DS240F1
CS8413 CS8414
PACKAGE DIMENSIONS
E H
1
b
D c
SEATING
PLANE A
∝
L
e A1
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.093 0.104 2.35 2.65
A1 0.004 0.012 0.10 0.30
B 0.013 0.020 0.33 0.51
C 0.009 0.013 0.23 0.32
D 0.697 0.713 17.70 18.10
E 0.291 0.299 7.40 7.60
e 0.040 0.060 1.02 1.52
H 0.394 0.419 10.00 10.65
L 0.016 0.050 0.40 1.27
∝ 0° 8° 0° 8°
DS240F1 33
CS8413 CS8414
8kΩ 8kΩ
16kΩ Figure 21. Professional Input Circuit
9 RXP
+
* See Text 0.01 µF CS8413/14
XLR
10 RXN
- RXP
16kΩ 110Ω
4kΩ 4kΩ
Twisted 110Ω
Pair
0.01 µF
RXN
Figure 20. RS422 Receiver Internal Circuit 1
34 DS240F1
CS8413 CS8414
75Ω
Coax 75Ω
RXN RXN
0.01 µF 0.01 µF
DS240F1 35
CS8413 CS8414
M0 M0
M1 M1
CS8414
M2
M2
M3
M3
RESET
The CS8414 should be reset immediately after Mode Select pins high. Figure 25 shows a simple
power-up and any time the user issues a system- circuit to implement this. The OR gates can be
wide reset. This is accomplished by pulling all four 74LS32 type gates.
36 DS240F1
• Notes •