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    University of The People CS1104: Computer Systems Instructor: Raval Dipakkumar May 11, 2022

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    Qurtiss Mayfield
    The document discusses the Hack architecture and the differences between RISC and CISC architectures. The Hack architecture is a 16-bit von Neumann architecture that uses a single-cycle fetch-execute logic to execute instructions. It uses A-instructions to specify memory addresses and C-instructions to specify computations. RISC architectures use a small number of simple instructions that can be executed in one clock cycle, while CISC architectures use more complex variable-length instructions that may take multiple cycles. RISC has advantages of higher performance and simpler design, while CISC has advantages of smaller memory requirements and easier programming.

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    University of The People CS1104: Computer Systems Instructor: Raval Dipakkumar May 11, 2022

    Uploaded by

    Qurtiss Mayfield
    27 views4 pages
    The document discusses the Hack architecture and the differences between RISC and CISC architectures. The Hack architecture is a 16-bit von Neumann architecture that uses a single-cycle fetch-execute logic to execute instructions. It uses A-instructions to specify memory addresses and C-instructions to specify computations. RISC architectures use a small number of simple instructions that can be executed in one clock cycle, while CISC architectures use more complex variable-length instructions that may take multiple cycles. RISC has advantages of higher performance and simpler design, while CISC has advantages of smaller memory requirements and easier programming.

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    CS1104 Computer systems Discussion assignment unit 5 submission

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    DACS1104-51

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    The document discusses the Hack architecture and the differences between RISC and CISC architectures. The Hack architecture is a 16-bit von Neumann architecture that uses a single-cycle fetch-execute logic to execute instructions. It uses A-instructions to specify memory addresses and C-instructions to specify computations. RISC architectures use a small number of simple instructions that can be executed in one clock cycle, while CISC architectures use more complex variable-length instructions that may take multiple cycles. RISC has advantages of higher performance and simpler design, while CISC has advantages of smaller memory requirements and easier programming.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    27 views4 pages

    University of The People CS1104: Computer Systems Instructor: Raval Dipakkumar May 11, 2022

    Uploaded by

    Qurtiss Mayfield
    The document discusses the Hack architecture and the differences between RISC and CISC architectures. The Hack architecture is a 16-bit von Neumann architecture that uses a single-cycle fetch-execute logic to execute instructions. It uses A-instructions to specify memory addresses and C-instructions to specify computations. RISC architectures use a small number of simple instructions that can be executed in one clock cycle, while CISC architectures use more complex variable-length instructions that may take multiple cycles. RISC has advantages of higher performance and simpler design, while CISC has advantages of smaller memory requirements and easier programming.

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    Discussion Forum unit 5

    University of the People

    CS1104: Computer systems

    Instructor: Raval Dipakkumar

    May 11, 2022

    What are the implications of the Hack architecture?

    The Hack architecture is a 16-bit von Neumann architecture that is made of:

     data memory (RAM): a sequence of 16-bit registers. RAM[0], RAM[1], etc.


     instruction memory (ROM): a sequence of 16-bit registers. ROM[0], ROM[1], etc.
     CPU: performs 16-bit instructions
     I/O devices: a screen and a keyboard
     instruction bus/data bus/address bus: electric path

    The Hack architecture is unique in the way that it uses a single-cycle fetch-execute logic. While
    most general-purpose computers use a two-cycle logic, the Hack computer executes the current
    instruction and reads (fetches) the next instruction in a single, two-part clock cycle. 
    This can be done by using two instructions, an address instruction (A-instruction) and a compute
    instruction (C-instruction). Each type of instruction can be represented in the following symbolic
    and binary syntax.

    A-instruction
    C-instruction

    (Source: University of Washington, 2020).

    In the binary syntax, if MSB (Most Significant Bit) is 0, it represents A-instruction and if MSB is 1,
    it represents C-instruction. 

    For example, for the A-instruction, we can use the following syntax.
    Symbolic syntax
    @25  //represents the value that is loaded into the A register
    Binary syntax
    0000000000011001  //MSB is 0, which represents A-instruction followed by the value 25

    If we want to set RAM[300] to the value of the D register minus 1, the symbolic representation
    will be as followed:
    @250       // selecting the memory, data memory=250
    M=D-1     // RAM[250] = D -1

    Discuss the difference between RISC and CISC architecture. What are the advantages and
    disadvantages of each architecture?

    RISC (Reduced Instruction Set Computer Processor) and CISC (Complex Instruction Set
    Computer) are types of microprocessors. It performs the core functions of a computer CPU. 
    As the names indicate RISC is built to minimize the instruction and CISC has a more complex
    decoding of instructions. 

    Some of the differences between RISC and CISC are (GeeksforGeeks, 2022):
    1. RISC uses a limited number of instructions and CISC uses a larger number of
    instructions. 
    2. RISC execution time is shorter while CISC execution time is longer.
    3. RISC's instructions are generally executed in one clock cycle while CISC's instructions
    may take longer than a single clock cycle to execute. 
    4. RISC uses the pipelining technique to execute multiple parts of instructions while CISC is
    not pipelined or less pipelined.
    5. RISC uses multiple registers while CISC uses a single register set. 
    6. RISC has fixed format instruction while CISC's instruction length could be variable. 
    7. RISC does not support an array while CISC supports an array.

    Advantages of RISC

     Due to the small number of the instruction set used, the RISC's performance is better.
     RISC is simpler than CISC due to its simple design and the ability to execute in one clock
    cycle.
     Since the execution time is minimized, it can increase the speed of the overall operations
    while maximizing efficiency.

    Disadvantages of RISC (GeeksforGeeks, 2022):

     The computer has to repeatedly perform simple operations to execute a larger program
    having a large number of processing operations.
     The performance of RISC processors depends on the compiler or the programmer. The
    following instructions might rely on the previous instruction to finish their execution.

    Advantages of CISC

     Memory requirement is minimum.


     The compiler requires little effort to translate high-level programs or statement
    languages into assembly or machine language in CISC processors (Javatpoint, n.d.).
     It's easier to add the new command to the chip, which doesn't require the change the
    structure of the instruction set.

    Disadvantages of CISC (Javatpoint, n.d.):

     It tends to be slower than RISC to execute per instruction cycle.


     The performance could be decreased due to the slowness of the clock speed.
     CISC chips require more transistors compared to RISC design.

    References
    GeeksforGeeks. (2022, January 13). Difference between RISC and CISC processor | Set
    2. https://www.geeksforgeeks.org/difference-between-risc-and-cisc-processor-set-2/
    Javatpoint. (n.d.). Difference Between RISC and CISC - javatpoint.
    Javatpoint. https://www.javatpoint.com/risc-vs-cisc
    University of Washington. (2020). Hack Assembly &
    Reflection. https://courses.cs.washington.edu/courses/cse390b/20sp/lectures/
    CSE390b_Week4_Lecture8.pdf

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