DESIGN AND IMPLEMENTATION OF TERNARY LOGIC

CIRCUITS

ABSTRACT:

This project mainly concentrates on the design and implementation of ternary logic circuits. The
ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The
ternary logic has significant merits over binary logic in designing digital circuits. In this project, it is
proposed to NAND and NOR logical gates with ternary logic. The main objective of the work is, to design
and implement ternary logic circuits and to analyse the function of the ternary combinational circuits
using mentor graphics tool in 90nm technology. In this project Ternary logic gates are Implemented by
the layout tool. Power analysis are obtained.
 CHAPTER _I

INTRODUCTION

MVL (Multi-Valued Logic) is also called as MultipleValued, Multi-Valued logic. MVL

that is, Multi-Valued Logic is termed as a technique that has more than two possible states or two
truth values. A two-valued logic can be extended to a n-valued logic, that is, for example, in a
three valued logic i.e., base or radix as three, it is termed as ternary logic and a quaternary logic
i.e., radix as four is used for four valued logic and so on. Such a three valued logic with logic
symbols as 0,1 and 2 and four valued logic has logic states of 0,1,2 and 3. The ternary numeral
system has its base or radix as 3 [1]. Radix generally defined as the number of unique digits or
unique symbols that can be expressed using a single digit. In a binary system, the two logic
symbols 0 and 1 are used to represent a value, and coming to the ternary system, the three logic
symbols (0, 1 and 2) are used. The bipolar notation is one of the methods in the ternary logic
system which is denoted with symbols -1, 0, 1. In this paper, the notation used is 0,1 and 2. The
ternary logic system gives the meaning of three-valued switching. Three valued logic system or
ternary logic system has many benefits when compared with the binary logic system in designing
digital circuits. reduction in chip area can be achieved, and more importantly, easy error
detection and error correction codes can be employed. Revised Manuscript Received on
February 11, 2020. G.Thrishala*, Department of ECE, G. Narayanamma Institute of Technology
and Sciences, India. Email: thrishala437@gmail.com K.Ragini, Department of ECE, G.
Narayanamma Institute of Technology and Sciences, India. Email:
ragini_kanchimi@yahoo.co.in For instance, more data can be transmitted over an arrangement of
lines in a given length, diminishing in the complexity of interconnections is observed, decrease
in chip area can be accomplished, and more significantly the error detection and error correction
of codes can be accomplished. The ternary logic system has some significant merits over the
binary logic system [2,3]. To implement the different logic functions, the decrease in the number
of interconnections in a circuit is observed, in this way, the chip area has been reduced, and
importantly more data can be transmitted and lesser memory is required. Apart from this, at very
higher speeds, the serial and some serial-parallel operations are carried out. It’s been used in
applications like areas of communications and digital signal processing.

Binary logic has two logic values (logic 0 and logic 1) whereas MVL has more than two
logic values i.e. Ternary logic has three logic values (logic 0, logic 1 and logic 2) while
Quaternary logic has four logic values. Major problems with usage of two level logic are
interconnection problem that arises inside the chip and also among the chips (Vudadha et al.,
2013). As number of logic elements in the chip are increasing every year, positioning and
interconnection of those logic elements are creating problems for the designers; chip area
required for interconnecting logic elements are more than the area required for placing of all the
logic elements (Hurst et al., 1984). Also, taking the increasing number of interconnection out of
the chip for packaging is creating new challenges for industries (Hurst et al., 1984).

Due to this binary logic has reached its limitations therefore it is required to have a logic level of
radix greater than 2. MVL raises data content per interconnection therefore, interconnection and
insulation required can be reduced. As each pin are carrying more data, therefore number of pins
required can be reduced, hence the complexity of the chips are reduced. Pin-out issue and
number of associations inside the circuit could be considerably reduced if signals in the circuit
are permitted to expect more logic levels instead of two logic levels. (Dubrova et al., 1999).

As the number of transistors per unit area of the chip is doubling in every twelve months, various
endeavours have been made to shrivel the size of the MOSFET devices [Kim et al., 2010].
MOSFET device performance are hampered as the supply voltage (VDD) approached to 1V;
therefore, further lowering of threshold voltage (Vth) is difficult (Kim et al., 2010). Lowering of
threshold voltage leads to subthreshold leakage current increase exponentially as Vth decreases.
Therefore, it become necessary to determine lowest possible value of Vth for ideal working of
MOSFET devices (Kim et al., 2010).

Threshold voltage brings new challenges therefore; a new technology is required to acknowledge
these challenges. CMOS technology enabled scaling of MOSFET transistors from micrometre to
sub-100nm regime. As silicon device scaling reaches sub-100nm regime device performance are
hampered by short-channel effect (Kim et al., 2010).

As CMOS devices are reaching its limitation many researchers had made efforts to find a way to
take benefits of ballistic transport characteristics and quantum mechanical phenomena for these
nano devices under low power consumption. Lots of new nano-electronic devices are introduced
such as Nanowire (NW) transistors, Carbon Nanotube Field Effect Transistor (CNTFET),
Graphene Nanoribbon (GNR) Transistors, Single Electron Transistor, Quantum Dot Cellular
Autometa (Kim et al., 2010).

Carbon nanotube was introduced in 1991 (Iijima et al., 1991). CNTFET are most popular among
the nanoelectronic device because of its operating principle similar to that of CMOS transistors.
CNTFET with different threshold voltages (Vth) (Multi-threshold CNTFET) can be attained by
varying CNT’s diameter. Properties like high thermal conductivity, exceptional mechanical
stability, thermal stability and large current carrying ability makes CNTFET’s more popular
(Kim et al., 2010).

II. CARBON NANOTUBE FIELD EFFECT TRANSISTOR Carbon Nanotube (CNT) is a long
hollow tube that is done by wrapping a graphene sheet. Graphene is honey comb sheet of carbon
atom which is one atom thick. Chemical bonding of nanotube is composed of SP2 bonds (Iijima
et al., 1991).

Single Walled CNT (SWCNT) and Multi Walled CNT (MWCNT) are the types of CNT’s. Single Walled CNT
(SWCNT) comprise of single graphene sheet wrapped in the form of a tube, whereas Multi Walled CNT
(MWCNT) comprise of several sheets of graphene wrapped in a tube form (Iijima et al. and Iijima et al.,
1991,1993). Diameter of MWCNT can be in tens of nanometre, while diameter of SWCNT can be one or
five nanometres. The direction of wrapping of graphene sheet to form CNT decides whether the
nanotubes are of metallic nature or semiconducting nature. The chirality indexes (n, m) of nanotube
describes the direction of wrapping, where m and n are integers. Metallic or semiconducting behaviour
of nanotube can be resolved by its index (n, m). Nanotube is metallic in nature if n is equal to m i.e. (n =
m) or difference of n and m is equal to 3i i.e. (n – m = 3i), where ‘i’ is an integer; otherwise CNT is of
semiconducting nature (Stanford University CNFET Model et al.).

Depending upon the chirality CNT is classified as chiral, zigzag or armchair nanotube which has metallic
or semiconducting characteristics (Collins et al., 2001). CNTFET’s are of three types: - SB (Schottky
barrier) CNTFET, BTBT (Band to band tunnelling) CNTFET, Metal Oxide Semiconductor Field Effect
Transistor (MOSFET) like Carbon Nanotube Field Effect Transistor (CNTFET). MOSFET’s like CNTFET’s
have similar characteristics to that of MOSFET’s (Das et al., 2018). Therefore, MOSFET like CNTFET are
most popular among all other types of CNTFET’s. Diameters of CNT can be calculated by (Stanford
University CNFET Model et al.), (Deng et al. and Deng et al., 2007,2007): -

--------(1)

Where a0 = 0.142 nm is interatomic distance among neighbouring carbon atoms. CNTFET threshold
voltage can be changed by varying the diameter of CNT’s. Therefore, to accomplish multi-threshold
CNTFET’s with different diameters are used.The threshold voltage of the CNTFET can be changed by
altering the chirality vector. If we assume chirality vector m to be zero, then threshold voltage ratio of
two CNTFET’s with unlike chirality vector is given by (Raychowdhury et al., 2005): -

it is clear that diameter (DCNT) and chirality vector (n) both are in inverse proportion with Vth.
Therefore, it is possible to vary the Vth of the CNTFET by varying chirality vector (n) or DCNT (CNT
diameter) (Raychowdhury et al., 2005).
 COMPLEMENTARY MOSFET

CMOS
Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing
integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM,
and other digital logic circuits. CMOS technology is also used for several analog circuits such as
image sensors (CMOS sensor), data converters, and highly integrated transceivers for many
types of communication. Frank Wanlass patented CMOS in 1963 (US patent 3,356,858).

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–

semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the
typical design style with CMOS uses complementary and symmetrical pairs of p-type and n-type
metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.

Fig 4.1 CMOS INVERTER

Two important characteristics of CMOS devices are high noise immunity and low static power
consumption. Since one transistor of the pair is always off, the series combination draws
significant power only momentarily during switching between on and off states. Consequently,
CMOS devices do not produce as much waste heat as other forms of logic, for example
transistor–transistor logic (TTL) or NMOS logic, which normally have some standing current
even when not changing state. CMOS also allows a high density of logic functions on a chip. It
was primarily for this reason that CMOS became the most used technology to be implemented in
VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of

certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator,
which in turn is on top of a semiconductor material. Aluminium was once used but now the
material is polysilicon. Other metal gates have made a comeback with the advent of high-k
dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer

CMOS Inverter

CMOS circuits are constructed in such a way that all PMOS transistors must have either
an input from the voltage source or from another PMOS transistor. Similarly, all NMOS
transistors must have either an input from ground or from another NMOS transistor. The
composition of a PMOS transistor creates low resistance between its source and drain contacts
when a low gate voltage is applied and high resistance when a high gate voltage is applied. On
the other hand, the composition of an NMOS transistor creates high resistance between source
and drain when a low gate voltage is applied and low resistance when a high gate voltage is
applied. CMOS accomplishes current reduction by complementing every NMOSFET with a
PMOSFET and connecting both gates and both drains together. A high voltage on the gates will
cause the NMOSFET to conduct and the PMOSFET to not conduct while a low voltage on the
gates causes the reverse. This arrangement greatly reduces power consumption and heat
generation. However, during the switching time both MOSFETs conduct briefly as the gate
voltage goes from one state to another. This induces a brief spike in power consumption and
becomes a serious issue at high frequencies.

The figure above shows what happens when an input is connected to both a PMOS
transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of
input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current
that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and
much more current can flow from the supply to the output. Because the resistance between the
supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current
drawn from Q is small. The output therefore registers a high voltage.

On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF
(high resistance) state so it would limit the current flowing from the positive supply to the
output, while the NMOS transistor is in an ON (low resistance) state, allowing the output from
drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a
current drawn into Q placing Q above ground is small. This low drop results in the output
registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that
when the input is low, the output is high, and when the input is high, the output is low. Because
of this behavior of input and output, the CMOS circuits' output is the inverse of the input. The
power supplies for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on the
manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the
drain and source supplies. These do not apply directly to CMOS since both supplies are really
source supplies. VCC and Ground are carryovers from TTL logic and that nomenclature has been
retained with the introduction of the 54C/74C line of CMOS.

Duality

An important characteristic of a CMOS circuit is the duality that exists between its
PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to
exist from the output to either the power source or ground. To accomplish this, the set of all
paths to the voltage source must be the complement of the set of all paths to ground. This can be
easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's
laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in
series while the PMOS transistors in series have corresponding NMOS transistors in parallel are
complex logic functions such as those involving AND and OR gates require manipulating the
paths between gates to represent the logic. When a path consists of two transistors in series, both
transistors must have low resistance to the corresponding supply voltage, modeling an AND.
When a path consists of two transistors in parallel, either one or both of the transistors must have
low resistance to connect the supply voltage to the output, modeling an OR.

Fig 2.2 CMOS NAND GATE

The circuit diagram of a NAND gate in CMOS logic is shown above. If both of the A and
B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct,
neither of the PMOS transistors (top half) will conduct, and a conductive path will be established
between the output and Vss (ground), bringing the output low. If both of the A and B inputs are
low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will
conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the
output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct,
one of the PMOS transistors will, and a conductive path will be established between the output
and Vdd (voltage source), bringing the output high. As the only configuration of the two inputs

that results in a low output is when both are high, this circuit implements a NAND (NOT
AND) logic gate.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low output
transitions are fast since the pull-up transistors have low resistance when switched on, unlike the
load resistors in NMOS logic. In addition, the output signal swings the full voltage between the
low and high rails. This strong, more nearly symmetric response also makes CMOS more
resistant to noise.
 Power: switching and leakage

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates
power only when switching ("dynamic power"). On a typical ASIC in a modern 90 nanometer
process, switching the output might take 120 picoseconds, and happens once every ten
nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a
current path from Vdd to Vss through the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power
when idle. Earlier, the power consumption of CMOS devices was not the major concern while
designing chips. Factors like speed and area dominated the design parameters. As the CMOS
technology moved below sub-micron levels the power consumption per unit area of the chip has
risen tremendously. Broadly classifying, power dissipation in CMOS circuits occurs because of
two components:

Static dissipation

Sub threshold conduction will be done when the transistors are off

Both NMOS and PMOS transistors have a gate–source threshold voltage, below which
the current (called sub threshold current) through the device drops exponentially. Historically,
CMOS designs operated at supply voltages much larger than their threshold voltages (V dd might
have been 5V, and Vth for both NMOS and PMOS might have been 700 mV). A special type of
the CMOS transistor with near zero threshold voltage is the native transistor.

Tunneling current through gate oxide

SiO2 is a very good insulator, but at very small thickness levels electrons can tunnel
across the very thin insulation; the probability drops off exponentially with oxide thickness.
Tunneling current becomes very important for transistors below 130 nm technology with gate
oxides of 20 Å or thinner.
Leakage current through reverse-biased diodes

Small reverse leakage currents are formed due to formation of reverse bias between
diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-
well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold
and tunneling currents, so these may be neglected during power calculations.

Dynamic dissipation

Charging and discharging of load capacitances

CMOS circuits dissipate power by charging the various load capacitances (mostly gate
and wire capacitance, but also drain and some source capacitances) whenever they are switched.
In one complete cycle of CMOS logic, current flows from V DD to the load capacitance to charge
it and then flows from the charged load capacitance (C L) to ground during discharge. Therefore
in one complete charge/discharge cycle, a total of Q=C LVDD is thus transferred from VDD to
ground. Multiply by the switching frequency on the load capacitances to get the current used,
and multiply by the average voltage again to get the characteristic switching power dissipated by
a CMOS device:

Since most gates do not operate/switch at every clock cycle, they are often accompanied
by a factor , called the activity factor. Now, the dynamic power dissipation may be re-written

as .

A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most
data has an activity factor of 0.1.If correct load capacitance is estimated on a node together with
its activity factor, the dynamic power dissipation at that node can be calculated effectively.
The MOSFET – Metal Oxide FET
As well as the Junction Field Effect Transistor (JFET), there is another type of Field
Effect Transistor available whose Gate input is electrically insulated from the main current
carrying channel and is therefore called an Insulated Gate Field Effect Transistor or IGFET. The
most common type of insulated gate FET which is used in many different types of electronic
circuits is called the Metal Oxide Semiconductor Field Effect Transistor or MOSFET for short.
The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a
JFET in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main
semiconductor N-channel or P-channel by a very thin layer of insulating material usually silicon
dioxide, commonly known as glass.

This ultra thin insulated metal gate electrode can be thought of as one plate of a capacitor.
The isolation of the controlling Gate makes the input resistance of the MOSFET extremely high
way up in the Mega-ohms ( MΩ ) region thereby making it almost infinite.

As the Gate terminal is isolated from the main current carrying channel “NO current
flows into the gate” and just like the JFET, the MOSFET also acts like a voltage controlled
resistor were the current flowing through the main channel between the Drain and Source is
proportional to the input voltage. Also like the JFET, the MOSFETs very high input resistance
can easily accumulate large amounts of static charge resulting in the MOSFET becoming easily
damaged unless carefully handled or protected.

Like the previous JFET tutorial, MOSFETs are three terminal devices with a Gate, Drain
and Source and both P-channel (PMOS) and N-channel (NMOS) MOSFETs are available. The
main difference this time is that MOSFETs are available in two basic forms:

 1. Depletion Type   –   the transistor requires the Gate-Source voltage, ( V GS ) to switch
the device “OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed”
switch.
 2. Enhancement Type   –   the transistor requires a Gate-Source voltage, ( VGS ) to switch
the device “ON”. The enhancement mode MOSFET is equivalent to a “Normally Open”
switch.
The symbols and basic construction for both configurations of MOSFETs are shown below.
 Fig 2.3 Symbols for different types of MOSFET’S

 
The four MOSFET symbols above show an additional terminal called the Substrate and is
not normally used as either an input or an output connection but instead it is used for grounding
the substrate. It connects to the main semi-conductive channel through a diode junction to the
body or metal tab of the MOSFET. Usually in discrete type MOSFETs, this substrate lead is
connected internally to the source terminal. When this is the case, as in enhancement types it is
omitted from the symbol for clarification.

The line between the drain and source connections represents the semi conductive
channel. If this is a solid unbroken line then this represents a “Depletion” (normally closed) type
MOSFET and if the channel line is shown dotted or broken it is an “Enhancement” (normally
open) type MOSFET. The direction of the arrow indicates either a P-channel or an N-channel
device.

Fig 2.4 Basic MOSFET Structure and Symbol

 The construction of the Metal Oxide Semiconductor FET is very different to that of the
Junction FET. Both the Depletion and Enhancement type MOSFETs use an electrical field
produced by a gate voltage to alter the flow of charge carriers, electrons for N-channel or holes
for P-channel, through the semi conductive drain-source channel. The gate electrode is placed on
top of a very thin insulating layer and there are a pair of small N-type regions just under the drain
and source electrodes.

We saw in the previous tutorial, that the gate of a junction field effect transistor, JFET
must be biased in such a way as to reverse-bias the PN-junction. With a insulated gate MOSFET
device no such limitations apply so it is possible to bias the gate of a MOSFET in either polarity,
positive (+ve) or negative (-ve).

This makes the MOSFET device especially valuable as electronic switches or to make
logic gates because with no bias they are normally non-conducting and this high gate input
resistance means that very little or no control current is needed as MOSFETs are voltage
controlled devices. Both the P-channel and the N-channel MOSFETs are available in two basic
forms, the Enhancement type and the Depletion type.

2.2.1 Modes of operation:

The operation of a MOSFET can be separated into three different modes, depending on
the voltages at the terminals. In the following discussion, a simplified algebraic model is used.[9]
Modern MOSFET characteristics are more complex than the algebraic model presented here.For
an enhancement-mode, n-channel MOSFET, the three operational modes are:

Cutoff, sub threshold, or weak-inversion mode

When VGS < Vth:

where is gate-to-source bias and is the Threshold Voltage of the device.

Fig 2.5 (Example application of an N-Channel MOSFET, when the switch is pushed the LED lights
up.)
 Fig 4.6 Regions of MOSFET’S

(Ohmic contact to body to ensure no body bias; top left: subthreshold, top right: Ohmic
mode, bottom left: Active mode at onset of pinch-off, bottom right: Active mode well into pinch-
off – channel length modulation evident)

According to the basic threshold model, the transistor is turned off, and there is no
conduction between drain and source. A more accurate model considers the effect of thermal
energy on the Fermi–Dirac distribution of electron energies which allow some of the more
energetic electrons at the source to enter the channel and flow to the drain. This results in a sub
threshold current that is an exponential function of gate–source voltage. While the current
between drain and source should ideally be zero when the transistor is being used as a turned-off
switch, there is a weak-inversion current, sometimes called sub threshold leakage. In weak
inversion where the source is tied to bulk, the current varies exponentially with as given
approximately by:

where = current at , the thermal voltage and the slope factor n is

given by
with = capacitance of the depletion layer and = capacitance of the oxide layer. This
equation is generally used, but is only an adequate approximation for the source tied to the bulk.
For the source not tied to the bulk, the sub-threshold equation for drain current in saturation is

Where the is the channel divider that is given by

With = capacitance of the depletion layer and = capacitance of the oxide layer.
In a long-channel device, there is no drain voltage dependence of the current once ,
but as channel length is reduced drain-induced barrier lowering introduces drain voltage
dependence that depends in a complex way upon the device geometry (for example, the channel
doping, the junction doping and so on). Frequently, threshold voltage V th for this mode is defined
as the gate voltage at which a selected value of current ID0 occurs, for example, ID0 = 1 μA, which
may not be the same Vth-value used in the equations for the following modes.

Some micro power analog circuits are designed to take advantage of subthreshold
conduction. By working in the weak-inversion region, the MOSFETs in these circuits deliver the

highest possible transconductance-to-current ratio, namely: , almost that

of a bipolar transistor.

The sub threshold I–V curve depends exponentially upon threshold voltage, introducing a
strong dependence on any manufacturing variation that affects threshold voltage; for example:
variations in oxide thickness, junction depth, or body doping that change the degree of drain-
induced barrier lowering. The resulting sensitivity to fabricational variations complicates
optimization for leakage and performance.

Depletion-mode MOSFET

The Depletion-mode MOSFET, which is less common than the enhancement types is
normally switched “ON” without the application of a gate bias voltage making it a “normally-
closed” device. However, a gate to source voltage ( VGS ) will switch the device “OFF”. Similar
to the JFET types. For an N-channel MOSFET, a “positive” gate voltage widens the channel,
increasing the flow of the drain current and decreasing the drain current as the gate voltage goes
more negative.

In other words, for an N-channel depletion mode MOSFET: +V GS means more electrons
and more current. While a -VGS means less electrons and less current. The opposite is also true
for the P-channel types. Then the depletion mode MOSFET is equivalent to a “normally-closed”
switch.

Depletion-mode N-Channel MOSFET and circuit Symbol

Fig 2.7

 
The depletion-mode MOSFET is constructed in a similar way to their JFET transistor
counterparts were the drain-source channel is inherently conductive with the electrons and holes
already present within the N-type or P-type channel. This doping of the channel produces a
conducting path of low resistance between the Drain and Source with zero Gate bias.

2.2.3 Enhancement-mode MOSFET

The more common Enhancement-mode MOSFET is the reverse of the depletion-mode

type. Here the conducting channel is lightly doped or even undoped making it non-conductive.
This results in the device being normally “OFF” when the gate bias voltage is equal to zero.

A drain current will only flow when a gate voltage ( VGS ) is applied to the gate terminal
greater than the threshold voltage ( VTH ) level in which conductance takes place making it a
transconductance device. This positive +ve gate voltage pushes away the holes within the
channel attracting electrons towards the oxide layer and thereby increasing the thickness of the
channel allowing current to flow. This is why this kind of transistor is called an enhancement
mode device as the gate voltage enhances the channel.

Increasing this positive gate voltage will cause the channel resistance to decrease further
causing an increase in the drain current, I D through the channel. In other words, for an N-channel
enhancement mode MOSFET: +VGS turns the transistor “ON”, while a zero or -VGS turns the
transistor “OFF”. Then, the enhancement-mode MOSFET is equivalent to a “normally-open”
switch.

Enhancement-mode N-Channel MOSFET and circuit Symbols

 

Fig 2.8

Enhancement-mode MOSFETs make excellent electronics switches due to their low

“ON” resistance and extremely high “OFF” resistance as well as their infinitely high gate
resistance. Enhancement-mode MOSFETs are used in integrated circuits to produce CMOS type
Logic Gates and power switching circuits in the form of as PMOS (P-channel) and NMOS (N-
channel) gates. CMOS actually stands for Complementary MOS meaning that the logic device
has both PMOS and NMOS within its design.

The MOSFET Amplifier

 Just like the previous Junction Field Effect transistor, MOSFETs can be used to make
single stage class “A” amplifier circuits with the Enhancement mode N-channel MOSFET
common source amplifier being the most popular circuit. The depletion mode MOSFET
amplifiers are very similar to the JFET amplifiers, except that the MOSFET has a much higher
input impedance.

This high input impedance is controlled by the gate biasing resistive network formed by
R1 and R2. Also, the output signal for the enhancement mode common source MOSFET
amplifier is inverted because when VG is low the transistor is switched “OFF” and V D (Vout) is
high. When VG is high the transistor is switched “ON” and VD (Vout) is low as shown.

Fig 2.9 Enhancement-mode N-Channel MOSFET Amplifier

The DC biasing of this common source (CS) MOSFET amplifier circuit is virtually identical to
the JFET amplifier. The MOSFET circuit is biased in class A mode by the voltage divider
network formed by resistors R1 and R2. The AC input resistance is given as RIN = RG = 1MΩ.

Metal Oxide Semiconductor Field Effect Transistors are three terminal active devices
made from different semiconductor materials that can act as either an insulator or a conductor by
the application of a small signal voltage. The MOSFETs ability to change between these two
states enables it to have two basic functions: “switching” (digital electronics) or “amplification”
(analogue electronics). Then MOSFETs have the ability to operate within three different regions:

 1. Cut-off Region   –  with VGS < Vthreshold  the gate-source voltage is lower than the

threshold voltage so the MOSFET transistor is switched “fully-OFF” and I DS = 0, the
transistor acts as an open circuit
 2. Linear (Ohmic) Region   –  with VGS > Vthreshold  and VDS > VGS the transistor is in its
constant resistance region and acts like a variable resistor whose value is determined by
the gate voltage, VGS
 3. Saturation Region   –  with VGS > Vthreshold the transistor is in its constant current region
and is switched “fully-ON”. The current IDS = maximum as the transistor acts as a closed
circuit
 The Metal Oxide Semiconductor Field Effect Transistor, or MOSFET for short, has an
extremely high input gate resistance with the current flowing through the channel
between the source and drain being controlled by the gate voltage. Because of this high
input impedance and gain, MOSFETs can be easily damaged by static electricity if not
carefully protected or handled.
 MOSFET’s are ideal for use as electronic switches or as common-source amplifiers as
their power consumption is very small. Typical applications for metal oxide
semiconductor field effect transistors are in Microprocessors, Memories, Calculators and
Logic CMOS Gates etc.
 Also, notice that a dotted or broken line within the symbol indicates a normally “OFF”
enhancement type showing that “NO” current can flow through the channel when zero
gate-source voltage VGS is applied.
 A continuous unbroken line within the symbol indicates a normally “ON” Depletion type
showing that current can flow through the channel with zero gate voltage. For P-channel
types the symbols are exactly the same for both types except that the arrow points
outwards. This can be summarized in the following switching table.
 
MOSFET type VGS = +ve VGS = 0 VGS = -
 ve

N-Channel Depletion ON ON OFF

N-Channel Enhancement ON OFF OFF

P-Channel Depletion OFF ON ON

P-Channel Enhancement OFF OFF ON

 Table 2.1 switching table of MOSFET’s

 So for N-channel enhancement type MOSFETs, a positive gate voltage turns “ON” the
transistor and with zero gate voltage, the transistor will be “OFF”. For a P-channel
enhancement type MOSFET, a negative gate voltage will turn “ON” the transistor and
with zero gate voltage, the transistor will be “OFF”. The voltage point at which the
MOSFET starts to pass current through the channel is determined by the threshold
voltage VTH of the device and is typical around 0.5V to 0.7V for an N-channel device and
-0.5V to -0.8V for a P-channel device.
 In the next tutorial about Field Effect Transistors instead of using the transistor as an
amplifying device, we will look at the operation of the transistor in its saturation and
cut-off regions when used as a solid-state switch. Field effect transistor switches are used
in many applications to switch a DC current “ON” or “OFF” such as LED’s which
require only a few milliamps at low DC voltages, or motors which require higher currents
at higher voltages.

ADVANTAGES OF MOSFETS:

 Low gate signal power requirement. No gate current can flow into the gate after the small
gate
 Oxide capacitance has been charged.
 Fast switching speeds because electrons can start to flow from drain to source as soon as
the channel opens. The channel depth is proportional to the gate voltage and pinches
closed as soon as the gate voltage is removed, so there is no storage time effect as occurs
in transistors.
  MOSFET’s are small compare to BJT's so it fabricated easily and space saving scheme
on the IC's
 MOSFET's input impedance are very high so they do not load the circuits. Loading effect
doesn't arise.
 Operating frequency is very high so may be used at higher frequencies.
 Used in digital circuits for it's reliability.
 Effect of noise is less than bjt. so high signal to noise ratio.
 MOSFET’s are unipolar devices so reverse saturation current doesn't exist.
 It consumes less D.C power rather than BJT.
2.3.2 DISADVANTAGES OF MOSFET:

Handling is not easy.

MOSFET is very sensitive to electrostatic charge so it may be destroy when you touch
the pins of MOSFET devices by hand.
High resistance channels. In normal operation, the source is electrically connected to the
substrate. With no gate bias, the depletion region extends out from the N+ drain in a
pseudo-hemispherical shape. The channel length L cannot be made shorter than the
minimum depletion width required to support the rated voltage of the device.
 Channel resistance may be decreased by creating wider channels but this is costly since
it uses up valuable silicon real estate. It also slows down the switching speed of the
device by increasing its gate capacitance.
2.3.3 Applications

 Digital integrated circuits such as microprocessors and memory devices.

 Power electronics applications where each device may be switching hundreds or
thousands of watts.
 Radio-frequency amplifiers up to the UHF spectrum use MOSFET transistors as analog
signal and power amplifiers.
 Radio systems also use MOSFETs as oscillators, or mixers to convert frequencies.
ALU is a core part of computer or digital processor that executes arithmetic and logical operation, such as increment,

decrement, addition and subtraction as an arithmetic operation and AND, OR, XOR, XNOR as a logical operation. ALU is

build by using FA and multiplexer.

A. 11 Transistor Full Adder (11T FA)

FA is basic functional module for designing ALU. 11T used for design of FA, this modern
design of FA is minimize the power and reduced the delay. FA depicts in Fig. 2, circuit is
operating at power supply (VDD) 0.9V. Inputs A apply to the gate terminal of PMOS_1 and
NMOS_1, drain terminal of PMOS_2. Inputs B apply to the gate terminal of PMOS_2 and
PMOS_2, drain terminal of NMOS_1. When source voltage (VS) is greater than threshold
voltage (VTH) transistor is ON and pass the signal from gate terminal to drain terminal means
pass the gate voltage (VG) to drain terminal.
 CMOS Full Adder

Thus, when input A is high, pass the input B vice versa. FA build using low power XOR gates
and 2 is to 1 multiplexer. XOR gates gives the sum output and multiplexer responsible for carry
out (Cout). An extra transistor NMOS_6 operates in ultra-low mode using subthreshold current
and consumes low power. At strong inversion region gate to source voltage (VGS) is higher than
threshold voltage (VTH), majority carriers removed from the area of gate and minority carriers is

produced, at weak inversion region VGS is below than VTH less minority carrier is produced,
but their presence produce leakage current this current is called subthreshold current. This
current can be used when VDD is below then VTH and run the circuit at ultra-low mode and
consumes less power. 11T FA is operating at subthreshold mode by adding an extra transistor
NMOS_6.

CMOS Multiplexer
 CHAPTER-3

CMOS TERNARY LOGIC CIRCUITS

A binary number system is a number system that consists of two distinct logic levels: True (1) or
False (0). This classical two-valued system can be further extended to a multiplevalued logic
system that consists of “R” discrete logic levels, where R > 2. The different logic levels can be
represented by some signal variables like voltage, current, or charge. The set of the discrete logic
levels of an MVL device can be demonstrated by any of the two prevailing conventions:
unbalanced and balanced.

When the binary system is extended in such a

waythattheextensionisconstrainedtoonlyonedirection,the system is called an unbalanced system.
For instance, an R-bit unbalanced MVL system is represented by 0, 1, 2… (R-2), (R-1). And the
balanced system is characterized by the set of the integer numbers with the help of an odd radix
R=2K+1 such as (-K), (1-K)…-1, 0, 1…. (K-1), K [1]. The ternary logic system is one form of
multi-valued logic (MVL) system, where the value of R=3.

Following the same convention of the MVL system, the unbalanced and balanced ternary logic
system can be represented as 0, 1, 2, and -1, 0, 1. In this paper, the unbalanced ternary logic
system is implemented using a 0.9 V power supply (VDD) and 0 V as the ground potential. The
convention of the unbalanced ternary logic values and the corresponding voltage levels are
illustrated in Table 1. Basedontheoperatingprinciple,aGeneralTernaryInverter (GTI) can be of
three types: Negative, Positive, and Standard. A GTI is represented by (1), (2) and (3), where x is
the input and y0, y1 and y2 are the outputs that represent a Negative Ternary Inverter (NTI), a
Positive Ternary Inverter (PTI) and a Standard Ternary Inverter (STI), respectively [21]. The
truth table that represents the functions, y0, y1, and y2, is shown in tables.
INVERTER Figure 5 shows the design for the negative ternary inverter (NTI) and the positive
ternary inverter (PTI). For NTI, the numbers of dimmer lines (N) are 7 and 9 for the p-type and
n-type GNRFET, respectively. For PTI, the values of N are 9 and 7 for the p-type and n-type
GNRFET, respectively. Figure 6 shows the standard ternary inverter (STI) design. The circuit
topology for the inverter used here is similar to the CNTFET based inverter topology
demonstrated in [2]. However, the operating principle and techniques to achieve multiple voltage
levels are different in the proposed GNRFET
basedternaryinverter.Forexample,inCNTFETbasedternary inverter, the chirality of the CNTs are
varied to achieve different threshold voltages. On the other hand, in GNRFET, the width of the
GNRs are varied to change the threshold voltage. Here,Q1,Q2, andQ3 aren-
typetransistors,andQ4,Q5, and Q6 arep-typetransistors.ThethresholdvoltageofQ1,Q2, and Q3 are
0.24 V, 0.6 V, and 0.4 V, respectively. The threshold voltage of Q4, Q5, and Q6 are −0.4 V, −0.6
V, and −0.24 V, respectively. To obtain the specific threshold voltage, Q1 and Q6 are set to have
N = 9, Q2, and Q5 to N = 7 and Q3 and Q4 to N = 10. If the input voltage is increased from low
to high, whenitislessthan0.3V,Q5 and Q6 become ON,which makes the output voltage high. For
an input voltage within the range 0.3 V and 0.6 V, Q1 and Q6 become on, and Q3 and Q4
perform as a diode-connected load. This maintains an intermediate voltage level at the output
node. When the Input voltage reaches to a value higher than 0.6 V, Q2 becomes ON, which
brings the output voltage to a value equal to 0 V.

FIGURE 7. Transient response of NTI, PTI, and STI.

FIGURE 8. Transfer curve for GNTFET based STI.

Figure 7 shows the transient response of three different types of ternary inverters. The voltage
transfer curve for the STI is shown in Figure 8, which displays that the device is capable of
holding three discrete output voltage levels for a wide range of input voltage. Four separate noise
margins (NM) are relevant to the ternary logic circuit, and these are (i) noise margin low (NML),
(ii) noise margin low-to-medium (NMML), (iii) noise margin medium-to-high (NMMH), and
(iv) noise margin high (NMH) [30]. To estimate the robustness of the three discrete voltage
levels (logic states) of the implementedSTI,weperformedthenoisemarginanalysisusingthe
butterfly curve method, as shown in Figure 9. Butterfly curve method is a well-known approach
to determine the noise margins of logic and memory circuits. Figure 9 demonstrates that the
GNRFET based STI has reasonably high noise margins to offer stable output voltages.

B. TERNARY NAND AND NOR GATES Using the same convention used for the STI, we have
designed both ternary NAND and NOR gates. The designs for these gates are presented in
previous literature using different technologies [2]. Here, we have implemented the designs using
GNRFET. Figure 10 shows the implemented design of a ternary NAND gate and its’ logic
symbol. Figure 11 shows the design of a ternary NOR gate and its’ logic symbol. The transient
response for the ternary NAND and NOR gates are shown in Figure 12.

C. TERNARY DECODER Using the logic gates mentioned above, a ternary decoder can be
designed. The decoder is an essential part of a ternary half adder. It has one input port (X) and
three output ports (X0, X1, and X2). A ternary input voltage operates the decoder, and depending
on the input voltage level, one of the three output ports gives a high output voltage. For example,
if the input voltage is 0 V, the X0 node will show a high voltage level (Vdd). The logical relation
between the input and output ports ofthedecoderisrepresentedby(7),anditsschematicdiagram and
transient response

D. TERNARY HALF-ADDER

The ternary half adder takes two 1-trit input voltage and produces a 1-trit sum and a 1-trit carry
as the outputs. Table 5 shows the truth table of the ternary half adder. From the truth table, the
equations for the sum and carry outputs can be expressed in terms of input A and B as in (8).
Sum=2•(A0B2 +A1B1 +A2B0) +1•(A0B1 +A1B0 +A2B2) (8a) Carry=1•(A1B2 +A2B1
+A2B2) (8b)For the internal operation of the adder, different designs have been proposed in [4],
[5], and [31]. Among them, the design in [31] uses the simplest and the most efficient topology
using CNTFET. For the half adder, we have followed the topology of [31] and proposed a
simpler carry circuitry whichrequireslessertransistor.Figure14(b)demonstratesthe
proposeddiagramoftheternaryhalfadderusingourproposed
decoder.Here,thedecoderisternary,andittakesternaryinput and produces high voltage levels at the
respective output port, depending on the input voltage level. For example, for the input A=2 and
B=1, it will give full rail-to-rail voltage on A2 and B1. The second stage of the ternary half-adder
is made of binary logic gates, which receive the input signals from the ternary decoder output
nodes to generate the half-adder outputs as in (8). And the outputs of these binary logic gates
remaininbinaryform.Thethirdstageofthehalf-addercircuit is comprised of a ternary OR and a T-
buffer gate, which converts the binary signals from the second stage to ternary signals. T-buffer
is a simple circuit that acts as a level shifter. ThelogicaloperationoftheT-
bufferisasshownin(9),andthe proposedcircuitdiagramoftheT-bufferisshowninFigure15. The input-
output voltage curves of the ternary half-adder of
Figure14isshowninFigure16.Itisobservedthatthevoltage curves match the truth table exactly. Out
=1, Vin=1,2 0, Vin=0 (9).

. TERNARY MULTIPLEXER

The basic multiplexer is a device, which depending on the signal value in a particular select pin,
can transmit one of several inputs to the output port. For example, in case of a 2:1 binary
multiplexer (MUX), if the value on the select pin is 0, input-1 will be transmitted to the output,
and if the value on the select pin is 1, input-2 will be transmitted. Here, we propose the design of
a 3:1 ternary multiplexer, which can transmit any one of the 3 inputs to the output port depending
on the select pin value. And it can transmit both binary and
ternarydata.Table6showsthetruthtable,and(10)represents thelogicalexpression(input-
outputrelation)of the3:1ternary MUX.

Output =S0 A+S1B+S2C (10)

Here, the values of S0,S1, and S2 are obtained from a

ternarydecoderexplainedintheprevioussubsection.Depending on the input voltage value at the
select (S) input terminal, it passes the corresponding input signals (A, B, or C) to the output port.
The logic and schematic diagrams of the ternary MUX are shown in Figure 17, where S denotes
the select pin and A, B, and C are the three different inputs of the multiplexer. Figure 18 shows
the simulated output of the multiplexer. The voltage range in those inputs is varied in such a
manner that it can be observed that the circuit can transmit inputs of all voltage range. Here,
input A is a signal within the range 0 to 2, input B is in the range of 0 to 1, and input C is in the
range of 1 to 2. In all of the cases, the signal is passed accordingly without any significant
distortion.
 RESULTS

TERNARY INVERTER
TERNARY NAND OUTPUTS:
TERNARY NOR:
 CONCLUSION AND FUTURE SCOPE

This project presents the designs of a set of basic ternary logic gates (inverter, NAND, and NOR)
and circuits (decoder, multiplexer, and half-adder) based on GNRFET. These particular set of
basic gates and circuits are selected to establish the proposed design methodology. These basic
gates and circuits can be utilized to implement any complex logic, arithmetic, and signal
processing circuits. Here, the fundamental approach is to control the threshold voltage and other
electrical properties of GNRFETs by changing the width of the GNRs to obtain different output
levels. A comparative analysis between some of the proposed GNRFET based ternary logic gates
and circuitsandexistingdesignsisperformedintermsofdelay,leakage power, total power, and
power-delay-product (PDP). It is observed that the proposed GNRFET based ternary gates and
circuits offer significantly better results compared to similar
gatesandcircuitsbasedonCMOSandCNTFETtechnologies. The H-SPICE simulation and analysis
are performed using a GNRFET model available on Nanohub, and the channel
lengthforthedeviceisselectedtobe16nm.Theproposeddesignapproachcanbeextendedtoimplementq
uaternarylogic. However, it is essential to acknowledge that this paper is an attempt to establish
the fundamental design concept of GNRFET based ternary logic gates and circuits. Some many
issues and challenges need to be addressed before implementing more complex circuits like
ternary full adders and complete ternary application systems. Implementing ternary memory with
the proposed logic gates and circuits is another direction
thatcanbepursued.Asmemoryisthemostcriticalpartofany electronic system, increasing information
and data storage capacity while decreasing delay and power consumption are the grand
challenges for the memory designers. The ternary logic system is highly promising to resolve the
grand challenges of the memory industry. It is also important to remember that the analysis
techniques and design metrics for the MVL devices and circuits are still evolving. Our ongoing
and future work is focused on addressing some of the issues and challenges mentioned above.
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