Digital Logic (ECE 339a) Laboratory and Design Project

by Z. Kucerovsky, K.A. McIsaac and R. Eagleson Laboratory Manual and List of Assignments

University of Western Ontario Department of Electrical and Computer Engineering London, Canada

Copyright c September 2002 by Z. Kucerovsky, K.A. McIsaac and R. Eagleson

The manual was prepared to assist in meeting requirements in Digital Logic undergraduate laboratory.
A Set in L TEX 2 . Issued on September 14, 1999. Amended and reprinted in September, 2000. Electronic version amended on October 12, 2000. Amended and reprinted in September, 2001.

Distributed to those, listed in chapter 9 on page 35. This Manual is copyright under the Berne Convention. All rights are reserved. Apart from fair dealing for the purpose of private study, research, criticism or review, as permitted under the Copyright Act, 1956, no part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, electrical, chemical, mechanical, optical, photocopying, recording or otherwise, without the prior permission of the copyright owner. Trademark Notices: TEXTM is a trademark of the American Mathematical Society. Microsoft r , Windows 95 r , PowerPoint r , Project 98 r and Word r are registered trademarks of Microsoft Corporation. r is a registered trademark of Adobe Systems Incorporated. PageMaker Visio r is a registered trademark of Visio Corporation. WordPerfect r is a registered trademark of Corel Corporation. Trademarks are observed in the text of the report by capitalization of appropriate names.

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Abstract
The Laboratory Manual, which complements the courses textbook, denes the scope, content, timing and academic standards in the laboratory and design part of the course on Digital Logic. Most of the essential laboratory regulations are contained in chapter 3 on page 5. Detailed specications for the laboratory exercises and the design project are contained in separate chapters. Guidelines are included that provide information on the form and content of the laboratory reports. Although care has been taken to make the Manual reasonably accurate and helpful, it should be stressed that no document can cover all the situations encountered in engineering work. The safety issues associated with laboratory work are regulated by the appropriate safety regulations of the University, referenced in chapter 10 on page 36.

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Acknowledgments
Many faculty, sta, and graduate and undergraduate students from the Faculty of Engineering Science contributed to the content of this document, and their help is appreciated. Special thanks are due to T.E. Doyle, A. Ieta, D. Trybus and A. Weigl. The help of the Electronic Shop, especially Mr Aartsen and Kettlewell, and the Oce of the Department of Electrical and Computer Engineering, Westerns Library, and the Department of Information Technology Services has also been invaluable.

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Contents
Auxiliary Information Abstract Acknowledgments Contents List of Tables List of Figures Glossary 1 Synopsis 1.1 Calendar Description of the Course . . . . . . . . . . . . . . . . . . . 1.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Laboratory Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Introduction 2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Evaluation of the Laboratory Assignments . . . . . . . . . . . . . . . 3 General Regulations 3.1 Demonstrators . . . . . . . . . . . . . . . 3.2 Laboratory Logbook . . . . . . . . . . . 3.3 Attendance of Laboratory Sessions . . . 3.4 Submission of Laboratory Reports . . . . 3.5 Content and Form of Laboratory Report v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii iii iv v viii ix x 1 1 1 2 3 3 3 5 7 7 7 7 7

3.6 3.7 3.8 3.9

Group Laboratory and Design Projects Scholastic Oences . . . . . . . . . . . Laboratory Related Penalties . . . . . Appeals . . . . . . . . . . . . . . . . .

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8 9 9 10 11

4 Debugging 5 Lab 5.1 5.2 5.3 5.4 Breadboard Users Guide Power Supply Circuits . . . . . . Input Circuits . . . . . . . . . . . Output Circuits . . . . . . . . . . Prototyping Breadboard Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15 16 16 17 19 21 21 23 23 23 25 25 27 27 29 30 30 32 32 32 35 36 37 38 39

6 Laboratory I: Boolean Decoders 6.1 Problem Denition . . . . . . . . 6.2 Specication look-up . . . . . . . 6.3 Construction of the Truthtable . . 6.4 Minterm Expression . . . . . . . 6.5 Maxterm Expression . . . . . . . 6.6 Gate Circuit Building and Testing

7 Laboratory II: Multiplexed Digital Display 7.1 Problem Denition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Multiplexed Display of a Number . . . . . . . . . . . . . . . . . . . . 8 Laboratory III: Modulo N Counter 8.1 Problem Denition . . . . . . . . . 8.2 Specication look-up . . . . . . . . 8.3 Modulo N Counter implementation 8.4 Notes on counter design . . . . . . 9 People 10 Safety A A.1 Laboratory Kit Components and Supplies . . . . . . . . . . . . . . . A.1.1 List of Major Parts . . . . . . . . . . . . . . . . . . . . . . . . vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2 A.3 A.4 A.5

A.1.2 List of Minor Parts Digital Breadboard . . . . Digital Voltmeter . . . . . Power Supply . . . . . . . ABEL Software . . . . . .

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39 39 39 39 40 42

Bibliography

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List of Tables
6.1 Truthtable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 38

A.1 Laboratory kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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List of Figures
5.1 5.2 5.3 5.4 7.1 8.1 Overall view of the digital breadboard. . . . . . . Digital inputs available on the digital breadboard. Circuit prototyping section. . . . . . . . . . . . . Circuit prototyping section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 17 18 19 29 33

Multiplexed digital display . . . . . . . . . . . . . . . . . . . . . . . . Modulo N counter block diagram . . . . . . . . . . . . . . . . . . . .

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Glossary
ABEL: Advanced Boolean Expression Language. (p.44) AND-OR implementation of Boolean network is the architecture used to support minterm types of Boolean circuits. (p.17) Attendance of laboratory sessions: a laboratory session is taken as having been attended by a student, if the demonstrator in charge of the laboratory signs the students laboratory log book, signifying that the pre-laboratory work has been satisfactory, and if the student signs the attendance list of the laboratory session and submits an acceptable laboratory report. (p.9) BCD: binary-coded decimal. (p.24) Boolean circuits (switching circuits) are digital circuits in which the outputs Y0 , Y1 , Ym depend only on the present state of inputs X0 , X1 , Xn . (p.12) Complex Boolean circuits are digital circuits that use simple Boolean subsytem as their building blocks. (p.19) Conversion of student number to the unique problem initiation number is required so that the student can have the opportunity of solving a unique laboratory problem. (p.21,26) CSA: Canadian Safety Association. (p.44) Decoder is a Boolean circuit of the Q = (X0 , , Xn ) type, which typically generates output (Q) that depends on the set of input signals (X0 , , Xn ) (e.g. computer memory address decoder). (p.12) Design project in digital logic requires that a simple digital system be designed, built and tested. (p.29) x

Digital Logic laboratory logbook: Physics Note Book (A 90). (p.8) ECE: (Department of) Electrical and Computer Engineering (p.39) Gate: an integrated electronic circuit that implements a Boolean operator. (p.17) Group work is not allowed; each student is assigned an individual workstation in order to prepare an original submission of the laboratory report. (p.10) INT: integer part of a number (e.g. INT(3.1415) = 3). (p.31) ITS: Information Technology Services, UWO. (p.iv) Laboratory report is a succinct and accurate description of the work done in preparation for the laboratory and during the laboratory session; the report must be presented in a laboratory log book. (p.9) LED: light emitting diode. (p.30) A modulo N counter is a counter with N states in its cycle (cf. [16]). (p.24) Multiplexer is a switching circuit which allows one functional block (e.g. a display) to be time-shared among several other circuit blocks that provide the input for it. (pp.19,22,27) OR-AND implementation of Boolean network is the architecture used to support maxterm type of Boolean circuits. (p.17) Pre-laboratory work: the part of laboratory that must be prepared prior to the laboratory session. (p.10) Positive-true logic: unless otherwise specied, all exercises described in this Manual will be done using positive-true logic. (p.12) Problem initiation number: a number, linked to the student number, used to customize Digital Logic problem assignments; the number can be decimal or hexadecimal, as specied in problem denition. (pp.14,21,26) Scholastic oence is a violation of academic discipline, dened in [3]; it is subject to an academic penalty. (p.10) Sequential circuits are digital circuits in which the outputs Y0 , Y1 , Ym depend only on the present and previous states of inputs X0 , X1 , Xn . (p.24) xi

SPOS: Standard Products of Sums. (p.17) SSOP: Standard Sum of Products. (p.15) Student number: the identication number assigned to every student by the Registrar. (pp.14,21,26) Target number in the regular blackjack: the number that is the desired sum of card values in a hand. (p.29) Target number in the student blackjack: the target number is derived from the student number. (p.30) Truthtable: a table expressing each and every combination of inputs and corresponding outputs of a Boolean circuit. (p.15)

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Chapter 1 Synopsis
1.1 Digital Logic (ECE 339a): Calendar Description

Digital Logic (ECE 339a) is briey described in the Westerns Academic Calendar [2]: Theory of Boolean algebra, switching circuits, Venn diagrams; Karnaugh maps; logic and memory systems, design of combinational and sequential switching machines; electronic switching circuits; basic design of digital computers. Antirequisites and prerequisites: as listed in the course calendar. 3 lecture hours, 3 laboratory hours, half course.

1.2

Evaluation

The nal mark in the course on Digital Logic (ECE 339a) consists of the components listed in course outline [12]. The laboratory component of the course mark will be determined by the instructors using a formula that will be available to the students prior to beginning the lab. As stated in the course outline [12], students must pass the laboratory in order to obtain a passing mark in the course. During the term, a student must obtain 1

a passing mark in each of the three laboratory sessions and in the design project . Students who fail to obtain a passing mark in any of the laboratory assignments shall fail the laboratory and shall receive a nal mark not greater than 48/100. Penalties, incurred during the term shall be subtracted from the nal mark awarded for the laboratory.

1.3

Laboratory Schedule

The most up-to-date reference for the schedule and location of the laboratory sessions is the university registrars website. Please refer there for your lab and lecture times. Dates for individual labs will be updated throughout the semester by announcements from the instructors. The lab will not begin until Monday, Oct. 3.

Chapter 2 Introduction
2.1 Background

The course on Digital Logic (ECE339a) is described in the University academic calendar [2] and in the course outline [12]. The course includes two laboratory sessions dealing with combinational logic, one with sequential circuits and the nal four weeks of the course are given over to a design project. All of the laboratory assignments can be solved successfully using the lecture notes, the courses textbook [15] and the auxiliary book dealing with ABEL [13], and the Altera software included with the textbook. The rst edition of the book by Mano [10] or the second edition [11] is also fairly useful in preparing for the laboratory. Safety issues associated with laboratory work are discussed in the University occupational health and safety regulations [8][4] and Ontario Government regulations [7]. It is expected that the laboratory reports will follow the form suggested in a style manual e.g. [9][14][17]. Evaluation of the laboratory will follow the weights specied in the course outline and the regulations of the Professional Engineers Ontario [1].

2.2

Evaluation of the Laboratory Assignments

In evaluating the laboratory performance, approximately equal weight will be given to the following components: 1. theoretical content, 3

2. design component, 3. results of measurements, 4. presentation. Rules of the Laboratory, such as the attendance, submission of reports, prelaboratory preparation, etc. are outlined in chapter 3.

Chapter 3 General Regulations

Students registered in Electrical and Computer Engineering will follow the University academic regulations [2], issued annually. In addition to the university-wide regulations, the students will observe rules specic to the Department of Electrical and Computer Engineering, outlined in this document. Scheduling of laboratory sessions will be announced by the instructor during the course. As mentioned in the course outline, in some cases, computer based logic design projects may be assigned en lieu of formal laboratory attendance, however unless an explicit announcement from the instructors is received, lab assignments will be performed during scheduled lab time. In the Digital Logic Laboratory, students are given opportunity to apply the course theory and to demonstrate that they are able to work independently on projects of reasonable complexity, and that they are able to write a coherent report describing their work. To facilitate the evaluation of engineering assignments and reports, Professional Engineers Ontario (PEO), the organization chartered to regulate engineering work in Ontario, proposed that the following ve components must be discernible in a competently executed block of engineering work [1]: Introduction, objectives: Statement of the problem, clarication of need and requirements. Approach and methods: Relevant literature review. Use of suitable engineering concepts and methods. 5

 Analysis, synthesis, and testing: Use of modern concepts and methods for data gathering, testing, analysis and synthesis. Appropriateness of the inferences and deductions.

Results and conclusions: Concise statement of the outcome with recommendations as appropriate. Critical evaluation of results (discussion). Evidence that the stated objectives have been met.

Technical writing and general organization: Technical writing, English, spelling, conciseness, clarity. Cover page, index, sequence of sections, references, overall adequacy and integration of the report.

The importance of these ve components in engineering work is suggested to be approximately equal. The task of writing should not be underestimated, as it is stressed in the Faculty of Engineering Science statutory course outline clause [12]: In addition to the practical experimental and design work, in the professional life of an engineer, the manner in which oral and written communications are presented is extremely important. An engineering student must develop communication skills as an integral part of the undergraduate program. To encourage the student to do so, the grades assigned to all written and oral work will take into account all aspects of presentation including conciseness, organization, neatness, use of headings, and the preparation and use of tables and gures. It is also in accordance with the policy of the University, that the grade assigned to all written and oral work presented in English shall take into account syntax, diction, grammar and spelling. The department policy on English grammar, spelling and presentation is given in the course outline. Penalties up to a maximum of 5% for poor presentation or poor English will be deducted where applicable. Students are reminded that clarity in lab reports aids graders in determining the intent of the experimenter, and thus may ensure that credit is given for good work. Do not let bad English ruin good engineering.

3.1

Demonstrators

Work in the electrical engineering digital logic laboratory is done under supervision of demonstrators. The demonstrators also mark the laboratory reports. Most demonstrators are full-time graduate students in the Department of Electrical and Computer Engineering. It should be stressed, that demonstrators shall answer reasonable questions related to the laboratory and course problems, but they will not provide complete solutions to the laboratory assignments.

3.2

Laboratory Logbook

Each student enrolled in the course will keep an up-to-date laboratory log book. The log book suggested for use in Digital Logic is the A 90 Physics Note Book, available from the UWO Bookstore, however any permanently bound notebook is satisfactory.

3.3

Attendance of Laboratory Sessions

Attendance of the assigned laboratory sessions is compulsory. Because of a high course enrollment, it is not possible to allow the students to participate in the laboratory sessions at random or at convenience. In each of the assigned laboratory sessions, students must sign the attendance list, present to the Laboratory Demonstrator an evidence that they are prepared for the laboratory, and submit a satisfactory laboratory report on time. Penalties for absence without a valid reason are described in section 3.8 on page 9.

3.4

Submission of Laboratory Reports

Laboratory logbooks with completed laboratory reports for sessions 1, 2 and 3 are handed in at the end of each of the scheduled laboratory sessions.

3.5

Content and Form of Laboratory Report

In general, a good laboratory report comprises the following sections:

1. denition of the problem, 2. introduction and literature search, 3. analysis of the problem, 4. design part, 5. measurements, 6. discussion, 7. conclusions and recommendations, 8. references. Parts (1, 2, 3, 4 and 8) of the laboratory report shall be prepared and entered into the log book prior to the laboratory session. The pre-laboratory work will be checked by the demonstrators at the start of the laboratory session. In Part 5 (measurement), laboratory reports must demonstrate the procedures followed during the laboratory period. Ideally, this should take the form of periodic log entries (every 10-15 minutes or so), but other documentation formats may also be used. It is essential for experimenters to record problems encountered, debugging techniques attempted and solutions found. Good note-keeping, aside from being good engineering practice, will aid students in the completion of their assignments, and graders in evaluating the students performance.

3.6

Group Laboratory and Design Projects

Each student registered in ECE 339a is required to submit his (her) own laboratory reports and design project items; no collective documents are acceptable. Each of the laboratory items must be prepared solely by the presenter. Any help in producing the documents or in collecting and evaluating data, must be acknowledged. Proper references are also required when other peoples design ideas or quotes from their work are used. The presenters who fail to reference the work of others could be guilty of a scholastic oence (cf. section 3.7). Whereas collaboration on pre-laboratory work is inevitable and acceptable, photocopies of peers designs are not acceptable as pre-lab documentation.

3.7

Scholastic Oences

Engineering projects require work in the laboratory, library, and reasonable writing and communication skills. As a future member of the profession, the student is responsible for performing the required work in an honest manner, without plagiarism and cheating [2]. When in doubt how to prevent committing a scholastic oence and incurring appropriate penalty, consult the Academic Calendar [2].

3.8

Laboratory Related Penalties

The course outline contains the following warning: Abusive and/or threatening behaviour, including the use of foul language and raised voices, towards laboratory demonstrators and graders (teaching assistants) will not be tolerated. Any behaviour which in the opinion of the teaching assistant is intended to intimidate will be recorded and led with the Associate Dean Academic and may result in a grade of zero for the laboratory assignment. In addition, the following violations of laboratory discipline may incur a two mark penalty: Late arrival to the assigned laboratory session; Each time any laboratory re-submission is required or granted. The following violation of laboratory discipline may incur a two-mark penalty per day: Failure to come to the assigned laboratory session; Failure to meet the deadline for the submission of a laboratory report, design project report or design project hardware. Extensions of deadlines are seldom granted. If there are compelling reasons for an extension, a formal petition may be made in writing to the demonstrator or the course instructor. The petition must be submitted at least three days before the deadline.

Late design projects will not be accepted, unless a recommendation for a grade of Incomplete (INC) has previously been approved. In the absence of such a recommendation, a grade Fail shall be assigned for the course. Project related penalties will be accumulated throughout the year and subtracted from the nal mark at the conclusion of the project.

3.9

Appeals

If an appeal becomes necessary, it will be initiated by the student. The successive levels for appeal in ECE 339a laboratory are: 1. Demonstrator, 2. Instructor, 3. Department Chair, 4. Faculty of Engineering Associate Dean-Academic, 5. UWO Senate Review Board Academic. All levels of appeal shall be by the submission of written request. Each step of the appeal procedure should be completed as soon as possible, but not later than ten days from the date of the action or decision giving rise to the appeal. Students who repeat the course for any reason shall repeat it in its entirety, unless an exception is granted. Application for exception is to be submitted in writing to the course instructor.

Chapter 4 Debugging
By the time any student becomes eligible for ECE339a, it is expected that he or she has had some experience implementing simple software projects, and therefore, some experience nding (and xing) bugs in software programs. Debugging techniques for software include watch variables, breakpoints, single-step tracing and so on, and are generally intended to give the debugger some idea of what is going on, besides it doesnt work. Debugging techniques for digital logic circuits are analogous, and also generally intended to give the debugger some idea of what is going on. In past years, for some reason, students in ECE339a labs have forgotten all they once knew about debugging. A very common diagnosis heard in digital labs is My circuit is perfect, it just doesnt work. To avoid such confusion, this chapter presents some useful steps in the debugging process. Students are urged to use this steps, in whatever order seems appropriate to the circumstances, in order to make laboratory experiments more enjoyable for all parties. Visual inspection This is the most common debugging technique used in the lab, and one of the least useful. Visual inspection means tracing the circuit interconnections to ensure that ICs are connected as intended. In rare cases, errors are found by this technique, a common error being that there are no valid power (+5V and GND) signals connected to a given IC. Unfortunately, a disheartening number of students stop at this stage and complain that their circuit just doesnt work. In software terms, this is like reading a piece of code over and over and concluding that it looks right, so it must be right. Many possible 11

problems, including design aws, faulty logic ICs, misunderstood logic ICs and so on, will never be found by this technique, Power check The rst thing a debugger should verify is whether or not there is valid power to the system, by using a voltmeter to measure the +5V line somewhere in the circuit. It is very common for incorrectly connected circuits to shortcircuit the breadboard supply, blowing the fuse and dooming the experiment to failure until the fuse is replaced and the error corrected. If a valid +5V signal is not present, the circuit should be disconnected from the supply, and the supply tested individually. If an unloaded supply does not supply a valid +5V, then the supply fuse is likely blown. If an unloaded +5V is veried, but a loaded +5V can not be vered, then there is a low-impedance path from +5V to GND somewhere in the circuit. Test points All digital logic circuits are multi-level, which means that there are intermediary signals produced by one set of ICs which form the inputs of a second (or third, etc) set of ICs. If these intermediary signals are incorrect, then the overall output is guaranteed to be incorrect, but examination of the output circuit will not nd the problem. Debuggers should probe sensible places to nd where the fault occurs. If for example, an AND gate outputs a 0 when it should output a 1, the most likely explanation is that one of the gates inputs is a 0 when a 1 was expected. If the inputs are probed, the unexpected 0 (or 0s) will be found, and can in this way be traced backwards until the root cause of the problem is found. Modular implementation Nobody writes a program by starting on line one and writing all the necessary code until the problem is complete. Instead, standard practice is to break software into modulessmall blocks implementing simple functions that can be tested individually, and then combined to accomplish more complex tasks. Digital circuits should be implemented the same way. Experimenters should build some small piece of the circuitthe clock, for example, or a rst-level gatethen test this piece to make sure it is correct. By proceeding in this fashion, errors are found when they occur, instead of later, amid a spaghetti of leads and wires. As a secondary bonus, incremental circuit implementation allows experimenters to demonstrate partial functioning to lab

demonstrators, which in turn allows demonstrators to give grades between 100% and 0% for partially complete circuits. Proper IC functioning The laboratory kit contains a certain number of useful, standard ICs, such as multiplexers, decoders, ip-ops and so on. Students often have diculty in the lab because the operation of these ICs is not understood when circuits are designed. Common errors include inverting outputs or inputs treated as non-inverting; open-collector (open-drain) outputs used without pullup circuits; enable lines for tri-state outputs ignored, and so on. Full data sheets for the parts used in ECE339a labs are available on pages linked to the course web page at: http://www.engga.uwo.ca/People/kmcisaac/CoursePages/ECE339a.html Students are urged to examine the operation of ICs carefully when designing their circuits. A good rule of thumb is to make sure that the function of every input and every output is fully understood. It is then much less likely that important details will be neglected. Function-based debugging No amount of inspection or probing will solve circuit problems that stem from faulty design. Ideally, students will debug designs in simulation using the Altera software package before coming to the lab, so this problem should not occur. If, however, every connection seems to be correct, every IC has been wired correctly, and all tests of sub-modules seem to perform as expected, but the overall result is incorrect, then the problem is likely in design. Students should then perform function-based debugging, in which test probes are based on the specied behaviour of the circuit, not the behaviour of the circuit as designed. This style of debugging is extremely dicult and time-consuming, and points to the utility of proper pre-lab preparation. Single stepping In synchronous circuits (circuits in which time plays a role), problems are often related to the state progression of a circuit. In these circumstances, it does little good to watch a circuit operate and hope to guess at which point the error intrudes. Instead, experimenters can replace the clock circuit with a manual switch. This allows the experimenter to stop time and

observe each state transition. In this way, problems should be found quickly and easily.

Chapter 5 Lab Breadboard Users Guide

Digital circuits for ECE 339a are constructed on the digital breadboards, available in ESB-3097. Figure 5.1 is a diagrammed representation of the breadboard. This chapter presents some basic notes on using the breadboards. It is recommended that students familiarize themselves with the contents of this chapter, in order to minimize the work required in the lab.
A B C D E F GH I J K L A B C D E F GH I J K L HIGH LOW HIGH GND + 5v ON OFF + 1v - 15v METER + 1v - 15v Coarse Pulsers 11 10 9 8 7 6 5 4 3 2 1 Clock

Fine

Figure 5.1: Overall view of the digital breadboard.

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5.1

Power Supply Circuits

To supply power to the breadboard, use the toggle switch in the bottom left hand corner, labelled ON/OFF . The LED directly above this switch indicates that there is valid power in the circuit. It is advisable to wire the circuits with the power in the OFF state, and apply power when testing is to begin. There are three separate power supplies on the breadboard, of which only one is applicable in ECE 339a. Directly above the main power switch, the black and red posts labelled GND and +5v supply 5V power to digital circuits. This is the only power suitable for digital circuitry. The two other supplies (labelled 1v-15v) and the associated meter supply variable voltages and are isolated from the rest of the supporting circuitry.

5.2

Input Circuits

The most straightforward set of inputs to digital circuitry constructed on the breadboard are the inputs AL, available on the left hand side of the panel. (See Figure 5.2.) In past years, there has been a great deal of confusion related to these circuits, so this section will describe their operation in some detail. This section relies heavily on the labels given in the gure. The inputs are controlled by a set of 10 toggle switches (labelled AJ) and two pulser buttons (labelled K,L). Above each switch (or pulser) there are a grouping of eight DIP-sized holes, grouped in two rows of four. The top row supply the noninverting state of the associated switch, and the bottom two supply the inverting state. This means that when a given switch is in the HIGH state, the top row (noninverting) will be at a logic 1, and the bottom row (inverting) will be at a logic 0. When the switch changes state (toggles) to a logic LOW state, the top row will be at logic 0 and the bottom row will be at logic 1. To consider an example, suppose the logic function f (A, B) = AB is to be implemented. The simplest way to wire this circuit would be a lead from the inverting row above switch A; and a lead from the non-inverting row above switch B; both wired into a two-input AND gate. After wiring in this fashion, switch A represents the value of variable A and switch B represents the value of variable B. So, the truth table can be exercised as follows:

Toggle switches Non-inverting A B C D E F GH I J KL A B C D E F GH I J K L HIGH LOW HIGH Constant high(1) Pulsers Inverting

Figure 5.2: Digital inputs available on the digital breadboard. A B Switch A Switch B f 0 0 LOW LOW 0 0 1 LOW HIGH 1 1 0 HIGH LOW 0 1 1 HIGH HIGH 0 It is also possible, though less advisable, to use only the non-inverting versions of the inputs (to create the signal A) and an inverter chip on the breadboard to create the signal A. When constant logic 1s are required, the 16 DIP-sized hole bank labelled HIGH can be used, as well as the 5V supply line. Constant logic 0s should come from GND.

5.3

Output Circuits

The most straightforward set of outputs for digital circuitry implementation are the LED bank on the right hand side of the breadboard. (See Figure 5.3.) There are 11 usable outputs and one for the built-in CLOCK circuit. Over each LED labelled 111, there are located a set of 8 DIP-sized holes. Any of these holes can be used to

control the state of the LED. There are series resistors built in to the breadboard, so digital signals can be wired directly into the LEDs without any danger of over-current. Students should be careful to ensure that only one signal drives a given LED. If a valid logic 1 is supplied to a given LED, it should light up very clearly. A dim or hazy LED indicates a problem with the input circuitrythe signal is either toggling between two valid states, or two devices are ghting, with one trying to drive the line high while the other tries to hold it low.

LED connects

11 10 9 8 7 6 5 4 3 2 1 Clock

LEDs Coarse

Do not use

Fine

Figure 5.3: Circuit prototyping section.

There is a variable frequency clock output also available on the far right side of the breadboard. This signal is not suitable as a clock signal for ECE 339a labs because it has an extremely short duty cycle. In any case, in labs 2 and 3, design and implementation of a clock circuit is part of the assigned work.

5.4

Prototyping Breadboard Circuits

The breadboards prototyping section is diagrammed in Figure 5.4. The proto-board provides a number of built-in interconnects that can be useful for implementation, but there are some points of which students should be aware. Note that Figure 5.4 only represents half of the total breadboard. There are two identical halves which have the same operation, and are completely isolated from each other.

Outer rows No connection Y-axis No connection Inner columns

No connection X-axis

Figure 5.4: Circuit prototyping section. The top two and bottom two rows (labelled Outer rows in the gure) are usually used for power (+5V) and GND supply. These four rows are electrically connected (shorted) in the X-direction (referring to the coordinate system in the bottom left hand corner of the drawing). Note, however, that there is no connection across the central bridge (labelled no connection in the gure). Power and ground planes that are intended to cross this bridge should be wired by external leads. The remaining DIP-sized holes (labelled Inner columns in the gure) are used for individual digital signals. Each column of holes are electrically connected (shorted) in the Y direction (again referring to the coordinate system in the bottom left hand corner of the drawing). The columns above and below the large central gap (labelled no connection) are NOT electrically connected. Typical practice is to place DIP chips so that one row of pins is on each side of the large central gap. In this way, as many as four leads can be connected to each pin without diculty. It is also good

practice to place chips all facing the same way, so that identifying (counting) pins becomes as simple as possible.

Chapter 6 Laboratory I: Boolean Decoders

6.1 Problem Denition

The purpose of this laboratory assignment is to design and test two positive-truelogic Boolean decoders, which will provide output signal Q when a set of four specic input signals (A, B, C, D) is present on the input. Specically, in this laboratory exercise two standard Boolean polynomials will be constructed, analysed, minimized, and digital gate circuits will be built that would conform to the minimized Boolean expressions. The problem consists of the following parts: 1. look-up the circuit specications at http://www.engga.uwo.ca/People/kmcisaac/CoursePages/ECE339a/Lab1Specs.html 2. construction of a truth table for Qm (A, B, C, D) and QM (A, B, C, D), 3. Boolean algebra minimization of minterm expression Qm (A, B, C, D), 4. Boolean algebra minimization of maxterm expression QM (A, B, C, D), 5. construction of a Karnaugh map for Qm (A, B, C, D), 6. Karnaugh map minimization for Qm (A, B, C, D) and QM (A, B, C, D) 7. designing a gate circuit for Qm (A, B, C, D), using only NAND gates 21

8. designing a gate circuit for QM (A, B, C, D), using only NOR gates. Hint: the laboratory parts kit does not contain a 4-input NOR gate. Correctly minimized gate circuits should not either. 9. recording modules 1 - 8 into laboratory logbook, 10. building gate circuits for Qm (A, B, C, D) and QM (A, B, C, D) on the laboratory breadboard, 11. testing circuits for Qm (A, B, C, D) and QM (A, B, C, D); entering test results into the truth table, 12. completing the laboratory log book. The tasks from 1 to 9 are part of extramural pre-laboratory work, that has to be recorded in the laboratory logbook before the student is allowed to start the laboratory session. Refer to Section 3.5 for the expected form of the laboratory report. At the beginning of the laboratory session, student submits the laboratory logbook to the demonstrator, who will verify that the pre-laboratory work has been done satisfactorily. Intramural laboratory work consists of items 10, 11 and 12; the student shall assemble the circuits designed in the pre-laboratory work, test them, and shall record the results in the laboratory logbook. The intramural laboratory work of the student who has not prepared a satisfactory pre-laboratory documentation, shall not be marked. Theory related to this laboratory exercise is discussed in the textbooks by Vranesic [15], Wakerly [16], Mano [11], Pellerin and Holley [13], and in the course notes.

6.2

Specication look-up

In order to guarantee that each student performs a unique experiment, students will select the specications for their circuits from the website: http://www.engga.uwo.ca/People/kmcisaac/CoursePages/ECE339a/Lab1Specs.html This le contains a list of maxterms associated with the student number of every student registered in ECE 339a. A straightforward le search for the student number will yield the correct specications. For example, suppose student number 1234567 nds the following line in the HTML le: 123456 3 5 6 7 8 9 10 13 14 then that students assigned experiments will be to design: QM (A, B, C, D) = Qm (A, B, C, D) = M (3, 5, 6, 7, 8, 9, 10, 13, 14) m(0, 1, 2, 4, 11, 12, 15) (6.1) (6.2)

The logic functions have been chosen carefully to equalize (as much as possible) the workload required of each student.

6.3

Construction of the Truthtable

The Boolean functions associated with the maxterms found in Section 6.2 can be used to produce a truthtable of four variables Q(A, B, C, D), as shown (cf. table 6.1).

6.4

Minterm Expression

From the truthtable 6.1 a four-variable Boolean polynomial of the minterm type can be written in general as
k=F

Q(A, B, C, D) =
0

mk .

(6.3)

The values for Q(A, B, C, D), shown in truthtable 6.1 can be inserted into the general expression 6.3 to yield a set of minterms Q(A, B, C, D) = m0 + m1 + m2 + m4 + mB + mC + mF ,

Table 6.1: Truthtable k 0 1 2 3 4 5 6 7 8 9 A B C D E F A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C D 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mk AB C D AB CD ABC D ABCD AB C D AB CD ABC D ABCD AB C D AB CD ABC D ABCD AB C D AB CD ABC D ABCD Mk A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D A+B+C +D Q 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 1

that yield an SSOP expression Q(A, B, C, D) = AB C D + AB CD + ABC D + AB C D + ABCD + AB C D + ABCD which is commonly written as Q(A, B, C, D) = m(0, 1, 2, 4, B, C, F) . The SSOP expression for A(A, B, C, D) can be simplied using the axiom on complementation: Q(A, B, C, D) = AB C(D + D) + B C D(A + A) + AB D(C + C) + ACD(B + B)

which yields a minimum expression Q(A, B, C, D) = AB C + B C D + AB D + ACD (6.4)

6.5

Maxterm Expression

Similarly, from the same data, a four-variable Boolean polynomial of the maxterm type can be written as
k=F

Q(A, B, C, D) =
0

Mk .

(6.5)

The maxterm expression matching truthtable 6.1 is Q(A, B, C, D) = M3 M5 M6 M7 M8 M9 MA MD ME , which can be written as an SPOS expression: Q(A, B, C, D) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) that is often written as Q(A, B, C, D) = M (3, 5, 6, 7, 8, 9, A, D, E) . The expression can be minimized to yield several equally comlplex expressions, one of them being Q(A, B, C, D) = (A + C + D) (A + B + D) (A + B + C) (B + C + D) (B + C + D) (A + C + D) (6.6)

6.6

Gate Circuit Building and Testing

Two circuits can be built that match truthtable 6.1: 1. AND-OR architecture circuit, based on expression 6.4. Since only inverting gates are available in the laboratory kit, this circuit will have to be implemented

with a NAND-NAND structure. Fortunately, converting AND-OR circuits to NAND-NAND circuits is trivial. 2. OR-AND architecture circuit, based on expression 6.6. Since only inverting gates are available in the laboratory kit, this circuit will have to be implemented with a NOR-NOR structure. Fortunately, converting OR-AND circuits to NORNOR circuits is trivial. Both of these circuits can be tested by applying appropriate input signals A, B, C, D and measuring output Q(A, B, C, D). The results of the measurements are to be entered into the truthtable, such as the one shown (cf. table 6.1 on page 24). Minimization of Boolean expressions is discussed in [15][16][11][13] and in other books.

Chapter 7 Laboratory II: Multiplexed Digital Display

7.1 Problem Denition

The purpose of this laboratory assignment is to design and test a Boolean system, consisting of a simple encoder, multiplexer, display, and a timer. Specically, a circuit will be designed that will display alternately two assigned digits. The problem is composed of the following modules: 1. look-up the circuit specications at http://www.engga.uwo.ca/People/kmcisaac/CoursePages/ECE339a/Lab2Specs.html 2. encode the two swap values into binary numbers for implementation in the circuit. 3. design of an encoder-driver for a seven segment display. For this step, label the individual segments of the seven segment display with letters a-f, then draw a truth table for the four-input/seven-output function that maps the four-bit input number onto the seven segments a-f, showing when each segment should be lit. Since there are only two possible four-bit inputs in your circuit, there should be a large number of dont care states in this truth table. Design a circuit to implement the logic given in this truth table; 27

4. design of an encoder-driver for a seven segment display based on the 74LS47 seven-segment driver. In the implementation, either this circuit, or the previous one can be used to drive the display. If you choose to use the 7447, make sure you read the data sheet carefully before the lab. The 7447 has some interesting features that you need to understand; 5. design of a multiplexer circuit based on the 74LS257 multiplexer chip that can switch between your two four-bit numbers; 6. design of a systems clock based on the 555 timer that will time the display so that each digit is shown for one second. You may prefer either the Astable Oscillator, or 50 % Duty Cycle Oscillator modes of the LM555, both of which are covered in detail in the 555 timer datasheet, useful for this problem; 7. preparation of a laboratory report on modules (1 - 6); 8. building of the modules (2 - 6) on the laboratory breadboard; 9. testing of the system, presenting the evidence of its functionality (demonstrator signature is required); 10. completing of the laboratory log book. The tasks from 1 to 7 are part of extramural pre-laboratory work, that has to be recorded in the laboratory logbook before the student is allowed to start the laboratory session. Refer to Section 3.5 for the expected form of the laboratory report. At the beginning of the laboratory session, students submit laboratory books to the demonstrator, who will verify that the pre-laboratory work has been done satisfactorily. The intramural laboratory work consists of items 8, 9 and 10; the student shall assemble the circuits designed in the pre-laboratory work, test them, demonstrate the operation of the system to the laboratory demonstrator and shall record the results in the laboratory logbook. The intramural laboratory work of the student, who has not prepared a satisfactory pre-laboratory documentation, shall not be marked. Theory related to this laboratory exercise is discussed in the textbooks by Wakerly [16], Mano [11], Pellerin and Holley [13], and in the course notes.

7.2

Multiplexed Display of a Number

As stated earlier, the specications for problem 7 call for displaying alternately one and then the other of two assigned digits. Each of the digits is to be displayed for one second. One of the possible strategies for building a system that would meet the specications is shown in gure 7.1. (Note that this is a possible strategy. If you nd that your solution does not match the picture, that is not necessarily bad).

First digit 4

Second digit 4

8-4 multiplexer 4 7-segment display driver

Clock

Figure 7.1: Multiplexed display of two random BCD digits. As a part of pre-laboratory work, details of the system should be solved, and the systems detailed diagram prepared and recorded in the laboratory log book. During the laboratory session, the system is to be built, tested, and its functionality demonstrated. Encoders, multiplexers, displays, and timers are discussed in [16][11][13] and in other books.

Chapter 8 Laboratory III: Modulo N Counter

8.1 Problem Denition

The purpose of this laboratory assignment is to design and test a typical, simple sequential circuit, a modulo N counter, that will use either JK- or T-architecture. (Since you have only JK ip-ops in your kit, both circuits will use JK-ip-ops for implementation. Remember that it is easy to turn a JK into a T by tying the inputs together.) A Modulo N (or modulus N ) counter is a cyclic counter with N states in its cycle (cf. [16]). Specically, the modulo N counter, when driven by a clock, will go through all its states sequentially (0,1,2...,N-1), then it will reset and start its next counting cycle. The counter content will be displayed on a seven segment display and by a set of light-emitting diodes. The counters specications are available on-line. In this laboratory exercise, the counter shall be built as an up-counter. The problem solution can be divided into the following modules: 1. look-up the circuit specications at http://www.engga.uwo.ca/People/kmcisaac/CoursePages/ECE339a/Lab3Specs.html 2. design of modulo N counter for a counting sequence [repeat(0, 1, , N 1)] (modulo N and the desired architecture (T or JK) are to be found in the circuit specications from step 1 ). This implementation will be done using the J-K ip-ops provided in the laboratory kit, and should not involve a counter chip ; 30

3. design testing using the Altera software package. Students must bring evidence of a successful simulation of their design as part of their pre-lab work. 4. design of a seven segment display for the counter content; 5. design of a binary light-emitting display for the counter content; This display must use discrete LEDs available in the laboratory kit, rather than the LEDs on the breadboard 6. preparation of a laboratory report on modules (1 - 5); 7. building of the modules (2 - 5) on the laboratory breadboard; 8. testing of the counter and display, presenting the evidence of its functionality (demonstrator signature is required); 9. completing of the laboratory log book. The tasks from 1 to 6 are part of extramural pre-laboratory work, that has to be recorded in the laboratory logbook before the student is allowed to start the laboratory session. Refer to Section 3.5 for the expected form of the laboratory report. At the beginning of the laboratory session, students submit laboratory books to the demonstrator, who will verify that the pre-laboratory work has been done satisfactorily. The intramural laboratory work consists of items 7, 8 and 9; the student shall assemble the circuits designed in the pre-laboratory work, test them, demonstrate the operation of the system to the laboratory demonstrator and shall record the results in the laboratory logbook. The intramural laboratory work of the student, who has not prepared a satisfactory pre-laboratory documentation, shall not be marked. Theory related to this laboratory exercise is discussed in the textbooks by Brown and Vranesic [15] (especially Chapter 7), Wakerly [16], Mano [11], Pellerin and Holley [13], and in the course notes.

8.2

Specication look-up

In order to guarantee, as much as possible, that each student performs a unique experiment, students will select the specications for their circuits from the website: http://www.engga.uwo.ca/People/kmcisaac/CoursePages/ECE339a/Lab3Specs.html This le contains a list of modulus numbers and architectures associated with the student number of every student registered in ECE 339a. A straightforward le search for the student number will yield the correct specications. For example, suppose student numbers 123456 and 9876543 nd the following lines in the HTML le: 123456 B JK 987654 9 T then student 123456 is required to design a Mod-B counter using a JK architecture, and student 987654 is required to design a Mod-9 counter using T architecture. NOTE: The 7447 DOES NOT gracefully handle inputs greater than 9, but rather outputs error codes. Those of you who are assigned moduli greater than 10 will observe these funny looking codes. They do not necessarily indicate an incorrect circuit.

8.3

Modulo N Counter implementation

As stated earlier, the specications for problem 8 call for building an up-counter with two displays: a seven segment, and a binary-coded LED type. The system is shown in gure 8.1. The number of ip-ops is determined by the modulo N . As a part of pre-laboratory work, details of the system are to be solved, and the systems detailed diagram prepared and recorded in the laboratory logbook. During the laboratory session, the system is to be built, tested, and its functionality demonstrated. Counters and sequential circuits are discussed in [16][11][13] and in other books.

8.4

Notes on counter design

There are, in principle, two ways to design a counter (see Chapter 7 of Brown/Vranesic):

Counter circuit Clock Flip-flops Combinational logic 4 7-segment display driver

LED circuit

Figure 8.1: Block diagram of a modulo N counter with a seven segment and a light emitting diode displays. 1. Asynchronous (ripple) counters use the inverse of lower-order bits to clock higher order bits 2. Synchronous counters use a common clock for all bits, and simple circuitry on the ip-op control inputs to determine when bits switch. There are also, in principle, two ways to design the reset circuitry needed to implement a Modulo-N counter: 1. Asynchronous reset uses a RESET signal connected to the asynchronous reset inputs to clear the individual ip ops 2. Synchronous reset uses a synchronous pre-load value to load a zero onto the ip-ops at the next clock edge There are, therefore, in principle, four ways to design the circuit required in this lab. Evaluation will be as follows: 1. Asynchronous counters with asynchronous resets. This is the simplest style of circuit. However, this style of circuit contains race conditions which makes it highly unlikely ever to succeed after implementation. In addition, circuits designed according to this specication will not function correctly when simulated

in the Altera software package. As a result, this style of design is highly inadvisable, and students choosing it should not expect to get full (or even passing) marks for this experiment. 2. Synchronous counters with asynchronous resets. This is the standard style of circuit and can be implemented for full marks. It requires only slightly more work than the previous case, and whereas it does contain a glitchy condition, that is acceptable for the purposes of this experiment. Note, however, that the nal circuit must display Modulo-N counting. In other words, all the expected digits must be visible on the display. This should give a hint towards handling the glitchiness. T- and JK-architecture circuits of this type are expected to be identical. 3. Asynchronous counters with synchronous resets. It makes no sense to speak of a circuit of this style, and implementation of such a circuit would be highly dicult (if not impossible), and certainly contain race conditions. Students are not advised even to attempt this. 4. Synchronous counters with synchronous reset. This is ideally the type of circuit students should be designing in this lab, and correct implementation of such a circuit will be worth 1 bonus mark. Once again, the nal circuit must display Modulo-N counting. Also, in this case, the expected T- and JKarchitecture circuits are not identical, although both involve similar levels of diculty.

Chapter 9 People
A list is attached of the people who are in charge of various aspects of the Electrical Engineering Project during the current school year. All of them are located on the Campus, most of them in the Engineering Science Building. Mr. Aartsen, Supervisor, FE Electronic Shop. Prof. Knopf, Associate Dean-Academic, FE. Mr. Hood, Safety Ocer, UWO. Prof. McIsaac, Course Instructor (ECE339a). Prof. Reyhani-Masoleh, Course Instructor (ECE339a),

35

Chapter 10 Safety
Usually there are no substantial safety problems associated with laboratory work in digital logic. All laboratory tasks require a degree of judgement, and it is most important not to put anyone involved in such work to an unreasonable degree of risk. However, laboratory work in general involves a measure of personal risk. Caution should be used when working with high voltage power supplies, sources of radiation, compressed gases and various machines. A person that feels uncomfortable using unfamiliar equipment should seek help and should not try to solve problems by trial and error. A brief version of the Ontario regulations regarding the occupational health and safety is contained in reference [7]. The University safety regulations are summarized in reference [4] and the laboratory safety is covered in the University document Laboratory and Safety Manual for General Laboratory Practices [8]. The Safety Manual deals with basic safety including electrical equipment and apparatus, hazardous materials, hygiene practices and emergency equipment and procedures. The manual denes electrical equipment as any equipment which operates with or from a power supply of thirty volts or greater. It is stressed that all electrical equipment currently in use at the University must meet the provisions of the Power Commission Act of Ontario. All new equipment at the University must be approved by either the Canadian Standards Association or Ontario Hydro, Electrical Inspection Department. It is permitted to construct an electrical system for research or instruction on the University premises, but the system must be comprised of components that comply with the Electrical Equipment Policy of the University. 36

Appendix A

37

A.1

Laboratory Kit Components and Supplies

A laboratory kit of parts, needed in Digital Logic laboratory and design sessions, is provided by the Electronic Shop at nominal cost. The kit will be available from room 15 in the Engineering Science building during the oce hours; care should be taken to secure the kit prior to the rst scheduled laboratory session. The cost of the year 2000 kit is $ 45. Most of the parts contained in the kit are classied as major (cf. section A.1.1); however, some essential minor parts (cf. section A.1.2) are also included.

5 74LS132N 5 74LS00N 5 74LS02N 5 74LS04N 4 74LS10N 4 74LS20N 4 74LS27N 3 74LS47N 2 74LS73N 1 74LS283N 2 74LS257N 2 LM555N 2 LTS 312 AR 4 LTL-4233 4 LTL-4213 2 10 F/25 V 30 470 1/4 W

Table A.1: List of parts in Laboratory Kit quad NAND Schmidt trigger quad binary NAND quad binary NOR hex inverter triple 3-input NAND dual 4-input NAND triple 3-input NOR seven segment driver dual JK ip-op binary adder multiplexer timer seven segment display green LED red LED capacitor resistors

Functional equivalents of the major parts may be used. Detailed data sheets of the parts are available from the TTL index web site at: http://mwd.ee.qub.ac.uk/DataSheet/Down_Load/74%20TTL%20Series/

and other on-line resources, in the Electronics Shop, Engineering Science Resource Centre, and the Digital Logic Laboratory.

A.1.1

List of Major Parts

Integrated circuits and more complex and expensive parts are classied as major. A minimum of major parts should be used in the design.

A.1.2

List of Minor Parts

Diodes, transistors, resistors, capacitors, potentiometers.

A.2

Digital Breadboard

Manufacturer: Electronic Shop, FES.

A.3

Digital Voltmeter

It is recommended that students obtain a simple digital voltmeter and bring it to each of the laboratory and design sessions.

A.4

Power Supply

Power supply is incorporated into digital breadboard (cf. section A.2) provided by the Department. Other power supplies may be used, provided they meet the CSA specications (cf. chapter 10, page 36).

A.5

ABEL Software

ABEL is acronym for Advanced Boolean Expression Language, which is described in a book by Pellerin and Holley [13] and in [16].

Bibliography
[1] Anon. Engineering report appraisal. Professional Engineers Ontario, 1994. [2] L. Chalomer, editor. Academic Calendar. The University of Western Ontario, London, ON, January 1999. [3] L. Chalomer, editor. Academic Calendar. The University of Western Ontario, London, ON, January 2000. [4] Department of Occupational Health and Safety. Occupational Health and Safety Guide for Supervisors. The University of Western Ontario, London, ON, 1996. [5] Ian Fleming. Casino Royale. J. Cape, London, 1953. [6] Dick Francis. Comeback. Michael Joseph, London, 1991. [7] Laboratory Safety Committee. Pocket Ontario Occupational Health and Safety Act and Regulations. Carswell, general edition, 1994. [8] Laboratory Safety Committee. Laboratory Health and Safety Manual for General Laboratory Practices. The University of Western Ontario, September 1997. [9] Beth Luey. Handbook for Academic Authors. Cambridge University Press, Cambridge, U.K., revised edition, 1991. [10] Morris M. Mano. Digital Design. Prentice Hall, New York, rst edition, 1984. [11] Morris M. Mano. Digital Design. Prentice Hall, New York, second edition, 1991. [12] Department of Electrical and Computer Engineering. Digital logic (ece339a). Course Outline, 2000. [13] David Pellerin and Michael Holley. Digital Design Using ABEL. Prentice Hall, New York, 1994. 41

[14] Kate L. Tourabian. A Manual for Writers of Term Papers, Thesis, and Dissertations. The University of Chicago Press, Chicago, IL, third, revised edition, 1970. [15] Stephen Brown and Zvonko Vranesic Fundamentals of Digital Logic with VHDL Design McGraw-Hill, Toronto, 2000. [16] John F. Wakerly. Digital Design: Principles and Practices. Prentice Hall, Upper Saddle River, N.J., 3rd, new edition, 2000. [17] Roy McKeen Wiles. Scholarly Reporting in Humanities. University of Toronto Press, Toronto, ON, fourth edition, 1968.