Oscilador RF
Oscilador RF
Oscilador RF
9GG C j0
Cj (9)
0 0 [1 (Vctrl Va ) / VB ]n
1 n
1
1
§ Vctrl Va ·
KVCO L C 2 2
¨1 ¸ (10)
4S VB
j0
© VB ¹
&YDU &YDU
making C j 0 3 pF , VB
0.5V , Va 0V , L 1nH and
n 1 / 2 ˈthe relationship between KVCO and Vctrl is depicted
0 0
by Fig.4 which shows the gain decrease rapidly as the
control voltage increasing from zero. That deteriorates the
,WDLO
linearity of the system.
B. Use of HBT
NPN heterojunction bipolar transistor (HBT) is used to
replace the NMOS in Fig.3 for its high characteristic
frequency, low 1/f noise, low flicker noise and
thermal noise[3]. And the NPN HBT has a larger
transconductance at a common bias, especially makes the
whole circuit have a lower phase noise in the case of small
power consumption.
C. Linearization of LC-tank
The gain of the VCO is a significant parameter which
shows relationship between varition of frequency and control Figure 4. Relationship between gain and control voltage.
voltage. It is ideally needed invariable to make the system as
linear as possible. In the LC-tank, the resonant frequency is 9FWUO
9D 9D
&Y &Y
1
fosc (6)
2S LC &Y 5 &Y
It is necessary to make the KVCO Vctrl curve more
smooth to improve the linearity of VCO.A new structure id2T 0 ig2 0
ig2 id2T
showed in Fig.5 is designed for the capacitor of the LC-tank.
There are eight variodes in this differential structure, each
half has four variodes in parallel. The symmetric center is
AC ground, so the capacitance is
Figure 7. Noise model of MOS.
C CV 1 CV 2 CV 3 CV 4 (11)
A. Noise of the PMOS
Beside CV 1 , the control voltage of CV 2 , CV 3 and CV 4 is According to the noise model of MOS shown in Fig.7,
divided by the resistors. There are the noise of PMOS is consisted of local thermal noise and
gate noise, they are .
R R1
Vc 2 Vctrl (12) 2kT JPCOX I bias W
R
2
idT / 'f (16)
gm L
R R1 R2
Vc 3 Vctrl (13) 2kT GZ 2 Cgs2 g m L
R ig2 / 'f (17)
R R1 R2 R3 5I bias uCOX W
Vc 4 Vctrl (14)
R
where k is Boltzmann constant, T is absolute temperature, J
According to (10), KVCO yields is a constant 2/3 for long-channel and 2-3 for short-channel
and G is two times of J . So noise of each PMOS is
1 12 32 § wCV 1 wCV 2 wCV 3 wCV 4 ·
KVCO L C ¨ ¸ (15) 2
idT ig2
4S © wVctrl wVctrl wVctrl wVctrl ¹ iM2 / 'f (18)
'f 'f
where C CV 1 CV 2 CV 3 CV 4 , each CV can be derived
According to Thevenin’s theorem, the noise from the
from (9). Making VB 0.5V , Va 0V , L 1nH ,
differential structure composed of two PMOS is given by
n 1/ 2 and C j 0 0.75 pF ( just one fourth of Fig.3 to make
the two structure have the same capacitance with zero bias. 1 iM2 i2 1 iM2
Applying different ratios of resisters, the results are shown in iP2 / 'f ( M) (19)
Fig.6. It is obvious that a large ratio of resisters leading to a 4 'f 'f 2 'f
more smooth curve which means a better linearity. But this
benefit is abtained by sacrificing range of frequency-tuning
in fact. B. Noise of NPN HBT
& &
4 4
iR2 iR2
iO2 / 'f 5 'f 'f 5 iin2 iO2 / 'f
iin2
'f
'f
9ELDV 9ELDV
Figure 6. KVCO Vctrl Curve with diferent ratios of resisters. The noise model of NPN HBT is established as shown in
Fig.8.In this model there is a current noise of each NPN
III. NOISE OF THE VCO Z
2
where Z is impedance between emitter and base, at the same noise model can be transformed to a capacitor connected to
time there are noises coupled into collector by C1 or C2 a resistor in series. And it is given by
iin2 i2 4kT 2
vCV / 'f 8kT 1
ic2 / 'f R 2qI B (21) 2
iCV / 'f 2 ˄RCS ˅(24)
'f 'f R 2
RCP RCP (ZCV ) 2 RCP
Similar to the analysis of section A, the noise from the where RCP is resistor in parallel and RCS is resistor in series.
differential structure composed of two NPN HBTs is given So the noise of LC-tank is
by
iL2 i2 (25)
k / 'f 4 CV
2
itan
1 i
2
i
Q1
2
Q2 1 i i 2 2 'f 'f
i2
NPN / 'f ( ) ( ) o c
(22)
4 'f 'f 2 'f 'f
D. Noise of the Whole Structure
According to Hajimiriÿs phase noise theory[6,7,8], the
C. Noise of LC-tank
single band phase noise at f off offset in 1 / f 2 region is
The noise model of LC-tank is established as shown in
Fig.9.The LC-tank is made up of variodes, inductors and
* 2rms ¦ in / 'f
2
resistors. In this model the noises from variodes and L{ f off } 10 log( ) (26)
inductors are considered, the noise from resistors shown in 8S f off
2 2 2
qmax
Fig.5 is ignored because they are connected to AC ground.
The noises of inductor [4] are mainly from the thermal cost where *rms | 1/ 2 for differential noise sources and qmax is
of the coils and the thermal cost of between coils and the maximum charge of the capacitor. Substituting the
substrate former formula in (26) with results of section A, B and C ,
there is
ª 1 1 º
iL2 / 'f 2
2(iLP / 'f iLS
2
/ 'f ) | 8kT « » (23) 2
R
¬ P ( LZ ) 2
/ RS ¼
itan i2 i2
¦i 2
n / 'f k
'f 'f
P NPN
'f
(27)
RP
2
iLP / 'f 2
iLP / 'f RP
The parameters of this design is shown in Table I when
control voltage is set as 2.5V. Making these parameters in
the noise model, the results of each part is abtained as shown
L RS
2
iLS / 'f 2
iLS / 'f RS L
by table II. From Table II, it shows the noise caused by
differential pairs accounts for 80 percent. So the PMOS and
the NPN play an important role in the design, it is significant
CV 1 2
RCS 1 iCV 1 / 'f
2
iCV 1 / 'f RCS 1 CV 1 to use a suitable device such as HBT to decrease the noise.
At the same time, the noise from the gate of PMOS, the noise
coupled to collector of NPN by capacitor and the noise of
CV 2 2
RCS 2 iCV / 'f 2
iCV / 'f RCS 2
variode is much smaller than others. Therefore the phase
CV 2
noise can be calculated approximatively by
CV 3 2
RCS 3 iCV 3 / 'f
2
iCV 3 / 'f RCS 3 CV 3 * 2rms kT JPCOX I bias W 4kT 4kT
L{ f off } 10log{ (
4S f off2 qmax
2 2
gm L RP ( LZ )2 / RS
2
g m2 npn Z ª¬ 2kT (rb R) qI B (rb R) 2 º¼
4 / 'f 4 / 'f RCS 4
2 2
CV 4 RCS 4 iCV iCV CV 4 qI c )} (28)
2
Z rb R
Figure 9. Noise model of LC-tank.
The phase noise calculated by (28) is depicted in Fig.10
where RSP is equivalent resistor in parallel, RS is equivalent compared with the result simulated by spectreRF of cadence
using TSMC 0.35μm SiGe BiCMOS technology. In the
resistor in series and QL is the quality factor of inductor. The simulation, the output frequency sweep range is set from
variode is simulated by a capacitor and a resister in parallel. 10KHz to 1GHz. The result shows the calculation and
Because the quality factor of variode is much larger than the simulation are very approximate within 100MHz offset in
quality factor of inductor, the influence caused by capacitor which the phase noise is -109.1 dB at 1MHz offset just
noise is much smaller than inductor noise [5] , the variode 0.81% less than the value got from simulation.That means
the noise model of this work is mostly availiable, and the
difference value increasing in the large offset range may be IV. REALIZATION OF VCO
due to ignoring some noise source in the model. The circuit of VCO is realized using TSMC 0.35μm SiGe
TABLE I. PARAMETERS OF THIS DESIGN BiCMOS technology as shown in Fig. 11. Q5, Q6 and Q9
work as current mirror to supply Q1 and Q2 DC bias. Q3, Q4,
Parameter Value Q7 and Q8 work as output buffer. C3 shorts AC signal which
Parameters of oscillation frequency f 5.33 GHz may interfere Q6 to ground. The transient simulation
VCO depicted in Fig. 12 shows that the VCO can start self-
Bias current Ibias 871P A
oscillating in 4.5ns and output a steady waveform. Fig. 13
Amplitude of output 0.39 V depicts the relationship between frequency and control
Parameters of gm 3.13 mS voltage when different resistor ratio applied that leads to
PMOS W/L 80 um/350 nm different capacitance and gain shown in Part C of Section 2.
Cox 4.45 fiF/um2 And the simulation of phase noise is shown in Fig. 14 from
Cgs 77.22 fiF which the phase noise is got as -110dB at 1MHz offset.
According to the figure of merit (FOM) substituting the
Parameters of CS 70.34 fiF formula in (28) with former parameters, the FOM of this
NPN HBT
rb 35: design is -180dBc/Hz which means a good performance [9].
The layout is shown in Fig. 15.
E 199
Parameters of L 1.14 nH
inductor f OSC P
RS 2.46: FOM ( f offset ) L( f offset ) 20 lg 10 lg diss (29)
3.27 k:
f offset 1mW
RP
Parameters of CV 1 , CV 2 , CV 3 , CV 4 54.36 57.08 60.16
variodes 63.66 ( fiF )
9GG
0 0
RCP 244 M:
4
/ /
&Y 4
TABLE II. NOISE OF EACH PART 5
&Y
&Y 5
noise 2
idT / 'f ig2 / 'f io2 / 'f ic2 / 'f 5
&Y
&Y
5
Value 3.046 1.208 2.818 2.357 &Y
&Y
,ELDV
×10-22 ×10-24 ×10-22 ×10-24
( A / Hz )
2 5 &Y & &
Figure 13. Relationship between frenquency and control voltage.
Figure 14. Phase noise.
[3] Harame D, Ahlcrev D㸪et al. Current Status and Future Trends of
V. CONCLUSION SiCe BiCMOS Technology. IEEE Trans on Electron Devices, 2001,
This paper has introduced an efficient VCO for low 48(11):2575-2594.
voltage-supply, low power consumption, low phase noise [4] Thomas H. Lee. The Design of CMOS Radio-Frequency Integrated
Circuits Second Edition (Second edition㸪translated by Zhiping Yu
and large tuning range application. The circuit is designed and Runde Zhou), Beijing:Publishing House of Electronics Industry,
based on TSMC 0.35μm SiGe BiCMOS process. The center 2006, 88-113,505-528.
frequency of VCO is 5.5GHz and oscillation frequency [5] Maria del Mar Hershenson, Ali Hajimiri. Design and optimization of
range is from 5.1 GHz to 5.9 GHz, that means tuning range LC oscillators. Computer-Aided Design, Digest of Technical Papers.
is 14.5 %. With a supply voltage of 3.3 V, the dc power 1999: 65 - 69 .
consumption is 2.9 mW. The phase noise is -110 dBc/Hz at [6] Ali Hajimiri, Thomas H. Lee. A General Theory of Phase Noise in
lMHz offset and FOM is -180dBc/Hz. Electrical Oscillators. IEEE Journal of Solid-State Circuits, 1998, Vol.
33, No. 2:179-194.
REFERENCES [7] Ali Hajimiri, Thomas H. Lee. Corrections to “A General Theory of
Phase Noise in Electrical Oscillators”. IEEE Journal OF Solid-State
[1] Craninckx J, Steyaert M㸬Low-noise Voltage Controlled Oscillators Circuits, 1998,Vol. 33, No. 6:928.
Using Enhanced LC-tanks 㸬 IEEE Trans 㸬 Circuits Syst, II,
1995:794-804 [8] Lei Lu, Zhangwen Tang, Comments on “Comments on “A General
Theory of Phase Noise in Electrical Oscillators””. IEEE Journal of
[2] Thomas H. Lee, Ali Hajimiri㸬Oscillator Phase Noise: A Tutoria1. Solid-State Circuits, 2008, Vol. 43, No. 9:2170.
IEEE Journal of Solid-State Circuits, 2000, Vol. 35, No. 3:326-336.
[9] HuangYinkun, WuDanyu , ZhouLei, JiangFan,WuJin and JinZhi. A
23 GHz low power VCO in SiGe BiCMOS technology. Journal of
semiconductors, Vol. 34, No.4, pp.76-79, April 2013.