Department of Electrical Engineering

Faculty Member:____________________ Dated: ________________

Semester:__________________________ Section: ________________

Group No.:

EE-221: DIGITAL LOGIC DESIGN

LAB 6: BINARY TO GRAY AND GRAY TO BINARY CODE
CONVERSION

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7

Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performanc of data in Tool Usage Safety and Team marks
e Lab Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

EE-221: Digital Logic Design Page 1

 LAB6: PART (A): BINARY TO GRAY AND GRAY TO BINARY CODE CONVERSION

LAB6: PART (B): GATE-LEVEL MODELING IN VERILOG

This Lab has been divided into two parts:

In first part you are required to design and implement a binary to gray and gray to binary code
converter. You will be cascading these two converters thus implementing a binary to gray coder
and decoder (gray to binary).

The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
lab.

Objectives:

 Understand steps involved in design of combinational circuits

 Understand binary codes for decimals and their hardware realization
 Write code for combinational circuits using Verilog Gate Level Modeling

LAB INSTRUCTIONS

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The students will get
hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with
teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab
report on LMS for grading.
 The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
 Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
 The students will complete lab task and submit complete report to Lab Engineer before leaving
lab.
 The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per day
will be done for late submission.
 A lab with in-complete lab tasks will not be accepted.
 There are related questions at the end of this activity. Give complete answers.

EE-221: Digital Logic Design Page 2

 PRE-LAB TASKS: (TO BE DONE BEFORE COMING TO THE LAB) (2 MARKS)

WHAT DO YOU MEAN BY BINARY CODES FOR THE DECIMAL DIGITS? GIVE SOME EXAMPLES AND CODES (TABLES)
FOR THE DECIMAL DIGITS.

ANSWER

In the coding, when numbers, letters or words are represented by a specific group of symbols, it is said that
the number, letter, or word is being encoded. The group of symbols is called as a code. The digital data is
represented, stored, and transmitted as group of binary bits. This group is also called as binary code. The
binary code is represented by the number as well as alphanumeric letter.

DECIMAL BCD EXCESS-3

8421
0 0000 0011
1 0001 0100
2 0010 0101
3 0011 0110
4 0100 0111
5 0101 1000
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100

WHAT IS A SELF-COMPLEMENTING CODE? NAME ANY TWO OF THEM; SHOW THEIR COMPLEMENTING NATURE
WITH EXAMPLES AND DESCRIBE ADVANTAGES.

ANSWER
Self-Complementing Codes are those codes which have the property that 9’s complement of decimal number is directly obtained by
replacing 1 by 0’s and 0’s by 1’s. This means complementing each bit of the pattern. The example self-complementing codes are: The
2421, the excess‐3 and the 84-2-1 codes are examples of self‐complementing codes.

DECIMAL
2421 EXCESS-3
0 0000 0011
1 0001 0100
2 0010 or 1000 0101
3 0011 or 1001 0110

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 4 1010 or 0100 0111
5 0101 or 1011 1000
6 1100 or 0110 1001
7 1101 or 0111 1010
8 1110 1011
9 1111 1100

IN THE LAB YOU WOULD BE IMPLEMENTING A GRAY TO BINARY AND BINARY TO GRAY CODE CONVERTER. MAKE A
TRUTH TABLE FOR BOTH THE CODES BY FILLING IN THE FOLLOWING TABLES AND SIMPLIFY THE EXPRESSIONS FOR
W, X, Y, Z IN TERMS OF A,B,C,D AND VICE VERSA.( USE BACKSIDE OF THE PAGE IF NECESSARY). ALSO GIVE SOME
APPLICATIONS IN WHICH GRAY CODE COULD BE USED.

BINARY TO GRAY CODE CONVERTER:-

TABLE:

Dec Binary Gray

HINT:
A B C D W X Y Z
Our inputs and outputs are of 4-bit each. You
0 0 0 0 0 0 0 0 0 will have to make 4 K-Maps (Consider W as
independent function of A,B,C,D, Make K-Map
1 0 0 0 1 0 0 0 1 and simplify it). Arrive at the simplest
expression for each output.
2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 0 1 0

4 0 1 0 0 0 1 1 0 Final Boolean Equation after using K-

5 0 1 0 1 0 1 1 1 map
W= A
6 0 1 1 0 0 1 0 1
X= A’B + AB’ , or we can say X= A xor B
7 0 1 1 1 0 1 0 0 Y= B’C + BC’ , or we can say Y= B xor C

8 1 0 0 0 1 1 0 0 Z= C’D + CD’ , or we can say Z= C xor D

9 1 0 0 1 1 1 0 1

10 1 0 1 0 1 1 1 1

11 1 0 1 1 1 1 1 0

12 1 1 0 0 1 0 1 0

13 1 1 0 1 1 0 1 1

14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
EE-221: Digital Logic Design Page 4
GRAY TO BINARY CODE CONVERTER:

TABLE:

Dec Gray Binary HINT:

W X Y Z A B C D Our inputs and outputs are of 4-bit each. You

will have to make 4 K-Maps (Consider A as
0 0 0 0 0 0 0 0 0 independent function of W,X,Y,Z. Make K-Map
and simplify it). Arrive at the simplest
1 0 0 0 1 0 0 0 1 expression for each output.

2 0 0 1 1 0 0 1 0

3 0 0 1 0 0 0 1 1
Final Boolean Equation after using K-
4 0 1 1 0 0 1 0 0 map:
A= W
5 0 1 1 1 0 1 0 1
B= W’X + WX’ or B= W xor X
6 0 1 0 1 0 1 1 0
C= Y’B+YB’ or C= Y xor B
7 0 1 0 0 0 1 1 1 D= Z’C + Z’C or D= Z xor C
8 0 1 0 0 1 0 0 0

9 1 1 0 1 1 0 0 1

10 1 1 1 1 1 0 1 0

11 1 1 1 0 1 0 1 1

12 1 0 1 0 1 1 0 0

13 1 0 1 1 1 1 0 1

14 1 0 0 1 1 1 1 0

15 1 0 0 0 1 1 1 1

EE-221: Digital Logic Design Page 5

Draw the logic diagram for the Binary-to-Gray and Gray-to-Binary code converters using Exclusive-OR gates in the space
provided below.

Binary Gray Binary

A
W A

B
X B

C
Y C

D
Z D

Only the following gates are available to you for lab tasks.

EE-221: Digital Logic Design Page 6

Lab Tasks: (To be completed in the lab) (3 marks)
Lab Task 1:

Now cascade the two circuits in series by connecting the outputs of binary-to-gray converter to the inputs of the gray-to-
binary converter. You should be able to get the binary input at output as well. Show the results to your Teacher/Lab Engr.
Use LEDs to show input-output relationship.

//Add the pictures

Lab Task 2:

Binary to Gary using Nand Gates.

EE-221: Digital Logic Design Page 7

Lab Task 3:

Design and simulate the gate-level model of the circuit you patched in task 3. Give the code in the space provided below.
Code:
module BGB(OutputA, OutputB, OutputC, OutputD, W, X, Y, Z, A, B, C, D);

input A, B, C, D;
output OutputA, OutputB, OutputC, OutputD, W, X, Y, Z;

wire w1, w2, w3;

// Converting Binary to Gray

buf b1(W, A);

buf b2(OutputA, A); //Bit of gray to binary

xor x1(w1, A, B);

buf b3(X, w1);

xor x2(w2, B, C);

buf b4(Y, w2);

xor x3(w3, C, D);

buf b5(Z, w3);

// Converting Gray to Binary

xor x4(OutputB, A, w1);

xor x5(OutputC, OutputB, w2);
xor x6(OutputD, OutputC, w3);

endmodule

module testbench();
reg A, B, C, D;
wire OutputA, OutputB, OutputC, OutputD, W, X, Y, Z;

EE-221: Digital Logic Design Page 8

 BGB t1(OutputA, OutputB, OutputC, OutputD, W, X, Y, Z, A, B, C, D);

initial begin
#100ns A = 0; B = 0; C = 0; D = 0;
#100ns A = 0; B = 0; C = 0; D = 1;
#100ns A = 0; B = 0; C = 1; D = 0;
#100ns A = 0; B = 0; C = 1; D = 1;
#100ns A = 0; B = 1; C = 0; D = 0;
#100ns A = 0; B = 1; C = 0; D = 1;
#100ns A = 0; B = 1; C = 1; D = 0;
#100ns A = 0; B = 1; C = 1; D = 1;
#100ns A = 1; B = 0; C = 0; D = 0;
#100ns A = 1; B = 0; C = 0; D = 1;
#100ns A = 1; B = 0; C = 1; D = 0;
#100ns A = 1; B = 0; C = 1; D = 1;
#100ns A = 1; B = 1; C = 0; D = 0;
#100ns A = 1; B = 1; C = 0; D = 1;
#100ns A = 1; B = 1; C = 1; D = 0;
#100ns A = 1; B = 1; C = 1; D = 1;
end
endmodule
Output:

EE-221: Digital Logic Design Page 9