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    DLD Assignment 1

    Uploaded by

    Mahnoor Vohra
    The document provides instructions for a digital logic design assignment involving combinational circuits. It contains 6 questions testing various concepts in digital logic including designing combinational circuits, minimizing logic expressions using Karnaugh maps, simplifying logic expressions using Boolean laws, performing arithmetic operations using binary numbers, and creating logical expressions to model real-world scenarios. Students are advised to solve the questions individually, submit their work through the university's online system, and avoid plagiarism.

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    © All Rights Reserved
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    DLD Assignment 1

    Uploaded by

    Mahnoor Vohra
    117 views8 pages
    The document provides instructions for a digital logic design assignment involving combinational circuits. It contains 6 questions testing various concepts in digital logic including designing combinational circuits, minimizing logic expressions using Karnaugh maps, simplifying logic expressions using Boolean laws, performing arithmetic operations using binary numbers, and creating logical expressions to model real-world scenarios. Students are advised to solve the questions individually, submit their work through the university's online system, and avoid plagiarism.

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    The document provides instructions for a digital logic design assignment involving combinational circuits. It contains 6 questions testing various concepts in digital logic including designing combinational circuits, minimizing logic expressions using Karnaugh maps, simplifying logic expressions using Boolean laws, performing arithmetic operations using binary numbers, and creating logical expressions to model real-world scenarios. Students are advised to solve the questions individually, submit their work through the university's online system, and avoid plagiarism.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    117 views8 pages

    DLD Assignment 1

    Uploaded by

    Mahnoor Vohra
    The document provides instructions for a digital logic design assignment involving combinational circuits. It contains 6 questions testing various concepts in digital logic including designing combinational circuits, minimizing logic expressions using Karnaugh maps, simplifying logic expressions using Boolean laws, performing arithmetic operations using binary numbers, and creating logical expressions to model real-world scenarios. Students are advised to solve the questions individually, submit their work through the university's online system, and avoid plagiarism.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 8

    JINNAH UNIVERSITY FOR WOMEN

    Department of Computer Science & Software Engineering


    BS(SE)-2020
    Digital Logic Design [CSS 1582]
    Theory Assignment
    Maximum Marks: 10

    Instructions:

    • The assignment must be submitted on JUW LMS. Email submission will not be accepted.
    • Each student should solve the assignment individually.
    • You are advised to go through the related topics before solving the assignment.
    • Make your work clear and understandable.
    • Plagiarism may lead to marks deduction.
    • Use references where necessary.
    • Students can solve questions on paper and include image in assignment.

    Question No.1 [2 marks]

    Design a combinational circuit with three inputs, A, B, and C, and three outputs, Q, R, and S.
    • When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input.
    • When the binary input is 4, 5, 6, or 7, the binary output is one less than the input.

    INPUT OUTPUT
    A B C Q R S
    0 0 0 0 0 1
    0 0 1 0 1 0
    0 1 0 0 1 1
    0 1 1 1 0 0
    1 0 0 0 1 1
    1 0 1 1 0 0
    1 1 0 1 0 1
    1 1 1 1 1 0

    A/BC 00 01 11 10

    0 1
    1 1 1 1

    Q = AB + AC + BC
    A/BC 00 01 11 10

    0 1 1
    1 1 1

    R=AꚚBꚚC

    S = C’
    Question No.2 [2 marks]

    Minimize the circuit using kaunaugh map.

    WX\YZ 00 01 11 10
    00 1 0 1 1 1 3 1 2

    01 0 4 0 5 0 7 1 6

    11 1 12 1 13 1 15 1 14

    10 0 8 0 9 1 10 1 11

    The unreduced equation:

    O = W’X’Y’Z’+W’X’Y’Z’+W’X’Y’Z’+W’X’Y’Z’+XW’Z+Z’YX’+WXYZ’

    The reduced equation would be:

    O = W’X’ + YZ’ + WX + WY
    Question No.3 [2 marks]

    Simplify using Boolean Laws. Draw circuit diagram of the simplified expression and apply
    NAND and NOR logic in both the simplified expression.
    1. X’Y’Z + X’YZ +XY’

    F = X’Y’Z+X’YZ+XY’
    = X’Z (Y’+Y) +XY’ ( ∵ Y’+Y= 1)
    = X’Z + XY’

    2. XY +X’Z +YZ

    F = XY+X’Z+YZ ( X+X’)
    = XY+X’Z+XYZ+X’YZ
    = XY+XYZ+X’Z+X’YZ
    = XY (1+Z) + X’Z (1+Y) (∵ 1+Z = 1)
    = XY+X’Z
    Question No.4 [2 marks]

    Find M –N and.
    M= 22 M = 4567
    N= 26 N = 1234
    • Using 2’s complement method (5- • 10’s complement method
    bit)
    M = 22 Taking 10’s complement of N:
    N = (8766)10
    2 22 Now adding it in M:
    2 11 ---- 0
    2 5 ----- 1 4567
    2 2 ----- 1 +8766
    1 ----- 0
    13 3 3 3
    M = (10110)2

    N= 26 End carry discard,

    2 26 3333 ANSWER
    2 13 ---- 0
    2 6 ------ 1
    2 3 ------ 0
    2 1 ------ 1

    N= (11010)2

    2’s complement of N= (00110)2


    Add in M:
    10110
    +00110

    11100

    No carry, taking complement of


    answer and putting negative sign

    (-00100)2 ANSWER
    Question No.5 [1 marks]

    A certain system contains two identical circuits operates in parallel, initial output is zero when
    both are inactive. As long as both are operating properly, the outputs of both circuits are always
    the same, if one of the circuits fail, the output will be at opposite levels. Create a logical expression
    to detect that failure has occurred in one of the circuit.

    SOLUTION:

    Both circuits I1 and I2 are identical, B1 and B2 are their outputs


    respectively,
    B1 B2 y
    0 0 1
    0 1 0
    1 0 0
    1 1 1

    If I1 fail B1 = 0

    If I2 fail B2 = 0
    B1 B2 y
    0 0 0
    0 1 0
    1 0 0
    1 1 1

    The output is high only when both the circuits work properly, In
    comparison with XOR gate the AND gate is more efficient.

    Question No.6 [1 marks]

    A bank wants to install an alarm system with 3 movement sensors.


    To prevent false alarms produced by a single sensor activation, the alarm will be triggered only
    when at least two sensors activate simultaneously. Create a logical expression and draw its circuit
    diagram.

    C B A X

    0 0 0 0
    0 0 1 0
    0 1 0 0
    0 1 1 1
    1 0 0 0
    1 0 1 1
    1 1 0 1
    1 1 1 1
    SUM OF PRODUCTS:

    X = C’BA + CB’A + CBA’ + CBA

    The Boolean expressions for the circuit is:

    X = B.A + C.A + C.B

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