BGA’s, LGA’s, QFN/DFN’s – Oh My,

Can Traditional DFM Survive

Dale.Lee@Plexus.com
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Low Stand-Off Components

Low Stand-off Components
Cover A Wide Range Of
Package Styles And Types
Including DFN, QFN, LGA,
Leadless Chip Carriers and
some BGA’s (Ball and Bump
Grid Arrays)

Lack Of Package
Standardization Increases
Inconsistency In Assembly
Processes,Stencil Tooling
Designs And Cleanability
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Where Is The Component?

IPC: Magnification Aids Shall Be Appropriate For Item Being

Inspected.
Is 20X Magnification Strong Enough? What About 40X?

Source: IPC-A-610, Section 1.10

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Land Pattern Design Inspection Impacts

IPC-7351 recognizes the requirements of higher
component density applications and provides
information on land pattern geometry used for
specific product categories.

Level A: Maximum Land Protrusion — For low-density product

applications
Level B: Median Land Protrusion — Products with a moderate
level of component density
Level C: Minimum Land Protrusion — Products with high
component density

Note: Smaller visible fillets impacts AOI ability to determine if

there is a fillet. Post reflow position also impacts this ability.
Level A Level B Level C
Increased false call rate.
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High Design Density

Spacing Limitations Are Not A Driven By The
Manufacturing/Assembly Process
SMT Pads
Minimum Or No Visible Solder (Toe) Fillets
Potential AOI/Inspection Issue
Component Spacing
Minimum Component to Component Spacing
Limited/No Rework
Limited AOI/Test Point Access
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6
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The PCB layout design for the …

requires a couple of
considerations. The design of
the cutout to allow light to
illuminate the sensor is a
critical part of this design.
The device layout is also critical
for optimal SMT assembly.

7
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Solder Mask Via Tenting Options

Atmel Application Note

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Via Filling Types

Solder Mask Via Cap

Solder Mask Via Plug

Solder Mask Via Fill

Via Fill & Over Plate

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Solder Mask Design

Exposed Via In Pad

• Ensure Solder Mask Is Not Applied On
Opposite Side Of PCB.
• If Applied, Ensure Via Hole Is Small
Enough To Restrict Solder Mask Flow
Through To Solder Attach Side Of PCB
• If Top Side Via Plugging Is Required,
Especially Is Under BTC Components, A
Note Should Be Added To Fabrication
And Assembly Drawing Referencing This
Condition Especially If Solder Mask Is
Designed To The Same Size As The PCB
Pad Size
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Solder Mask Opening Design

Pad Geometries
• Non-Solder Mask Defined (NSMD)
• Size of Pad Defined By Copper Pad and Interconnections
(Variable Size)
• Solder Encapsulates Pad
• Limited to Components With Lead Pitch Greater Than
0.4mm

• Solder Mask Defined (SMD)

• Size of Pad Defined By Solder Mask Opening (Uniform
Size)
• Solder Covers Exposed Pad (Fills Opening)
• Required For Components With Lead Pitch 0.4mm or
Less.
• Preferred for Leadless Array Devices Like LGA’s, Multi-
row QFN’s, etc.
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Solder Mask Defined Pads

PCB fabricator reduced solder mask openings greater than 0.002” resulting in solder paste
being printed on top of solder mask.

Results was a slight excess of solder paste on top of solder mask resulting in solder balls
under component package.
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Copper Etching Of Pads

Problem:
IPC requirement for measurement of etch size tolerance is taken from the located of
widest point (dimension “B”).
Solution:
Develop fabrication note that will specify tolerance.
Example:
Non-solder mask defined land/pad size tolerance measured at crest shall be +/-
0.001”.
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Copper Etching Of Pads

Copper pads when measured at the top
surface may be significantly smaller than
at widest point.

Potential issue where solder stencil

openings are too large to rest on top of
pad and insufficient solder paste may be
applied for reliable solder connection
formation.
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Over Etching Of Mounting Surface

Over etching of top of copper pad can Solder Paste
create issue with: Stencil

1. Decreased solder paste printed volume

2. Shifted component placement
3. Test probe missing pad (false failure – open
connection)
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Combined Copper Etching and Solder Mask Effects

Very Small Copper Features
• Shown is a 0.4mm pitch 8 ball CSP
with 0.2mm nominal pads.

• NSMD on left, SMD on right using

LDI

• Note NSMD no connects are

smaller due to 360°etching

• Etching accuracy can have a huge

impact on features 0.3mm (12mils)

Image: Benchmark Upper Midwest SMTA Chapter Presentation, April 2016

16
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Solder Mask Defined Pads

Problem:
IPC specifications do not have a size tolerance requirement for solder mask defined
pads. IPC tolerances only address solder mask clearances around non-solder mask
defined pads. For BGA components only, the tolerances are for registration
(encroachment) only, not for opening size.

Solution:
Develop fabrication note that will specify tolerance of solder mask openings on solder
mask defined pads. This tolerance may be limited to opening dimensions less than a
maximum dimension
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Conductive/Non-Conductive Fill
IPC-6012D Section 3.6.2.18 shall fill a minimum of 60% (voids of up to 40%) for Class 2
and Class 3 assemblies. When cap plating is not specified, fill material shall
encapsulate internal voids and be planar.
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Plated Copper Filled Microvias

Per IPC-6012 Section 3.6.2.11.3, voids are
acceptable provided they are completely
encapsulated and in total do not exceed 25% of
viewable area of filled microvia.
But does the trapped chemistry create a potential
reliability issue during soldering process or in end
use environment?
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Buried Plated Close Via

With plated closed buried via holes, there can be
plating chemistry still trapped in the close via
that may create excessive stress on barrel/wrap
plating that could lead to corrosive chemical
leakage after soldering process or in end use
applications
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Unbalanced Copper Density Under Package

Fine Pitched BGA With Micro-Via-In-Pad
Design.
PCB Design Was A 1-6-1 Construction
Unbalanced Copper Density On Layer Directly
Beneath Package
Localized PCB Thickness Variation
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Unbalanced Copper Density Under Package

Fine Pitched BGA With Micro-Via-In-Pad
Design.
PCB Design Was A 1-6-1 Construction
Unbalanced Copper Density On Layer Directly
Beneath Package
Localized PCB Thickness Variation
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Silk Screen Design - Low Standoff Packages

Silk Screen Should Not Be Placed
Under Body Of Low Standoff
Components
• Increased Gap For Solder To
Bridge During Solder Reflow
Process
• Potential Tilting Of Components
(Open Connection)
• Potential Latent Field Failure
With Partial Solder Connection
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Silk Screen Design - Low Standoff Packages

Low Component Stand-off Height
Excessive PCB to Component Standoff
Height – Open Joint
Tilted Component
Open Joints (one edge or center standoff
from PCB)
Misalignment
Component Types
Leadless
• QFN, DFN, LCC
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With BTC’s, Not All Pads Are Equal

Packages That Are Singulated By Saw Or Punch Cut Are
Not Solderable Per IPC-A-610 Section 8.3.13 Notes 2 And 5

Reference: QFN/DFN Inspection of Solder Joints, Linear Technology Application Note

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With BTC’s, Not All Pads Are Equal

Some Packages Have Solderable Edge Terminations
Requires additional pad length for solder fillet formation.
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LGA Pad Design

Solder Mask Defined Non-Solder Mask Defined

Solder wicking around NSMD pads produce significantly lower molten solder height.
Solder mask defined pads should be used for LGA and 0.4mm & smaller pitch BGA/CSP
packages.
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LGA/QFN Package Assembly

Trace Routing Under Component Create Localized Height Variations
• Standoff Height Variation

Leadless Devices Are More Sensitive To PCB/Component Flatness/Warpage

• Received Condition
• In-process Condition (During Reflow/Rework Solder Process)

LGA Package

BGA Package
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Trace Routing And Solder Mask Opening Impacts Solder Joint

EFFECTIVE PAD SIZE ANALYSIS
Increased Mounting Pad Size Affected By:
60 • Number Of Trace Connections To Each Pad
• Width Of Trace Connections To Each Pad
% PAD SIZE INCREASE

50

40 • Size of Pad
30 – Small Pads Have Less Margin
20 • Uniformity Of Trace Egress Direction
10 – Some Package Types Are More Sensitive
Than Others
0
4 10 15 20 • Uniformity Of Trace Sizes
WIDTH OF TRACE 10 Mil Nom 15 Mil Nom 20 Mil Nom
10 Mil Max 15 Mil Max 20 Mil Max
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Component and PCB Warpage

Combination Of Component And PCB
Thermal Expansion Differences Can Increase
Opportunity For Z-axis Expansion Induced
Defects
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Warpage Created Issues

INEMI Roadmap 2013.
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Component Warpage
Example Of Uniform Component Warpage Over Assembly Temperature
Range
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Component Warpage
Example Of Non-Uniform Component Warpage Over Assembly Temperature
Range
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Component Warpage
Bigger Aperture Is Recommended To Outer Region Where
Head In Pillow Is Observed
JEITA ED-7306 Allowed Warpage For BGA And FBGA Packages

Cypress Application Datasheet

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Component Warpage
Increase in aperture opening may not be the only
method to address component warpage. It can be
a decrease in aperture opening or a combination of
increased, 1 to 1, and decreased aperture openings
on the same package.

Intel Board Design Guideline for Intell Programmable Device Pacakges, AN-114
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Offset Paste – Normal Placement

Video Courtesy of Juki Automation

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Matched Offset – Paste & Part

Video Courtesy of Juki Automation

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Impacts of Via Design on Assembly

Placement And Types Of Vias
In Pad Can Affect Assembly
Solder Joint Formation
More Of An Impact On
Smaller Components
And/Or Lower I/O Count

Design and Construction Affects on PWB Reliability, Paul Reid, IPC Apex Proceedings 2012.
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Impacts of Via Design on Assembly

Placement And Types Of Vias
In Pad Can Affect Assembly
Solder Joint Formation
More Of An Impact On
Smaller Components
And/Or Lower I/O Count

Design and Construction Affects on PWB Reliability, Paul Reid, IPC Apex Proceedings 2012.
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Via-In-Pad Design Impacts

Increased Solder Process Thermal Variability
• PCBA Level
• Component To Component
• Pad To Pad
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Examples Of Via-In-Pad Types

Stacked Micro-via, Multiple

Copper Thicknesses

Filled & Over Plate Thru Via Stacked Micro-via On

Buried Via’s
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Z-Axis Expansion/Contraction Impacts Of Via In Pad

Placement Of Stacked Vias Or Through Via In Pad Under
Devices May Create Mounting Pad Height Differences
During Solidification Process
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Z-Axis Expansion/Contraction Impacts Of Via In Pad

More Of An Impact On Smaller And/Or Lower I/O
Count or Leadless (No Solder Ball/ Solder Bump)
Component Packages
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Board Warpage
Board Warpage Within IPC Assembly Workmanship Standards (0.75%) May Not Be Adequate
For Some Component Packages To Obtain High Assembly Yields.
Warpage can be impacted by both CTE mismatch and localize temperatures from localized
component density, component/printed board size, and vertical heating/cooling
differences.
Reflow profile to bridge component warpage gap: Decrease thermal rate of change and
delta T vertically in component package – reduce surface to cooler location temperature
delta - TCE induced warpage
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Exposed Via Impact

It is recommended that the via diameter be 0.30 to
0.33 mm with 1.0 ounce copper via barrel plating.
This is desirable to avoid any solder-wicking inside
the via during the soldering process, which may
result in voids in solder between the exposed pad
and the thermal land.

Freescale Semiconductor, Inc. Application Note

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Via Hole Size

Smaller Via Hole Size In Thermal Pad Reduce Solder Flow Into Via Hole
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Exposed Via Impact

Exposed Via Holes Provide Path For Flux
Volatiles And Solder To Escape From Under
Component Body

Note: Solder In Via Is Not Continuous.

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Exposed Via Impact

Exposed Via Holes Provide Path For Flux
Volatiles And Solder To Escape From Under
Component Body

Note: Solder In Via Is Not Continuous.

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Voids In Thermal Pad

Void Size and Quantity Decrease With Increased Number Of Exposed Via Holes In Thermal
Pad Per Unit Area
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Thermal Pad Residue Impacts

During Reflow Process, The Large Surface Area Of The Thermal Pad Creates A Large
Volume Of Nonvolatilized Residue Around The Perimeter Of The Pad.
As Pad Area Increases, The Residue Volume To Pad Perimeter Length Ratio Increases At A Linear
Rate (The Residue Volume Is Increasing At A Greater Rate Than The Area Around The Pad To
Clean)
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Why Cleaning Is Important!

With Increased Use Of Low Stand-Off Packages And With Or Without Thermal Pads Restricts
Cleaning Solutions Access To Soldering Residues

Fully Cleaned Partially Cleaned No Cleaning

Source: Reactivity of No-Clean Flux Residues Trapped Under BTCs, M.Bixenman, et.al., SMTA-I 2016 Proceedings
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Cleaning
Impacts of PCB Design on Ability to Remove Soldering Process Residues
• Solder Mask
• Component Size
• Cleaning Exposure Time
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Beware Of What You Cannot See

Courtesy of Kester
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Questions?

Intellectuals solve problems, Geniuses 
prevent them.

And when you thought it

could not get any worse.

Here it comes! Albert 

Einstein