L24 - Deadbeat Response Design - Sampled Data Control Systems With Deadbeat Response
L24 - Deadbeat Response Design - Sampled Data Control Systems With Deadbeat Response
L24 - Deadbeat Response Design - Sampled Data Control Systems With Deadbeat Response
The reason behind this is since the process zeros are canceled by controller poles, the con-
tinuous dynamics are excited by the input and are not affected by feed back.
The strategy of designing dead beat response for a sampled data system with the process
plant transfer function Gh0 Gp (z) having at least one zero is not to cancel the zeros, whether
they are inside or outside the unit circle.
H.P Sirisena gave a mathematical formulation and analysis to dead beat response.
Q(z −1 )
If Gh0 Gp (z ) =
−1
, then according to Sirisena the digital controller for ripple free dead
P (z −1 )
beat response to step input is
P (z −1 )
Dc (z) =
Q(1) − Q(z −1 )
The design of ripple free dead beat response can still be done using similar approach as discussed
in the previous chapters except for an added constraint which will increase the response time
of the system.
Example 1:
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Digital Control Module 6 Lecture 3
Thus
0.01(z + 0.9)
Gh0 Gp (z) =
(z − 1)(z − 0.8)
If we design Dc (z) without bothering about the inter sample ripples then
M (z) = z −1 , 1 − M (z) = 1 − z −1
100(z − 0.8)
Dc (z) =
(z + 0.9)
1
C(z) = = z −1 + z −2 + ..........
z−1
This implies that the output response is deadbeat only at sampling instants. However, the true
output c(t) has inter sampling ripples which makes the system response as shown in Figure 2.
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Digital Control Module 6 Lecture 3
Thus the system takes forever to reach its steady state. The necessary and sufficient condition
for c(t) to track a unit step input in finite time is
dc(t)
c(N T ) = 1 =0
d(t) t=N T
for finite N and all the higher derivatives should equal to zero. Let
dc(t)
w(t) =
d(t)
Taking Z-transform,
A1 (z − 1)
= R(z)
z(z + 0.9)
where A1 is a constant. Unit step response of W (z) will not go to zero in finite time since poles
W (z)
of are not all at z = 0.
R(z)
If we now apply the condition that zero of Gh0 Gp (z) at z = −0.9 should not be canceled
by Dc (z), then
1 − M (z) = (1 − z −1 )(1 + a1 z −1 )
Solving
⇒ m1 = 0.53, a1 = 0.47
Thus
0.53(z + 0.9)
M (z) =
z2
A2 (z − 0.8)
Dc (z) =
z + 0.47
C(z) = A3 z −1 + z −2 + z −3 + .......
where A2 and A3 are constants. This implies that the dead beat response reaches the steady
state after two sampling periods.
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Digital Control Module 6 Lecture 3
To show that the output response is indeed deadbeat, we derive the z-transform of w(t) as
W (z) = 2z −1
Thus c(t) will actually reach its steady state in two sampling periods with no inter sample
ripples which is shown in Figure 3.
If we apply the condition that zeros of Gh0 Gp (z) at z = −0.2 and z = −2.8 should not be
canceled by Dc (z), then
1 − M (z) = (1 − z −1 )(1 + a1 z −1 + a2 z −2 + a3 z −3 )
While considering M (z) and 1 − M (z), following points should be kept in mind
2. The number of poles over zeros of M (z) should be at least equal to that of Gh0 Gp (z) which
is 2 in this case.
4. The orders of M (z) and 1−M (z) should be same and should equal the number of unknown
coefficients.
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Digital Control Module 6 Lecture 3
1 − a1 = 0
m 1 = a1 − a2
3m1 = a2 − a3
0.56m1 = a3
The solutions of the above are m1 = 0.219, a1 = 1, a2 = 0.781 and a3 = 0.123. The closed loop
transfer function is
Thus the output response c(kT ) reaches the steady state in 4 sampling instants. This is one
more sampling instant than the previous example where we considered the plant to be all digital.
This implies that for sampled data control system, the dead beat response c(t) reaches the
steady state after three sampling periods but inter sample ripples occur. After four sampling
instants the inter sample ripples disappear.
To show that the output response is indeed deadbeat, we derive the z-transform of w(t) which
will come out to be
W (z) = A1 z −2 + A2 z −3
where A1 , A2 are constants.
Thus the derivative of c(t) is zero for kT ≥ 4T , which implies that the step response reaches
the steady state in 4 sampling instants with no inter sample ripples, as shown in Figure 4.
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Digital Control Module 6 Lecture 3
c(t)
1 c(4)
c(3)
c(2)
0 T 2T 3T 4T t
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