Cel 1330

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CEl1330
Electronics Circuit Design

(New) (1090)
P. Pages: 4
Tirrie : Three Hours Max. Marks : 100
Instructions to Candidates :
1. Do not write anything on question paper except Seat No. ,
2. Answersheet should be written with blue ink only. Graph or diagram should
be drawn with the same pen being used for writing paper or black HB
pencil.
3. Students should note, no supplement will be provided.
4. All questions are compulsory & carries equal marks.
5. Assume suitable data if necessary.
6. Unless specified assume used transistor is of silicon. J
7. Use of non-programmable calculator is allowed.
UNIT· I ·
1. Solve any two. 20
a) Design an unregulated power supply for following requirements.

i) Bridge Rectifier with capacitor filter.
ii) Output D.C. Load voltage of 1OV.
iii) Output D.C. Load current of 50 mA.
iv) Ripple factor of 3%.
v) Take R 5 =Rt = 5n and also find out the surge current Ratings
of the Diodes.
b) Design Boost Regulator using LM 257711577 l.C. for

V0 = 20V, IL = 0.6A, Vin = 8V, at 60°C. Design should include external
components around l.C. & Heat sink calculations if required.
Take Lil= 25% lindavg for LM 2577 1157 : ~
Isupply RoN ejA ecS Ti

15 mA 0.250 65°c/w 2°c/w 150°C
CEl1330 1 P.T.O.
CEl1330 CEl1330
c) Design a Regulated power supply using Three-terminal Regulator

LM 340 for V0 =12V, IL= 0.5amp at 35°C.
Design should include, the unregulated power supply section for
Vr(p-p) = 1.2V.
Also find out if heat sink to the l.C. is required or not:
for LM 340
Drop out voltage Ti ejA ejC ecs
3V 150°C 35°C/W 2.3°c/w 2°c/w
UNIT -11
a) Design a single stage common Base amplifier for

Av ~50, Ri ~75n, RLw =50kn, Rs =500, S=lO, Q points[lmA, 3V]
Assume used transistor have hfe = 100, hie = 10 k.
b) Design single stage common source amplifier with Bypassed source

1
resistance for (i) Av :::: 80 (ii) Ri:::: 500Kn (iii) Q points= loq = 21oss.
Vosq:::: 3V (iv) Rs= 0.5kn, RLw = 100K, fl= 20Hz
(v) Take VR 0 = VR 3 R 3 is the source resistance of device. FET used
have loss= 2mA, Vp = -SV, 9mo = 12mU rd= 80kn.

Use potential Divider Bias Network.
c) Design a single stage C.E. amplifier with [partially bipassed and pa1iially
unbypassed Emitter Resistance] for
Av5 ~ 50,[Qpoints : Icq = lmA, VcEq ~ SV]
Ri =lOK, S=lO, RLw =100kn, Rs =0.6kn
BJT have hfe = 200, hie = 10 K.
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UNIT -111
a) Design of class-A transformer coupled amplifier to deliver 45 mw of

a.c. power to the load resistance of. 4n, Take Vee = 9V and efficiency
of X'mer as 70%.
b) Design a class-B transformer coupled power amplifier for

Pac= 'IOW, RL =SQ, ntransformer = 80%, S = 8, Vee= 20V.
c) Design a ·Complementary symmetry power amplifier for

Pac= 0.5W, RL = 80, frequency response 30 Hz to 10 kHz.
Used transistors have hte = 120.
UNIT- IV
a) Design a monostable multivibratorto provide a pulse of 300µsec,
with amplitude of output is 9V, used BJT have hte =100, lcq =1mA.
b) Design a Colpitt oscillator using FET (n-channel) (with potential Bias N/W)
for
i) freq. of oscillation f0 = 5 MHz
ii) Voltage gain Av= 25, Ri = 200KQ
iii) Q points : loq = 1mA, Vosq = 5V.

iv) Voltage across source resistance R3 of Device VR 3 = 3V
v) Take inductor in feedback Network equals to 1µH.
· FET used have 1088 = 2mA, Vp = -6V, rd= 50Kn, 9mo = 3mu.
c) Design a Tuned Amplifier using FET for

i) Resonance frequency f0 = 5MHz
ii) Bandwidth== 125 KHz
iii) Overall voltage gain== 116
iv) =
l/P Resistance 500Kn
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v) Q points: loq = loss. Vosq ~ 5V.
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vi) Take Vos= VR 3 (R 3 is the source Resistance of Device)
vii) RLw = 100Kn, Rs= 50Kn.

Use potential Divider Network FET used have
loss= 20mA, Vp = -2V, rd= 50Kn, C 0 = 2.5pf.
UNIT-V
a) Design a Band pass filter for fL = 600 Hz, fH = 6 KHz with attenuation
Rate of 40 dBldecade in stop-band. Also take pass-band as flatt as
possible. Use salen-key equal component approach. [Take value of
capacitor as 0. 01 µf]
b) Design AC amplifier using 741-C with sing.le ended .power supply for
i) Inverting mode
ii) At = 10.5
iii) Rif ~ 20 K Rs = 75n
iv) Vee= +24V, IL~ 2mA fL = 20Hz
741-C have following specifications -
A 0 =2x10 5 , f0 =5Hz, Ri =2Mn, R 0 =750, S.R.=0.5V/µsec.
c) Design H.P.F. using 741-C

i) Order of filter~ 4th ·
ii) Overall -gain ~ 10
iii) Bessel Response (Assume C~0.01 µf)
iv) f0 = 9 KHz .
For Bessel filter use data
Filter order Sections Parameters

a.=1.916
151 (2nd order)
KLP = b.696
4th order
ex.= 1.241
tl~~r) _. KLP =0.621
***************
CEl1330 4 113/180

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I

Electronics Circuit Design

1. Solve any two. 20

a) Design an unregulated power supply for following requirements.

b) Design Boost Regulator using LM 257711577 l.C. for

Isupply RoN ejA ecS Ti

c) Design a Regulated power supply using Three-terminal Regulator

2. Solve any two. 20

a) Design a single stage common Base amplifier for

b) Design single stage common source amplifier with Bypassed source

Vosq:::: 3V (iv) Rs= 0.5kn, RLw = 100K, fl= 20Hz

(v) Take VR 0 = VR 3 R 3 is the source resistance of device. FET used

have loss= 2mA, Vp = -SV, 9mo = 12mU rd= 80kn.

3. Solve any two. 20

a) Design of class-A transformer coupled amplifier to deliver 45 mw of

b) Design a class-B transformer coupled power amplifier for

c) Design a ·Complementary symmetry power amplifier for

4. Solve any two. 20

a) Design a monostable multivibratorto provide a pulse of 300µsec,

ii) Voltage gain Av= 25, Ri = 200KQ

iii) Q points : loq = 1mA, Vosq = 5V.

c) Design a Tuned Amplifier using FET for

vii) RLw = 100Kn, Rs= 50Kn.

5. Solve any two. 20

c) Design H.P.F. using 741-C

Filter order Sections Parameters

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