12/6/21, 8:03 AM Binary Decoder in Digital Logic - GeeksforGeeks

Binary Decoder in Digital Logic

Difficulty Level :
Easy ● Last Updated :
06 Feb, 2020

In Digital Electronic s, discrete quantities of information are represented by binar y

codes. A binar y code of n bits is capable of representing up to 2^n distinct elements of

coded information. The name “Decoder ” means to translate or decode coded

information from one format into another, so a digital decoder transforms a set of

digital input signals into an equivalent decimal code at its output. A decoder is a

combinational circuit that conver ts binar y information from n input lines to a

maximum of 2^n unique output lines.

Binar y Decoder –

Binar y Decoders are another type of digital logic device that has inputs of 2-bit, 3-

bit or 4-bit codes depending upon the number of data input lines, so a decoder that

has a set of two or more bits will be defined as having an n-bit code, and therefore

it will be possible to represent 2^n possible values.

If a binar y decoder receives n inputs it activates one and only one of its 2^n outputs

based on that input with all other outputs deactivated. If the n -bit coded
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information has unused combinations, the decoder may have fewer than 2^n

outputs.

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Example, an inver ter ( NOT-gate ) can be classified as a 1-to-2 binar y decoder as
Register
1-input and 2-outputs is possible. i.e an input A can give either A or A complement

as the output.

Then we can say that a standard combinational logic decoder is an n-to-m decoder,

where m <= 2^n, and whose output, Q is dependent only on its present input states.

Their purpose is to generate the 2^n (or fewer) minterms of n input variables. Each

combination of inputs will asser t a unique output.

A Binar y Decoder conver ts coded inputs into coded outputs, where the input and

output codes are different and decoders are available to “decode” either a Binar y or

BCD (8421 code) input pattern to typically a Decimal output code.

Practical “binar y decoder ” circuits include 2-to-4, 3-to-8 and 4-to-16 line

configurations.

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2-to-4 Binar y Decoder –

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The 2-to-4 line binar y decoder depicted above consists of an array of four AND gates.

The 2 binar y inputs labeled A and B are decoded into one of 4 outputs, hence the

description of a 2-to-4 binar y decoder. Each output represents one of the minterms of

the 2 input variables, (each output = a minterm).

The output values will be:

Qo=A’B’

Q1=A’B

Q2=A B’

Q3=A B

The binar y inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic

level “1” while the remaining outputs are held “LOW ” at logic “0” so only one output can

be active (HIGH) at any one time. Therefore, whichever output line is “HIGH” identifies

the binar y code present at the input, in other words, it “decodes” the binar y input.

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Some binar y decoders have an additional input pin labeled “Enable” that controls the

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outputs from the device. This extra input allows the outputs of the decoder to be

Login Register
turned “ON” or “OFF ” as required. The output is only generated when the Enable input

has value 1; other wise, all outputs are 0. Only a small change in the implementation is

required: the Enable input is fed into the AND gates which produce the outputs.

If Enable is 0, all AND gates are supplied with one of the inputs as 0 and hence no

output is produced. When Enable is 1, the AND gates get one of the inputs as 1, and

now the output depends upon the remaining inputs. Hence the output of the decoder is

dependent on whether the Enable is high or low.

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1. GATE CS 2007, Question 85

2. GATE CS 20130, Question 65

References –

electronic shub – Binar y Decoder

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