Chapter 1 Introduction

Jin-Fu
u Li
Advanced Reliable Systems (ARES) Laboratory
Department of Electrical Engineering
National Central University
Jungli, Taiwan
 Outline

† VLSI Realization
† Role of Testing
† Trends of Architecture of VLSI Chips

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Hierarchical Design Flow for an System Chip

Requirements
and
Specification specification Specification

Hardware Architecture Software

Architecture Architecture

Hardware Software
Detail Design Design Design Module Design

Integration Integration Integration

Test System test Test

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

 VLSI Realization Process

Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development

Fabrication

g test
Manufacturing

Chips to customer

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

 Definitions
† Design synthesis
„ Given an I/O function, develop a procedure to
manufacture a device using known materials and
processes
† Verification
V ifi ti
„ Predictive analysis to ensure that the synthesized
design when manufactured
design, manufactured, will perform the given
I/O function
† Test
„ A manufacturing step that ensures that the physical
device, manufactured from the synthesized design,
has no manufacturing defect

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

 VLSI Design Cycle
Concept

Design Designer Final Product

Validation
Product
Behavior Specification Manufacturing Verification

RTL Behavior Synthesis Layout (Masks)

Verification
Layout
RTL Design Layout Synthesis Verification

Logic Logic Synthesis Netlist (Logic Gates)

Verification

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

 Verification
† The four representations of the design
„ Behavioral, RTL, gate level, and layout
† In mapping the design from one phase to
another, it is likely that some errors are
produced
„ Caused by the CAD tools or human mishandling of
the
h tools
l
† Usually, simulation is used for verification,
although
lth h more recently,
tl formal
f l verification
ifi ti h
has
been gaining in importance
† Two
T ttypes off simulations
i l ti are usedd to
t verify
if the
th
design
„ Functional
F ti l simulation
i l ti & timing
ti i simulation
i l ti
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 Role of Testing
† If you design a product, fabricate, and test it,
and it fails the test, then there must be a
cause for the failure
„ Test was wrong
„ The fabrication process was faulty
„ The design was incorrect
„ Th specification
The ifi ti problem
bl
† The role of testing is to detect whether
something
thi wentt wrong and d the
th role
l off
diagnosis is to determine exactly what went
wrong
† Correctness and effectiveness of testing is
most important for quality products
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
 Benefits of Testing
† Quality and economy are two major benefits of
testing
† The two attributes are greatly dependent and
can not be defined without the other
† Quality means satisfying the user’s needs at a
minimum cost
† The purpose of testing is to weed out all bad
products before they
p y reach the user
„ The number of bad products heavily affect the price
of good products
† A profound understanding of the principles of
manufacturing and test is essential for an
engineer
i tto d
design
i a quality
lit product
d t
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 Present and Future
† Semiconductor Industry Association’s (SIA’s)
p j
projection

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 Present and Future
† Semiconductor Industry Association’s (SIA’s)
p j
projection

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 Trends of Testing
† Two key factors are changing the way of VLSI
ICs testing
„ The manufacturing test cost has been not scaling
„ The effort to generate tests has been growing
geometrically
t i ll along
l with
ith product
d t complexity
l it

Cost: cents/transistor
1 Source: SIA
0.1
0.01 Si capital/transistor
0.001
0.0001
0.00001 Test capital/transistor
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

 Test Knowledge is Important
† Testing is becoming a factor in design
optimization
† Designers customarily strive for an optimal
design
„ A high-speed, low-power design occupying the
smallest possible area
† Conventionally, the designer often optimize
one of the tree attributes: speed (or delay),
area, and
d power
† At present, a fourth attribute is considered
„ Testability
† Nowadays, the testability cycle should parallel
the
h design
d i cycle
l
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 DFT Cycle
Behavioral Description Gate

Behavioral DFT Synthesis Technology Mapping

RTL Description Layout

Logic DFT Synthesis Parameter Extraction

Gate Description Manufacturing

Test Pattern Generation Product

Fault Coverage ? Test Application

Low High
Good Product

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

 As Technology Scales Continuously
† Die size, chip yield, and design productivity
have so far limited transistor integration in a
VLSI design
† Now the focus has shifted to energy
consumption, power dissipation, and power
delivery
† As technology scales further we will face new
challenges, such as variability, single-event
upsets (soft
f errors), and device (transistor
performance) degradation− these effects
manifesting
if ti as iinherent
h t unreliability
li bilit off the
th
components, posing design and test challenges
Source: S. Borkar (Intel Corp.), IEEE Micro, 2005
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Possible Solution to Conquer Unreliability
† The key to the reliability problem might be to exploit
the abundance off transistors−use Moore’s low to
advantage. Instead of relying on higher and higher
ffrequency
q y off operation
p to deliver higher
g performance,
p f a
shift toward parallelism to deliver higher performance
is in order, and thus multi mightg be the solution at all
levels−from multiplicity of functional blocks to multiple
pprocessor cores in a system
y

Source: S. Borkar (Intel Corp.), IEEE Micro, 2005

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Possible Solution to Conquer Unreliability
† We could distribute test functionality as a part of the
hardware to dynamically
y y detect errors, or to correct and
isolate aging and faulty hardware. Or a subset of cores
in the multicore design g could perform
p f this work. This
microarchitecture strategy, with multicores to assist in
redundancy, y is called resilient microarchitecture. It
continuously detects errors, isolates faults, confines
ffaults, reconfigures
fg the hardware, and thus adapts.
p Iff we
can make such a strategy work, there is no need for on-
time factory testing, burn in, since the system is capable
of testing and reconfiguring itself to make itself work
reliably throughout its lifetime.
Source: S. Borkar (Intel Corp.), IEEE Micro, 2005
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
Architecture of Current SOC Chips
† Multi-core chip architecture
† Use multiple identical cores to design a chip
† Network-on-chip communication infrastructure
† Multiple point-to-point data links interconnected by
switches (i.e.,
(i e routers)

RAM unit
μ
Engine
Compute unit

DDR2 DDR2
Controller Controller

Source: IEEE Computer, 2005. Source: IEEE Micro, 2007.

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

Examples
SPARC V9 (Sun) Cell Processor (IBM) Teraflops processor (Intel)

Source: IEEE JSSC, 2006. Source: IEEE JSSC, 2006.

4x4 mesh built with Xpipes Niagara2 (Sun) Source: IEEE Micro, 2007.
library components

Source: IEEE JSSC

JSSC, 2008
2008.
Source: IEEE Micro, 2007.
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 Importance of Testing Techniques

† Testing technique play an important role in

current multicore chips
„ Quality insurance
„ Yield improvement
Yield-improvement
„ Reliability-improvement
„ Monitoring
„ Diagnosis
„ …

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 Example: Itanium (JSSC, Jan. 2006)

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Example: Niagara2 & POWER6 (JSSC, 2008)
Niagara2 (Sun) POWER6 (IBM)
Design-for-Testability
F t
Features:

1. Logic BIST
2
2. BIST for arrays
3. BISR for arrays
4. …

Design-for-Testability Features:

1. 32 Scans + ATPG
2. BIST for arrays
3. ….

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

3D-SiP: Next Technology/Architecture Transition?

† Technology evolution
† Bipolar
p Æ CMOS Æ Multicore Æ 3D integration
g
+ System-in-package (3D-SiP)
† System-in-package
System in package
† stacking dies using bonding wires

Source: ISQED
ISQED, 2008.
2008

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3D-SiP: Next Technology/Architecture Transition?

† 3D integration
† Stacking dies using through silicon via
(TSV)

S
Source: IBM
IBM, 2008.
2008

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Challenges of 3D Implementations

† Yield
† Design for
fo resiliency
esilienc
† Thermal
† Can we overcome it?
† Test
† Reliability
†…

Source: IBM
IBM, 2008
2008.

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