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    DLC Model I

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    EEE DEPT
    This document contains exam questions for a Digital Logic Circuits course. It is divided into three parts: Part A contains 10 multiple choice questions worth 2 marks each, covering topics like fan in/fan out, number systems, logic gate types, shift registers, hazards, PROM, and VHDL. Part B contains 5 questions worth 5-13 marks each, involving binary to gray code conversion, TTL NAND gate operation, full adder/subtractor design, demultiplexer design, JK flip-flop explanation, shift register types, PLA design, and asynchronous circuit design. Part C contains 2 questions worth 15 marks each, about hazards in sequential circuits and 8 to 1 multiple

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    DLC Model I

    Uploaded by

    EEE DEPT
    45 views2 pages
    This document contains exam questions for a Digital Logic Circuits course. It is divided into three parts: Part A contains 10 multiple choice questions worth 2 marks each, covering topics like fan in/fan out, number systems, logic gate types, shift registers, hazards, PROM, and VHDL. Part B contains 5 questions worth 5-13 marks each, involving binary to gray code conversion, TTL NAND gate operation, full adder/subtractor design, demultiplexer design, JK flip-flop explanation, shift register types, PLA design, and asynchronous circuit design. Part C contains 2 questions worth 15 marks each, about hazards in sequential circuits and 8 to 1 multiple

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    This document contains exam questions for a Digital Logic Circuits course. It is divided into three parts: Part A contains 10 multiple choice questions worth 2 marks each, covering topics like fan in/fan out, number systems, logic gate types, shift registers, hazards, PROM, and VHDL. Part B contains 5 questions worth 5-13 marks each, involving binary to gray code conversion, TTL NAND gate operation, full adder/subtractor design, demultiplexer design, JK flip-flop explanation, shift register types, PLA design, and asynchronous circuit design. Part C contains 2 questions worth 15 marks each, about hazards in sequential circuits and 8 to 1 multiple

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    45 views2 pages

    DLC Model I

    Uploaded by

    EEE DEPT
    This document contains exam questions for a Digital Logic Circuits course. It is divided into three parts: Part A contains 10 multiple choice questions worth 2 marks each, covering topics like fan in/fan out, number systems, logic gate types, shift registers, hazards, PROM, and VHDL. Part B contains 5 questions worth 5-13 marks each, involving binary to gray code conversion, TTL NAND gate operation, full adder/subtractor design, demultiplexer design, JK flip-flop explanation, shift register types, PLA design, and asynchronous circuit design. Part C contains 2 questions worth 15 marks each, about hazards in sequential circuits and 8 to 1 multiple

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    Reg No :

    6214-MAHABARATHI ENGINEERING COLLEGE - CHINNASALEM

    B.E./B.Tech. DEGREE EXAMINATION, OCT-2021


    Third Semester / Electrical and Electronics Engineering
    EE-8351 DIGITAL LOGIC CIRCUITS
    (Regulation 2017)
    Model EXAM -1
    DATE: 15.11.2021(AN) Maximum Marks:100
    TIME: 3.00 Hours
    Answer ALL Questions
    PART A — (10 × 2 = 20 Marks)

    1. Define Fan in and Fan out.


    2. Convert (19.625)10 to Binary,Octal and Hexadecimal Number System.
    3. Define min term and max term.
    4. Differentiate decoder and demultiplexer.
    5. Give the design steps for synchronous sequential circuit.
    6. What are the types of Shift Registers?
    7. Define hazards and its types.
    8. Define PROM.
    9. What is VHDL.
    10. Write the program for half adder using in VHDL.
    PART-B (13*5=65 Marks)

    11. a)i)Explain about binary to gray code conversion. (06)


    ii)Explain the operation of TTL NAND gate with a neat circuit diagram. (07)
    (OR)
    b) Name and Briefly Explain About Characteristics Of Digital IC’s. (13)
    12.a) Design and implement the full adder and full subtractor circuit using only NAND Gates.
    (OR)
    b) Design and implement 1 to 8 demultiplexer using AND Gates. (13)
    13.a) With neat digram .explain about JK flip-flop. (13)
    (OR)
    b)Explain about different types of shift registers. (13)
    14.a)Draw the block diagram of a PLA device and briefly explain each block. . (13)
    (OR)
    b).summarize the design procedure for asynchronous sequential circuit. (13)
    15.a)Explain the structure and working principles of TTL based Totem-pole output
    configuration. (13)
    (OR)
    b) Write a VHDL code to realize a half adder using behavioral modeling and structural modeling
    (13)
    PART-C (15*1=15 Marks)
    16. a)Illustrate about hazards in sequential circuits and the steps to avoid hazards in it. (15)
    (OR)
    b) Design and implement 8 to 1 multiplexer using AND Gates (15)
    Reg No :

    6214-MAHABARATHI ENGINEERING COLLEGE - CHINNASALEM

    B.E./B.Tech. DEGREE EXAMINATION, OCT-2021


    Third Semester
    Electrical and Electronics Engineering
    EE-8351 DIGITAL LOGIC CIRCUITS
    (Regulation 2017)
    Common Internal Assessment Test-I

    DATE: 22 .10.2021(AN) Maximum Marks: 50


    TIME: 1.30 Hours
    Answer ALL Questions
    PART A — (09 × 2 = 18 Marks)

    1. List out the Numbering System.


    2. Convert (19.625)10 to Binary,Octal and Hexadecimal Number System.
    3. Convert (3A.2F)16 to Decimal,Binary and Octal Number System.
    4. Convert (1100.1011)2 to Decimal, Hexadecimal and Octal Number System.
    5. How you will represent signed binary numbers in computers?
    6. Give A=1010 B=1111 perform (a)A-B (b)B-A using 1’s complement.
    7. Using 2’s Complement Perform (42)10 – (68)10.
    8. Define Fan in and Fan out.
    9. Define Noise Margin Noise Immunity.
    PART-B (10*2=20 Marks)

    10. a) Explain About Different Types Of Logic Gates. (10)

    (OR)

    b) Briefly Explain About Characteristics Of Digital IC’s. (10)

    11.a) Briefly Explain About Different Types Of Bipolar Logic Families. (10)

    (OR)

    b) Briefly Explain About Different Types Of Mos Families.(10)

    PART-C (12*1=12 Marks)

    12. Explain About Different Types Of Numbering System. Give Example For Each. (12)

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