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    Chapter 5 A - DLD (Dr. Nauman)

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    Bangle Ch
    1) The document describes synchronous sequential logic and edge-triggered flip-flops. 2) Edge-triggered flip-flops change state at a specified point (positive or negative edge) on a clock signal, unlike latches which change state at any time the control signal is active. 3) An S-R flip-flop will set (Q=1) on a positive clock edge if S is high and R is low, reset (Q=0) if R is high and S is low, or retain its current state if both inputs are low or high.

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    Chapter 5 A - DLD (Dr. Nauman)

    Uploaded by

    Bangle Ch
    25 views16 pages
    1) The document describes synchronous sequential logic and edge-triggered flip-flops. 2) Edge-triggered flip-flops change state at a specified point (positive or negative edge) on a clock signal, unlike latches which change state at any time the control signal is active. 3) An S-R flip-flop will set (Q=1) on a positive clock edge if S is high and R is low, reset (Q=0) if R is high and S is low, or retain its current state if both inputs are low or high.

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    Chapter 5 a - DLD (Dr. Nauman)

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    1) The document describes synchronous sequential logic and edge-triggered flip-flops. 2) Edge-triggered flip-flops change state at a specified point (positive or negative edge) on a clock signal, unlike latches which change state at any time the control signal is active. 3) An S-R flip-flop will set (Q=1) on a positive clock edge if S is high and R is low, reset (Q=0) if R is high and S is low, or retain its current state if both inputs are low or high.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    25 views16 pages

    Chapter 5 A - DLD (Dr. Nauman)

    Uploaded by

    Bangle Ch
    1) The document describes synchronous sequential logic and edge-triggered flip-flops. 2) Edge-triggered flip-flops change state at a specified point (positive or negative edge) on a clock signal, unlike latches which change state at any time the control signal is active. 3) An S-R flip-flop will set (Q=1) on a positive clock edge if S is high and R is low, reset (Q=0) if R is high and S is low, or retain its current state if both inputs are low or high.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 16

    EE1001 - Digital Logic Design

    Chapter 5
    Synchronous Sequential Logic

    Dr. Nauman Razzaq


    Sequential Circuit
    ▪A sequential circuit consists of a feedback path, and employs
    some memory elements.
    Combinational
    outputs Memory outputs

    Combinational Memory
    logic elements

    External inputs

    Sequential circuit = Combinational logic + Memory Elements


    2
    Sequential Circuits
    Asynchronous
    Inputs Outputs
    Combinational
    Circuit
    Memory
    Elements

    Synchronous
    Inputs Outputs
    Combinational
    Circuit
    Flip-flops
    Clock
    3
    Memory Elements
    ▪Memory element: a device (latch) which can remember value
    indefinitely, or change value on command from its inputs.

    Memory Q
    command element stored value

    ▪Characteristic table:

    Command Q(t) Q(t+1)


    (at time t)
    Q(t): current state
    Set X 1
    Q(t+1) or Q+: next state
    Reset X 0
    Memorise / 0 0
    No Change 1 1 4
    Memory Elements
    ▪Synchronous Memory element
    These are memory element with clock, known as Flip-flops that change
    state on clock signals.
    Memory Q
    command element stored value

    ▪ Triggering/activation
    clock
    ❖pulse-triggered
    ❖edge-triggered
    Positive pulses
    ▪Pulse-triggered
    ❖latches
    ❖ON = 1, OFF = 0
    ▪Edge-triggered Positive edges Negative edges
    ❖flip-flops
    ❖positive edge-triggered (ON = from 0 to 1; OFF = other time)
    ❖negative edge-triggered (ON = from 1 to 0; OFF = other time)
    Memory Elements
    S-R Latch
    ▪Complementary outputs: Q and Q'.
    S Q
    ▪When Q is HIGH, the latch is in SET state.
    R Q'
    ▪When Q is LOW, the latch is in RESET state.

    ▪Characteristic table (active-HIGH input S-R latch):


    S R Q Q'

    0 0 NC NC No change. Latch
    remained in present state.
    1 0 1 0 Latch SET.
    0 1 0 1 Latch RESET.
    1 1 0 0 Invalid condition.
    S-R Latch

    ▪Active-HIGH input S-R latch

    10 100 R S R Q Q'
    Q 11000
    1 0 1 0 initial
    0 0 1 0 (afer S=1, R=0)
    0 1 0 1
    Q' 0 0 1 1 0
    10 001 S 0 0 0 1 (after S=0, R=1)
    1 1 0 0 invalid!
    Latches
    ▪Active-HIGH input S-R latch
    S R Q
    R Q Q0 No change
    0 0
    0 1 0 Reset
    1 0 1 Set
    S Q 1 1 Q=Q’=0 Invalid

    ▪Active-LOW input S-R latch (also known as S’R’ latch)


    S R Q
    S Q 0 0 Q=Q’=1 Invalid
    0 1 1 Set
    1 0 0 Reset
    R Q 8
    1 1 Q0 No change
    Controlled Latches
    SR Latch with Control Input
    R R S S
    Q Q
    C C
    S Q R Q
    S R

    C S R Q
    0 x x Q0 No change
    1 0 0 Q0 No change
    1 0 1 0 Reset
    1 1 0 1 Set 9

    1 1 1 Q=Q’ Invalid
    Controlled Latches
    Gated D Latch (D = Data)
    Timing Diagram
    ▪Make R input equal to S' → gated D latch.
    C
    ▪D latch eliminates the undesirable condition
    of invalid state in the S-R latch.
    D
    D S
    Q Q
    C
    R Q t
    Output may
    C D Q change
    0 x Q0 No change
    1 0 0 Reset 10
    1 1 1 Set
    Controlled Latches
    D Latch (D = Data) Timing Diagram

    S
    C
    D
    Q
    C D
    R Q
    Q

    C D Q Output may
    0 x Q0 No change change
    1 0 0 Reset
    1 1 1 Set
    11
    Latch Circuits: Suitability

    ▪Latch circuits are not suitable in synchronous logic circuits.


    ▪When the control (enable) signal is active, the excitation inputs
    are gated directly to the output Q. Thus, any change in the
    excitation input immediately causes a change in the latch
    output.
    ▪The problem is solved by using a special timing control signal
    called a clock to restrict the times at which the states of the
    memory elements may change.
    ▪This leads us to the edge-triggered memory elements called
    flip-flops.
    Edge-Triggered Flip-flops

    ▪Flip-flops: synchronous bistable devices


    ▪Output changes state at a specified point on a triggering
    input called the clock.
    ▪Change state either at the positive edge (rising edge) or at
    the negative edge (falling edge) of the clock signal.

    Clock signal

    Positive edges Negative edges

    13
    Triggering - Latches and Flip-Flops
    Controlled latches are level-triggered

    Flip-Flops are edge-triggered

    CLK Positive Edge

    CLK Negative Edge

    14
    S-R Flip-flop

    ▪S-R flip-flop: on the triggering edge of the clock pulse,


    ❖S=HIGH (and R=LOW) a SET state
    ❖R=HIGH (and S=LOW) a RESET state
    ❖both inputs LOW a no change
    ❖both inputs HIGH a invalid

    ▪Characteristic table of positive edge-triggered S-R flip-flop:


    S R CLK Q(t+1) Comments
    0 0 X Q(t) No change
    0 1  0 Reset
    1 0  1 Set
    1 1  ? Invalid
    X = irrelevant (“don’t care”)
     = clock transition LOW to HIGH 15
    S-R Flip-flop
    ▪Characteristic table S R CLK Q(t+1) Comments

    (+ive edge-triggered S-R flip-flop) 0 0 X Q(t) No change


    0 1  0 Reset
    1 0  1 Set
    1 1  ? Invalid
    ▪It comprises 3 parts:
    ➢ a basic NAND latch X = irrelevant (“don’t care”)
    ➢ a pulse-steering circuit  = clock transition LOW to HIGH
    ➢ a pulse transition detector (or edge
    detector) circuit
    ▪The pulse transition detector S
    Q
    detects a rising (or falling) edge Pulse
    transition
    and produces a very short- CLK detector
    duration spike. Q'
    R

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