Dell Optiplex 790 - Gold Coast - MTDT A00 PDF

5 4 3 2 1
D D
Gold Coast- MT / DT
C C
Intel PROCESSOR SANDY BRIDGE LGA1155
B
Intel Cougar Point B
REV A00
A A
Title
TBD
DWG NO Rev
A00
Gold Coast_MT/DT
Date: Friday, December 24, 2010 Sheet 19 of 70
5 4 3 2 1
5 4 3 2 1
1. Index / Block diagram

2. SMBus MAP
3. Clock Distribution Page 20 Page 65 ~ 70
4. Power Delivery Map CK505 CLOCK Gen VRD12 / VRM / Linear CHANNEL A DDR3 SDRAM (1066/1333)
DDR3 DIMM 1
D
5. Power On Sequence Page 15, 16
D
DDR3 DIMM 3
6. Reset / Power Good Map Intel PROCESSOR
7. Strap/IRQ/IDSel Table SANDY BRIDGE
XDP CHANNEL B DDR3 SDRAM (1066/1333)
8. GPIO Table Page 52 LGA1155 DDR3 DIMM 2
9-14. CPU Page 17, 18
DDR3 DIMM 4
15-16. DDR3 Conn: CHA PCIe Gen2 16x
PCIe 16x slot X1
17-18. DDR3 Conn: CHB Page 38 Page 9-14
19. TBD
FDI
DMI
20. Clock GEN
21-30. PCH Page 35
DP Link PCIe 1x Intel NIC + USB
31. PCH MISC Conn/BUZ/ID DISPLAY PORT Ports X 2
32-33. SIO:SMSC5544 Page 41 Page 34 Lewisville
34-35. LAN: INTEL LEWISVILLE VGA Port 0/1
VGA CONN
36-37 AUDIO:ALC269Q Page 42
C 38. Slot1: PCIe 16x Port 2 ~ 5 C
PCI Rear USB Ports X4

39. Slot4: PCIe 4x PCI Slot X1 Page 45
40. TBD Page 58
41. Display Port
PCIe 16x Slot X1 PCIe Gen2 4x
Intel USB 2.0 Port 6/7/10/11
Page 56
Front USB Ports X4
42. VGA Conn
43. SATA Conn
(wired as 4x signal) Page 39 Cougar Point Port 8/9
Internal USB
44. TBD Page 61
45. Rear USB PCIe 1x Slot X1 PCIe Gen2 1x Header X1
46. TPM & TCM Page 59
47. Thermal Sensor Conn Page 37
48. FAN HDA Rear Audio CONN
ALC269Q
49. PS2 Conn Page 36 Line In (MIC In)/Line Out
50. COM1
51. SPI XDP
Page 52 Front Audio CONN
B
52. XDP HP Out/ MIC In B
53. Pilot Run Conn Page 21-30

54. EMI Page 56
55. COM2 HDR SATA Port 0 LPC
SATA 3.0 CONN X1
56. Front_Panel Page 43
57. TBD SATA Port 1/ 2
SATA 2.0 CONN X2 SMSC5544 TPM/TCM
58. Slot3: PCI Page 43
59. Slot2: PCIe 1x Page 32 Page 46
SATA Port 3
60. SATA_MT SATA 2.0 CONN X1 (MT) (TCM is just reserved because
61. Flexbay USB_MT Page 60 MRD has removed TCM requirement)
62. PRT Port_MT SERIAL PS2 Printer (MT)
63. Power Conn Ports X2 KB/MS Port
64. Power Sequence Page 50, 55 Page 49 Page 62
65-66. Power: Linear Power
67-68. Power: Vcore PWM
SPI ROM SPI
A
69. Power: VCCIO/VCCSA 2M+8M
A
70. Power: DDR3/5Vdual/5VUSB Page 51
Title
Index / Block diagram

DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
D D
DIMM 2
Channel B
DIMM 4
DIMM 1 C_PCIEX1_1/C_PCIEX1#_1
C_PCI_SB MINI PCIe
Channel A
DIMM 3 C_PCI_SL1
25 MHZ
PCI SLOT SLOT 3
D3_MA_CLK/CLK#[0:3]
D3_MB_CLK/CLK#[0:3]
C_PCIEX16_1/C_PCIEX16#_1
C PCI EXPRESS X16 SLOT 1 C
PCH C_PCIEX1_2/C_PCIEX1#_2
32.768 KHZ
PCI EXPRESS X1 SLOT 2
Buffer Through Mode C_PCIEX4_1/C_PCIEX4#_1
PCI EXPRESS X4 SLOT 4
C_PE_100M_MCP/MCP#
CPU C_SRC1_PCH/C_SRC1_PCH#
PCH XDP
C_SATA_PCH/PCH#
C_96M_PCH/PCH#
C_DMI_PCH/PCH#
B
C_14M_TPM B
C_LPC_TPM
TPM/TCM
C_14M_MCH
25 MHZ LAN 82579 C_PCIE_L1/L1#

C_LPC_TPM
LPC HEADER
CK505
C_LPC_SIO
CLOCK CHIP
C_CK505_ITP/ITP#
SUPER IO C_14M_SIO CPU XDP
A A
T itl e
Clock Distribution
14.318 MHZ DWG NO Re v
A00
Gold Coast_MT/DT
Da te : Fri day, Dece m ber 2 4, 2010 Sheet 3 of 70
5 4 3 2 1
5 4 3 2 1
POWER DELIVERY MAP

Deep Sleep : Off
Default : S0 VCC_CORE
PSU P-FET 0.016A ME : Mx/Moff ON NCP6151+NCP5901
+3V_S5 +12V_CPU S0
2X12 FDN340P +3V_EPW VRD12 switcher, 4ph +VCORE S0
+5VSB S5,S0,S3,S4 +3V_Dual Linear
+5V S0 Switch SVID
Fairchild
5V 85A TDC; 112A ICCMAX
10.5A FAN5078D3 /N AOS452 +3V_Dual S5,S0,S3,S4
resistor, empty
LL = 1.7m ohms
+3V S0 +/-5% DC + AC
H=Power on
D +3V S0 D
S_SLP_M# H=Power on
3V L=Power off
S_SLP_S3#
3.4A L=Power off
+12V S0 H=Power on
12V resistor, empty +1P05V_VCCIO
L=Power off
6.1A
Deep Sleep : Off
-12V S0 Deep Sleep : Off
-12V Default S5,S0,S3,S4 VCC_AXG
P-FET Default S5,S0,S3,S4 P-FET ON NCP6151+NCP5901
+3V_Dual +3V_S5 +3V_PCIAUX
FDN340P FDN340P VRD12 switcher, 1ph
S5,S0,S3,S4 +3V_S5 S0=1.5A, +1P1V_AXG S0
+5VSB Switch Switch SVID
5VSB S3~5=0.45A
25A TDC; 35A ICCMAX
H=Power on H=Power on LL = 4.1m ohms
2X2 SLP_SUS_FET# S_SLP_S4#
L=Power off L=Power off
+12V_CPU S0 H=Power on
12V H=Power on S_SLP_S3#
S_PCIAUX_GATE L=Power off
9.6A L=Power off
resistor, empty
H=Power on
Current listed are for Deep Sleep : Off +1P05V_VCCIO
a typical 265W PSU L=Power off
C Default : S0 C
ME : Mx/Moff
P-FET +3V_S5 P-FET 0.218A VCCIO
+5VSB S5,S0,S3,S4
Default S5,S0,S3,S4 +3V_LAN
FDN340P +5V_S5 SI4835DDY ON NCP1589A
Switch Switch Switcher, 1ph +1P05V_VCCIO S0
17A Imax
H=Power on H=Power on +/-0.5% DC, +/-4.5% AC
SLP_SUS_FET# S_SLP_LAN# 1-bit VID(1.05V/1.0V)
L=Power off L=Power off
H=Power on
0.375A +1P05V_PCH
+3V S0 LDO resistor, empty
+V_1.5V_PCIE S0 L=Power off
NCP1117STAT3G
DDR3 DDR3 Vtt VCCSA

+5VSB S5,S0,S3,S4 +5V_DUAL S0,S3 Fairchild FAN5078D3 +1P5V_SM S0,S3, Fairchild FAN5078D3 ON NCP1589A
P NTGS4111PT
Switcher, 1ph Linear +1P5V_SM_VTT Switcher, 1ph
+5V S0 N AOS452 S0,S3, +V_VCCSA S0
1.5V, 26.5A Imax 0.75V, 1A TDC 8.8A Imax
Switch
B +/- 5% DC+ AC +/- 5% DC+ AC +/-5% DC + AC B
1-bit VID(0.925V/0.85V)
H=Power on
H = +5V S0 S_SLP_S4#
B_ATX_PWROK L=Power off H=Power on
L = +5VSB S3 S_SLP_S3#
PCH Core L=Power off
H=Power on Linear OP LM358
S_SLP_S3# +1P05V_PCH S0 H=Power on
L=Power off 1.05V, 6.2A Imax
VCCIO_PWRGD
+/- 5% DC+ AC L=Power off
H=Power on
Non-AMT
S_SLP_S3#
L=Power off stuff resistor, SFR
empty for ME Linear OP LM358
+3V S0
1.8V, 1.6A Imax +1P8V_SFR S0
+/-5% DC + AC
Deep Sleep : Off

Default S5,S0,S3,S4 Default S0
PCH ME (AMT only)
ME : Mx/Moff
A +5V_S5 Richtek RT8015 A
Switcher, 1ph +1P05V_ME
1.05V, 1.8A Imax
+/- 5% DC+ AC
Title
H=Power on
S_SLP_M#
L=Power off
Power Delivery Map
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
SMBUS DIAGRAM
SMdata2
SMdclk2
5544 SIO
Intel Lewisvillies Clock Generator
D D
LOM SMdata1
SMdclk1 IDTCV184-2APAG8
Write : 0 X D2
Read : 0 X D3
RO31/RO32 R015/RO16
SMLINK0
SMBus SMLINK1 QO4/QO5

Controller
BUS Switch
RESUME SMBUS Main SMBUS
C
PCH C
CPU-XDP PCH-XDP
RX5/RX6 RX3/RX4 RX1/RX2 RX9/RX10
PCIE 16x SMBUS

PCIE 4x SMBUS
Mini-PCIe 1x
PCI EXPRESS 16x SLOT 1

PCIE 1x SMBUS
PCI EXPRESS 16x (wired as 4x signal) SLOT 4

B B
PCI SMBUS
PCI EXPRESS 1x SLOT 2
PCI SLOT SLOT 3
DDR3 DIMM1 CHA Address : 0 X00

DIMM SLOTS
DDR3 DIMM3 CHA Address : 0 X02
DDR3 DIMM2 CHB Address : 0 X04
A A
DDR3 DIMM4 CHB Address : 0 X06
T itl e
BLOCK DIAGRAM
DWG NO Re v
A00
Gold Coast_MT/DT
Da te : Fri day, Dece m ber 2 4, 2010 Sheet 2 of 70
5 4 3 2 1
5 4 3 2 1
POWER ON Timing Diagram
O_PS_ON#
G3 to S4/S5 Timing Diagram
PCI/PCIe:100ms min
t226 S_SLP_S3#
VccRTC
t200 Power rails rise
0.2 20ms
+12V/+5V
D RTCRST# PSU: <=20ms D
t225 Power rails rise

0.2 20ms
+3V
VCCSUS
t201 =500ms
+1P5V_SM
RSMRST# t202
=50ms
+1P05V_VCCIO Uncorepwrgood assertion
SUSCLK
=50ms
+1P8V_SFR T17 MAX TBDns
SLP_S5# VCCSA VID[0] Buffers Output is

stable after VccIO Ramp VCCUSA VID[0] FINAL
H_VCCSA_VID
Uncorepwrgd must be stable (low) at this time
Ramp not to exceed 50mV/us
Recommended that VccSA ramp after VCCIO has

remped to ensure VCCSA_VID[0] is stable
VSAFINAL
=50ms
VSABOOT=SNB Vmax
+V_VCCSA Typ 60us
Depends on exact SVID
Deep Sleep Entry EN
RC VIH
TA transactions between CPU T
C
VR:5ms max
and VR TB 8
CPU:
C
A A Set VID A A GETReg A A

400us min
CPU SVID buffers are Hi-Z once VCCIO is T1 C C SLOW C C status C C
Pay Set VID Satus
DPWROK stable and Uncorepowergood=0 MISC K
0
K
1
Packet K
0
K
1 TD Packet K K
0 1 load Packet Packet
SVIDs CPU:
(VIDSOUT/VIDCLK) 500us max VR:2ms max
C
T
SUSWARN# Note5: Core and GT power supplies should not source current during this time. VR:5us max
+VCORE CPU
Packet
CPU SVID buffers are Hi-Z once VCCIO is T

SUS_PWR_ACK stable and Uncorepowergood=0 E
SAlert#I VR:1us max
GT
VIDALERT# Packet
T F
SLP_SUS# VR:min=Te,5ms max TC
VR_Ready =5ms
Feed into PCH PCH(t1001) VR:5us max
SYS_PWROK
RSMRST# Note5: Core and GT power supplies should not source current during this time. GT Ramp will occur after PLTRST#
+1P1V_AXG
T14
Min 10 PCIe bclks T 13 Min 10 PCIe bclks
1.05V
+5VDUAL Srtaps=CFG[x} Strapping option
Inactive / Disable
+5V_S5/+3V_S5 T11 Note: PCH THERMAL WATCHDOG TIMER WILL BE DISABLED WITH SNB. Enable
S_Thermtrip# SNB WILL NOT EXCEED VR IMAX UNTIL THERMTRIP# IS ENABLED T 12
CPU:[x]ms min CPU:[x]ms min
B T 10 B
CPU:1ms min
H_SM_DRAMPWRGD
(xxDRAM_PWROK)
Note:DDR spec reuqires that DDR_RESET# be

asserted during power ramp cycle BIOS will deassert DDR_RESET#
D3_RESET#
PCH t34
Deep Sleep Exit PSU (1ms)
100ms~500ms Min 10 PCIe bclks PCH: No min/max requirement

PWRGD_3V
Feeds into PCH_PWROK
DPWROK BCLK, PCIe

PCH t573
CLKs (1, 5, 50, or 100ms)
SLP_SUS# Note4:Uncorepwergood must be at 2
T CPUPWRGOOD
a valid level during all power states CPU:5ms min, 650ms max
UNCOREPWRGOOD AND PCH t1001
(PROCPWRGD) SYS_PWROK(VR_READY) 30us, 1, 2or 5ms
RSMRST# T =PCH_PWROK & SYS_PWROK &

6
S_RLTRST# CPU:1ms min, 100ms max t1001 Timer expired & internal_ready
+5V_S5/+3V_S5 T?
DMI
SUSWARN# DMI training CPU_RESET_DONE

CPU_RESET_DONE_ACK
A A
SUS_PWR_ACK
+5VDUAL
Title
Power On Sequence
DWG NO Rev
Gold Coast_MT/DT A00

5 4 3 2 1
5 4 3 2 1
RESET / Power Good MAP Deep Sleep Exit MAP

Sequence Signal Name: CPU-Sandy Bridge Sequence Signal Name:
UNCOREPWRGOOD
SM_DRAMPWROK
O_PWRBTN#IN
SM_DRAMRST*
(1) (D1) O_PWRBTN#IN
D
(2) S_SLP_S4# S_SLP_S3# S_SLP_M# (D2) S_SLP_SUS# D
(3) O_PSON# (D3) S_RSMRST#
RESET*
B_ATX_PWROK PROCPWRGD
(4) (D4) S_SUSWARN#
(5) PCH_MEPWRGD PWROK (D5) S_SUS_PWR_ACK#
(6) S_PCH_SYSPWROK P_VR_READY > 1ms
(7) PWRGD_3V
(8) H_DRAMPWRGD D3_RESET# (9) (10)
(9) H_PWRGD
(10) S_PLTRST# H_RESET#_R S_PLTRST#_R (8)
DDRIII Slots
D3_RESET#
(11) X_PLTRST_PCIE_SLOT# K_PCIRST#_SLOT Buffer (UH2)
(12) A_Z_RST#
(9)
(10) LAN
PE_RST_N
CPU-XDP (1)
(10) TPM/TCM
C
PCH-XDP (1) LRESET# C
F_TP_XDP_RST
Front Panel
O_PWRBTN#IN
(1)
PWRBTN#
PROCPWRGD
Power On Botton (1) (1) (8)

O_PWRBTN#IN PWRBTN# DRAMPWROK (11)
Mini-PCIe
(D1) PCI_RST_SYS# PERST#
(10)
PLTRST# LRESET#
ATX Power
(3)
VRD 12 PS_ON# PSON
(6) (7)
VR_RDY SYS_PWROK AND PWROK PWR_GOOD_3V (4)
PWRGD_PS PWROK
(2)
B
SLP_S3# SLP_S3# B
PCH (2)
SIO-5544
SLP_S4# SLP_S4_S5# PWR_GOOD_3V
RESET BUTTON
FP_RST# SYS_RESET# (2) PWRGD_PS
SLP_A# IO_SMI#
100~120ms
HD Audio (12) RSMRST#
RESET# HDA_RST#
(D3)
SUSWARN#
SLP_SUS#
ME POWER-GOOD Sequence
SUSACK#
CIRCUIT Logic
(5) Circuit
PCH_MEPWRGD APWROK Page.64
PCH_MEPWRGD (D5) (D4) (D2)

+1P05V_ME
A
> 1ms A
+5VDUAL Sequence +5V_S5/+3V_S5

Logic
SUSACK# Circuit SLP_SUS#
Title
Page.64
Reset / Power Good Map
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
RH4 usage 1kOhm ; CRB 0.7-12/10/09

Removed RH3; CRB 0.7-12/29/09
UH1E Dummy RH6 ; CRB 0.7-12/28/09
Removed RH7; CRB 0.7-12/10/09
W2 P34 +1P05V_VCCIO
[27] C_PE_100M_MCP W1 BCLK0 VCCSA_VID T2 H_VCCSA_VID [69]
[27] C_PE_100M_MCP# BCLK0* VCCSA_SENSE H_VCCSA_SENSE [69] RO40change reference to
A36 RH7 and move from SIO to
H_VIDSCLK C37 VCC_SENSE B36 H_VCC_SENSE [67]
RH2 change to 44.2 ; H_VIDSOUT B37 VIDSCLK VSS_SENSE H_VSS_SENSE [67] CPU side ; CRB *RH7 *RH4 *RH5 *RH6
**
H_VIDALERT# RH2 44.2Ohm A37 VIDSOUT AB4 0.7-12/29/09 51 Ohm 51 Ohm 51 Ohm
CRB0.7 12/07/09 VIDALERT* VCCIO_SENSE H_VCCTT_SENSE [69] 1K
+/-1% AB3 Dummy Dummy Dummy
D RH1 49.9 VSSIO_SENSE H_VSSTT_SENSE [69]
D
+1P05V_VCCIO
Dummy +/-1% J40 L32 H_PROCHOT#
[24,52,64] H_PWRGD UNCOREPWRGOOD VCCAXG_SENSE M32 H_VCCAGX_SENSE [67] H_PECI
Change net name to H_RESET#_R F36 VSSAXG_SENSE H_VSSAGX_SENSE [67]
+3V_S5 H_THERMTRIP#
RESET* L39 H_CATERR
H_RESET#-12/28/09 TDO H_TDO [52]
E38 L40
[23] H_PM_SYNC J35 PM_SYNC TDI M40 H_TDI [52]
[23,32] H_PECI H_CATERR E37 PECI
CATERR*
TCK
TMS
L38 H_TCK [52]
H_TMS [52]
*RH66
220
H34 J39 +/-5%
[32,67] H_PROCHOT# G35 PROCHOT* TRST* K38 H_TRST# [52] Dummy
[23] H_THERMTRIP# THERMTRIP* PRDY* K40 H_PRDY# [52]
*
AJ33 PREQ* E39 H_PREQ# [52] RH9 0
[23,24] H_SKTOCC# H_PROC_SEL K32 SKTOCC* DBR* C40 FP_RST# [24,52,53]
+1P05V_VCCIO
[52] H_CFG0 PROC_SEL RSVD36 D40 H_ITPCLK [52] Add RH66 pull-up to +3V_DUAL;
******************
Add off-page toXDP; CRB 0.7 RH10 1.5K Dummy H_CFG0 H36 RSVD0 H_ITPCLK# [52]
CFG0 CRB 0.7-12/10/09 Close to
12/27/09 RH11 1.5K Dummy H_CFG1 J36 H40
*
RH12 1.5K Dummy H_CFG2 J37 CFG1 BPM0* H38 H_BPM#0 [52] H_TDO XDPRH18
Conn 51 Ohm
RH13 1.5K Dummy H_CFG3 K36 CFG2 BPM1* G38 H_BPM#1 [52]
RH14 1.5K Dummy H_CFG4 L36 CFG3 BPM2* G40 H_BPM#2 [52]
RH15 1.5K Dummy H_CFG5 N35 CFG4 BPM3* G39 H_BPM#3 [52]
****
RH16 1.5K Dummy H_CFG6 L37 CFG5 BPM4* F38 H_BPM#4 [52] H_TDI RH21 51 Ohm
RH19 1.5K Dummy H_CFG7 M36 CFG6 BPM5* E40 H_BPM#5 [52] H_TMS RH23 51 Ohm
RH20 1.5K Dummy H_CFG8 J38 CFG7 BPM6* F40 H_BPM#6 [52] H_TCK RH25 51 Ohm
RH22 1.5K Dummy H_CFG9 L35 CFG8 BPM7* H_BPM#7 [52] H_TRST# RH27 51 Ohm
RH24 1.5K Dummy H_CFG10 M38 CFG9
RH26 1.5K Dummy H_CFG11 N36 CFG10 AB6
CFG11 RSVD1 Close to
RH28 1.5K Dummy H_CFG12 N38 AB7
RH29 1.5K Dummy H_CFG13 N39 CFG12 RSVD2 AD37 CPU
RH30 1.5K Dummy H_CFG14 N37 CFG13 RSVD3 AE6
C RH31 1.5K Dummy H_CFG15 N40 CFG14 RSVD4 AF4 20100107: C
RH32 1.5K Dummy H_CFG16 G37 CFG15 RSVD5 AG4
CFG16 RSVD6 Remove test points
RH33 1.5K Dummy H_CFG17 G36 AJ11
CFG17 RSVD7 AJ29
A38 RSVD8 AJ30
AU40 NCTF0 RSVD9 AJ31
AW38 NCTF1 RSVD10 AN20
C2 NCTF2 RSVD11 AP20
*
D1 NCTF3 RSVD12 AT11 RH35 0 RH61 178 Ohm
NCTF4 RSVD13 AT14 [32] H_RESET# H_RESET#_R [52]
Dummy +/-1%
AH1 RSVD14 AU10
[18] H_CPU_DIMM_VREF_B
[16] H_CPU_DIMM_VREF_A
AH4 FC_AH1
FC_AH4
RSVD15
RSVD16
AV34 +3V_DUAL *RH62
75
AW34 +/-1%
AV1 RSVD17 AY10
RSVD_NCTF0 RSVD18
MISC
AW2 C38 CH2 0.1uF
AY3 RSVD_NCTF1 RSVD19 C39
RSVD_NCTF2 RSVD20 D38 16V, X7R, +/-10%
5
RSVD21 H7
RSVD22
UH2 Change H_RESET# source from SIO
R34 H8 1
R36 RSVD40 RSVD23 J33 [24,32,34,46,52,53] S_PLTRST# 4 directly-12/28/09
R38 RSVD41 RSVD24 J34 2
RSVD42 RSVD25 20100104: add UH2 to prevent SIO
R40 J9
J31 RSVD43 RSVD26 K34 can't use
3
AD34 RSVD44 RSVD27 K9 74AHCT1G08GW
AD35 RSVD45 RSVD28 L31
H_PWRGD K31 RSVD46 RSVD29 L33
RSVD47 RSVD30 L34
RSVD31 L9
B
*RH58 RSVD32
RSVD33
M34
B
1K N33
RSVD34 N34
RSVD35 P33 H_VCCIO_SEL +V_NAND_IO
VCCP_SELECT P35
RSVD37 P37
RSVD38 P39
20100709: Reserve RH58 connect H_PWRGD to GND RSVD39 *RH60
5/10 2.2K
*
RH17 H_PROC_SEL
[25] M_NVR_CLE
4.7K
PE115527-4041-0DF CH11
0.1uF
16V, X7R, +/-10%
Dummy
+5V RH17 change to 4.7k; CRB 0.7-11/30/09

+1P05V_VCCIO 20100709: Reserve CH11 connect H_PROC_SEL to GND
*RH37
10K
RH38 * RH39 * RH40 * H_VCCIO_SEL [69]
91 Ohm 110Ohm 75
+/-1% +/-1% +/-1%
Dummy *RH34
4.7K
[67] H_VIDSCLK
[67] H_VIDSOUT
A [67] H_VIDALERT# A
Remove CH1,CH2-12/29/09 Add H_VCCIO_SEL circuit; CRB 0.7-12/03/09

RH39 change to 110 ohm; CRB 0.7-11/30/09
Title
CPU-1: MISC
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
UH1C
[38] X_1X16_RXP[15..0] X_1X16_TXP[15..0] [38]
X_1X16_RXP0 B11 C13 X_1X16_TXP0
[38] X_1X16_RXN[15..0] B12 PEG_RX0 PEG_TX0 C14 X_1X16_TXN[15..0] [38]
X_1X16_RXN0 X_1X16_TXN0
X_1X16_RXP1 D12 PEG_RX0* PEG_TX0* E14 X_1X16_TXP1
X_1X16_RXN1 D11 PEG_RX1 PEG_TX1 E13 X_1X16_TXN1
D X_1X16_RXP2 C10 PEG_RX1* PEG_TX1* G14 X_1X16_TXP2 D
X_1X16_RXN2 C9 PEG_RX2 PEG_TX2 G13 X_1X16_TXN2
UH1D X_1X16_RXP3 E10 PEG_RX2* PEG_TX2* F12 X_1X16_TXP3
X_1X16_RXN3 E9 PEG_RX3 PEG_TX3 F11 X_1X16_TXN3
AC5 AC8 X_1X16_RXP4 B8 PEG_RX3* PEG_TX3* J14 X_1X16_TXP4
[25] H_FDI_FSYNC0 AC4 FDI_FSYNC0 FDI_TX0 AC7 H_FDI_TXP0 [25] X_1X16_RXN4 B7 PEG_RX4 PEG_TX4 J13 X_1X16_TXN4
[25] H_FDI_LSYNC0 FDI_LSYNC0 FDI_TX0* AC2 H_FDI_TXN0 [25] X_1X16_RXP5 C6 PEG_RX4* PEG_TX4* D8 X_1X16_TXP5
FDI_TX1 H_FDI_TXP1 [25] PEG_RX5 PEG_TX5
PEG
AC3 X_1X16_RXN5 C5 D7 X_1X16_TXN5
AE5 FDI_TX1* AD2 H_FDI_TXN1 [25] X_1X16_RXP6 A5 PEG_RX5* PEG_TX5* D3 X_1X16_TXP6
[25] H_FDI_FSYNC1 AE4 FDI_FSYNC1 FDI_TX2 AD1 H_FDI_TXP2 [25] X_1X16_RXN6 A6 PEG_RX6 PEG_TX6 C3 X_1X16_TXN6
[25] H_FDI_LSYNC1 FDI_LSYNC1 FDI_TX2* AD4 H_FDI_TXN2 [25] X_1X16_RXP7 E2 PEG_RX6* PEG_TX6* E6 X_1X16_TXP7
FDI_TX3 AD3 H_FDI_TXP3 [25] X_1X16_RXN7 E1 PEG_RX7 PEG_TX7 E5 X_1X16_TXN7
FDI_TX3* H_FDI_TXN3 [25] PEG_RX7* PEG_TX7*
FDI
AG3 X_1X16_RXP8 F4 F8 X_1X16_TXP8
[25] H_FDI_INT FDI_INT AD7 F3 PEG_RX8 PEG_TX8 F7
FDI_TX4 AD6 H_FDI_TXP4 [25] X_1X16_RXP9 G2 PEG_RX8* PEG_TX8* G10 X_1X16_TXP9
FDI_TX4* AE7 H_FDI_TXN4 [25] X_1X16_RXN9 G1 PEG_RX9 PEG_TX9 G9 X_1X16_TXN9
FDI_TX5 AE8 H_FDI_TXP5 [25] X_1X16_RXP10 H3 PEG_RX9* PEG_TX9* G5 X_1X16_TXP10
*
RH41 24.9 AE2 FDI_TX5* AF3 H_FDI_TXN5 [25] X_1X16_RXN10 H4 PEG_RX10 PEG_TX10 G6 X_1X16_TXN10
+1P05V_VCCIO FDI_COMPIO FDI_TX6 H_FDI_TXP6 [25] PEG_RX10* PEG_TX10*
+/-1% AF2 X_1X16_RXP11 J1 K7 X_1X16_TXP11
FDI_TX6* AG2 H_FDI_TXN6 [25] X_1X16_RXN11 J2 PEG_RX11 PEG_TX11 K8 X_1X16_TXN11
AE1 FDI_TX7 AG1 H_FDI_TXP7 [25] X_1X16_RXP12 K3 PEG_RX11* PEG_TX011 J5 X_1X16_TXP12
FDI_ICOMPO FDI_TX7* H_FDI_TXN7 [25] X_1X16_RXN12 K4 PEG_RX12 PEG_TX12 J6 X_1X16_TXN12
X_1X16_RXP13 L1 PEG_RX12* PEG_TX12* M8 X_1X16_TXP13
4/10 PEG_RX13 PEG_TX13
X_1X16_RXN13 L2 M7 X_1X16_TXN13
X_1X16_RXP14 M3 PEG_RX13* PEG_TX13* L6 X_1X16_TXP14
PE115527-4041-0DF M4 PEG_RX14 PEG_TX14 L5
X_1X16_RXP15 N1 PEG_RX14* PEG_TX14* N5 X_1X16_TXP15
X_1X16_RXN15 N2 PEG_RX15 PEG_TX15 N6 X_1X16_TXN15
PEG_RX15* PEG_TX15*
C C
W5 V7
[22] H_DMI_RXP0 W4 DMI_RX0 DMI_TX0 V6 H_DMI_TXP0 [22]
[22] H_DMI_RXN0 V3 DMI_RX0* DMI_TX0* W7 H_DMI_TXN0 [22]
[22] H_DMI_RXP1 DMI_RX1 DMI_TX1 H_DMI_TXP1 [22]
DMI
V4 W8
[22] H_DMI_RXN1 Y3 DMI_RX1* DMI_TX1* Y6 H_DMI_TXN1 [22]
[22] H_DMI_RXP2 Y4 DMI_RX2 DMI_TX2 Y7 H_DMI_TXP2 [22]
[22] H_DMI_RXN2 AA4 DMI_RX2* DMI_TX2* AA7 H_DMI_TXN2 [22]
[22] H_DMI_RXP3 AA5 DMI_RX3 DMI_TX3 AA8 H_DMI_TXP3 [22]
[22] H_DMI_RXN3 DMI_RX3* DMI_TX3* H_DMI_TXN3 [22]
P3 P8
P4 PE_RX0 PE_TX0 P7
R2 PE_RX0* PE_TX0* T7
PE_RX1 PE_TX1
GEN
R1 T8
T4 PE_RX1* PE_TX1* R6
T3 PE_RX2 PE_TX2 R5
U2 PE_RX2* PE_TX2* U5
U1 PE_RX3 PE_TX3 U6
PE_RX3* PE_TX3*
*
B B4 B
RH42 24.9 +1P05V_VCCIO
PEG_COMPI B5 +/-1%
PEG_ICOMPO C4
PEG_RCOMPO
3/10
PE115527-4041-0DF
A A
Title
CPU-2: FDI/PCIe/DMI
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
UH1A
[15,16] D3_MAA[15..0] D3_MAA0 AV27 AK3
D3_MAA1 AY24 SA_MA0 SA_DQS0 AK2 D3_DQS_A0 [15,16]
AW24 SA_MA1 SA_DQS0* D3_DQS_A#0 [15,16]
D3_MAA2
D3_MAA3 AW23 SA_MA2
D3_MAA4 AV23 SA_MA3 AJ3 D3_DQ_A0
D3_MAA5 AT24 SA_MA4 SA_DQ0 AJ4 D3_DQ_A1 D3_DQ_A[63..0] [15,16]
D3_MAA6 AT23 SA_MA5 SA_DQ1 AL3 D3_DQ_A2
D3_MAA7 AU22 SA_MA6 SA_DQ2 AL4 D3_DQ_A3
D3_MAA8 AV22 SA_MA7 SA_DQ3 AJ2 D3_DQ_A4
D3_MAA9 AT22 SA_MA8 SA_DQ4 AJ1 D3_DQ_A5
D3_MAA10 AV28 SA_MA9 SA_DQ5 AL2 D3_DQ_A6
D D3_MAA11 AU21 SA_MA10 SA_DQ6 AL1 D3_DQ_A7 D
D3_MAA12 AT21 SA_MA11 SA_DQ7
D3_MAA13 AW32 SA_MA12 AP3
D3_MAA14 AU20 SA_MA13 SA_DQS1 AP2 D3_DQS_A1 [15,16]
D3_MAA15 AT20 SA_MA14 SA_DQS1* D3_DQS_A#1 [15,16]
SA_MA15
AW29 AN1 D3_DQ_A8
[15,16] D3_WEA# AV30 SA_WE* SA_DQ8 AN4 D3_DQ_A9
[15,16] D3_CASA# AU28 SA_CAS* SA_DQ9 AR3 D3_DQ_A10
[15,16] D3_RASA# SA_RAS* SA_DQ10 AR4 D3_DQ_A11
[15,16] D3_BAA[2..0] D3_BAA0 AY29 SA_DQ11 AN2 D3_DQ_A12
D3_BAA1 AW28 SA_BS0 SA_DQ12 AN3 D3_DQ_A13
D3_BAA2 AV20 SA_BS1 SA_DQ13 AR2 D3_DQ_A14
SA_BS2 SA_DQ14 AR1 D3_DQ_A15
SA_DQ15
AU29 AW4
[15] D3_SCS_A#0 AV32 SA_CS0* SA_DQS2 AV4 D3_DQS_A2 [15,16]
[15] D3_SCS_A#1 AW30 SA_CS1* SA_DQS2* D3_DQS_A#2 [15,16]
[16] D3_SCS_A#2 AU33 SA_CS2*
[16] D3_SCS_A#3 SA_CS3* AV2 D3_DQ_A16
SA_DQ16 AW3 D3_DQ_A17
AV19 SA_DQ17 AV5 D3_DQ_A18
[15] D3_CKE_A0 AT19 SA_CKE0 SA_DQ18 AW5 D3_DQ_A19
[15] D3_CKE_A1 AU18 SA_CKE1 SA_DQ19 AU2 D3_DQ_A20
[16] D3_CKE_A2 AV18 SA_CKE2 SA_DQ20 AU3 D3_DQ_A21
[16] D3_CKE_A3 SA_CKE3 SA_DQ21 AU5 D3_DQ_A22
SA_DQ22 AY5 D3_DQ_A23
AV31 SA_DQ23
[15] D3_ODT_A0 AU32 SA_ODT0 AV8
C [15] D3_ODT_A1 AU30 SA_ODT1 SA_DQS3 AW8 D3_DQS_A3 [15,16] C
[16] D3_ODT_A2 AW33 SA_ODT2 SA_DQS3* D3_DQS_A#3 [15,16]
[16] D3_ODT_A3 SA_ODT3
AY7 D3_DQ_A24
AY25 SA_DQ24 AU7 D3_DQ_A25
[15] D3_MA_CLK0 SA_CK0 SA_DQ25
DDR_A
AW25 AV9 D3_DQ_A26
[15] D3_MA_CLK#0 AU24 SA_CK0* SA_DQ26 AU9 D3_DQ_A27
[15] D3_MA_CLK1 AU25 SA_CK1 SA_DQ27 AV7 D3_DQ_A28
[15] D3_MA_CLK#1 AW27 SA_CK1* SA_DQ28 AW7 D3_DQ_A29
[16] D3_MA_CLK2 AY27 SA_CK2 SA_DQ29 AW9 D3_DQ_A30
[16] D3_MA_CLK#2 AV26 SA_CK2* SA_DQ30 AY9 D3_DQ_A31
[16] D3_MA_CLK3 AW26 SA_CK3 SA_DQ31
[16] D3_MA_CLK#3 SA_CK3* AV37
SA_DQS4 AV36 D3_DQS_A4 [15,16]
1 2 Dummy AW18 SA_DQS4* D3_DQS_A#4 [15,16]
RH8
[15,16,17,18] D3_RESET# SM_DRAMRST*
AU35
* CH47 D3_DQ_A32
*
0.1uF RH51 120Ohm AJ19 SA_DQ32 AW37 D3_DQ_A33
Add RC [24] H_DRAMPWRGD SM_DRAMPWROK SA_DQ33
Dummy +/-5% AU39 D3_DQ_A34
filter;CRB 16V, X7R, +/-10%
SA_DQ34 AU36 D3_DQ_A35
H_SM_VREF AJ22 SA_DQ35 AW35 D3_DQ_A36
0.7-11/30/09 SM_VREF SA_DQ36 AY36 D3_DQ_A37
AV13 SA_DQ39
[15,16] D3_DQS_A8 AV12 SA_DQS8 AP38
[15,16] D3_DQS_A#8 SA_DQS8* SA_DQS5 AP39 D3_DQS_A5 [15,16] +1P5V_SM
SA_DQS5* D3_DQS_A#5 [15,16]
D3_ECC_CB_A0 AU12
B
D3_ECC_CB_A1 AU14 SA_ECC_CB0 AR40 D3_DQ_A40 B
D3_ECC_CB_A2 AW13 SA_ECC_CB1
SA_ECC_CB2
SA_DQ40
SA_DQ41
AR37 D3_DQ_A41 *RH43
100 Ohm
D3_ECC_CB_A3 AY13 AN38 D3_DQ_A42 +/-1%
D3_ECC_CB_A4 AU13 SA_ECC_CB3 SA_DQ42 AN37 D3_DQ_A43
D3_ECC_CB_A5 AU11 SA_ECC_CB4 SA_DQ43 AR39 D3_DQ_A44
D3_ECC_CB_A6 AY12 SA_ECC_CB5 SA_DQ44 AR38 D3_DQ_A45
D3_ECC_CB_A7 AW12 SA_ECC_CB6 SA_DQ45 AN39 D3_DQ_A46 [13] H_SM_VREF
SA_ECC_CB7 SA_DQ46 AN40 D3_DQ_A47
SA_DQ47
[15,16] D3_ECC_CB_A[7..0]
SA_DQS6
AK38
D3_DQS_A6 [15,16]
* CH3
0.1uF *RH44
100 Ohm
AK39 16V, X7R, +/-10% +/-1%
SA_DQS6* D3_DQS_A#6 [15,16]
RH43,RH44 is 1k in
AL40 D3_DQ_A48
SA_DQ48 AL37 D3_DQ_A49 PDG; 100 in CRB
SA_DQ49 AJ38 D3_DQ_A50
SA_DQ51 AL39 D3_DQ_A52 RH43,RH44 usage 100 Ohm follow CRB;
SA_DQ52 AL38 D3_DQ_A53
SA_DQ53 CRB 0.7-12/10/09
AJ39 D3_DQ_A54
SA_DQ55
AF38
SA_DQS7 AF39 D3_DQS_A7 [15,16]
SA_DQS7* D3_DQS_A#7 [15,16]
AG40 D3_DQ_A56
SA_DQ56 AG37 D3_DQ_A57
SA_DQ57 AE38 D3_DQ_A58
A A
SA_DQ59 AG39 D3_DQ_A60
SA_DQ60
1/10
AG38 D3_DQ_A61
SA_DQ63 Title
PE115527-4041-0DF
CPU-3: DDR3_CHA
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
UH1B
[17,18] D3_MAB[15..0] D3_MAB0 AK24 AH7
D3_MAB1 AM20 SB_MA0 SB_DQS0 AH6 D3_DQS_B0 [17,18]
D3_MAB2 AM19 SB_MA1 SB_DQS0* D3_DQS_B#0 [17,18]
D3_MAB3 AK18 SB_MA2
D3_MAB4 AP19 SB_MA3 AG7 D3_DQ_B0
D3_MAB5 AP18 SB_MA4 SB_DQ0 AG8 D3_DQ_B1 D3_DQ_B[63..0] [17,18]
D3_MAB6 AM18 SB_MA5 SB_DQ1 AJ9 D3_DQ_B2
D3_MAB7 AL18 SB_MA6 SB_DQ2 AJ8 D3_DQ_B3
D3_MAB8 AN18 SB_MA7 SB_DQ3 AG5 D3_DQ_B4
D D3_MAB9 AY17 SB_MA8 SB_DQ4 AG6 D3_DQ_B5 D
D3_MAB10 AN23 SB_MA9 SB_DQ5 AJ6 D3_DQ_B6
D3_MAB11 AU17 SB_MA10 SB_DQ6 AJ7 D3_DQ_B7
D3_MAB12 AT18 SB_MA11 SB_DQ7
D3_MAB13 AR26 SB_MA12 AM8
D3_MAB14 AY16 SB_MA13 SB_DQS1 AL8 D3_DQS_B1 [17,18]
D3_MAB15 AV16 SB_MA14 SB_DQS1* D3_DQS_B#1 [17,18]
SB_MA15
AR25 AL7 D3_DQ_B8
[17,18] D3_WEB# AK25 SB_WE* SB_DQ8 AM7 D3_DQ_B9
[17,18] D3_CASB# AP24 SB_CAS* SB_DQ9 AM10 D3_DQ_B10
[17,18] D3_RASB# SB_RAS* SB_DQ10 AL10 D3_DQ_B11
[17,18] D3_BAB[2..0] D3_BAB0 AP23 SB_DQ11 AL6 D3_DQ_B12
D3_BAB1 AM24 SB_BS0 SB_DQ12 AM6 D3_DQ_B13
D3_BAB2 AW17 SB_BS1 SB_DQ13 AL9 D3_DQ_B14
SB_BS2 SB_DQ14 AM9 D3_DQ_B15
SB_DQ15
AN25 AR8
[17] D3_SCS_B#0 AN26 SB_CS0* SB_DQS2 AP8 D3_DQS_B2 [17,18]
[17] D3_SCS_B#1 AL25 SB_CS1* SB_DQS2* D3_DQS_B#2 [17,18]
[18] D3_SCS_B#2 AT26 SB_CS2*
[18] D3_SCS_B#3 SB_CS3* AP7 D3_DQ_B16
SB_DQ16 AR7 D3_DQ_B17
AU16 SB_DQ17 AP10 D3_DQ_B18
[17] D3_CKE_B0 AY15 SB_CKE0 SB_DQ18 AR10 D3_DQ_B19
[17] D3_CKE_B1 AW15 SB_CKE1 SB_DQ19 AP6 D3_DQ_B20
[18] D3_CKE_B2 AV15 SB_CKE2 SB_DQ20 AR6 D3_DQ_B21
[18] D3_CKE_B3 SB_CKE3 SB_DQ21 AP9 D3_DQ_B22
C AL26 SB_DQ23 C
[17] D3_ODT_B0 AP26 SB_ODT0 AN13
[17] D3_ODT_B1 AM26 SB_ODT1 SB_DQS3 AN12 D3_DQS_B3 [17,18]
[18] D3_ODT_B2 AK26 SB_ODT2 SB_DQS3* D3_DQS_B#3 [17,18]
[18] D3_ODT_B3 SB_ODT3
AM12 D3_DQ_B24
AL21 SB_DQ24 AM13 D3_DQ_B25
[17] D3_MB_CLK0 AL22 SB_CK0 SB_DQ25 AR13 D3_DQ_B26
[17] D3_MB_CLK#0 AL20 SB_CK0* SB_DQ26 AP13 D3_DQ_B27
[17] D3_MB_CLK1 SB_CK1 SB_DQ27
DDR_B
AK20 AL12 D3_DQ_B28
[17] D3_MB_CLK#1 AL23 SB_CK1* SB_DQ28 AL13 D3_DQ_B29
[18] D3_MB_CLK2 AM22 SB_CK2 SB_DQ29 AR12 D3_DQ_B30
[18] D3_MB_CLK#2 AP21 SB_CK2* SB_DQ30 AP12 D3_DQ_B31
[18] D3_MB_CLK3 AN21 SB_CK3 SB_DQ31
[18] D3_MB_CLK#3 SB_CK3* AN29
SB_DQS4 AN28 D3_DQS_B4 [17,18]
SB_DQS4* D3_DQS_B#4 [17,18]
AR28 D3_DQ_B32
SB_DQ33 AL28 D3_DQ_B34
SB_DQ35 AP28 D3_DQ_B36
SB_DQ36 AP29 D3_DQ_B37
SB_DQ37 AM28 D3_DQ_B38
AN16 SB_DQ39
[17,18] D3_DQS_B8 AN15 SB_DQS8 AP33
[17,18] D3_DQS_B#8 SB_DQS8* SB_DQS5 AR33 D3_DQS_B5 [17,18]
B SB_DQS5* D3_DQS_B#5 [17,18] B
D3_ECC_CB_B0 AL16
D3_ECC_CB_B1 AM16 SB_ECC_CB0 AP32 D3_DQ_B40
D3_ECC_CB_B2 AP16 SB_ECC_CB1 SB_DQ40 AP31 D3_DQ_B41
D3_ECC_CB_B3 AR16 SB_ECC_CB2 SB_DQ41 AP35 D3_DQ_B42
D3_ECC_CB_B4 AL15 SB_ECC_CB3 SB_DQ42 AP34 D3_DQ_B43
D3_ECC_CB_B5 AM15 SB_ECC_CB4 SB_DQ43 AR32 D3_DQ_B44
D3_ECC_CB_B6 AR15 SB_ECC_CB5 SB_DQ44 AR31 D3_DQ_B45
D3_ECC_CB_B7 AP15 SB_ECC_CB6 SB_DQ45 AR35 D3_DQ_B46
SB_ECC_CB7 SB_DQ46 AR34 D3_DQ_B47
SB_DQ47
[17,18] D3_ECC_CB_B[7..0] AL33
SB_DQS6 AM33 D3_DQS_B6 [17,18]
SB_DQS6* D3_DQS_B#6 [17,18]
AM32 D3_DQ_B48
SB_DQ55
AG35
SB_DQS7 AG34 D3_DQS_B7 [17,18]
SB_DQS7* D3_DQS_B#7 [17,18]
A
AH35 D3_DQ_B56 A
SB_DQ56 AH34 D3_DQ_B57
SB_DQ57 AE34 D3_DQ_B58
SB_DQ58 AE35 D3_DQ_B59
SB_DQ59 AJ35 D3_DQ_B60
SB_DQ60 AJ34 D3_DQ_B61
SB_DQ61
2/10
AF33 D3_DQ_B62 Title

SB_DQ62 AF35 D3_DQ_B63
SB_DQ63 CPU-4: DDR3_CHB
DWG NO Rev
PE115527-4041-0DF
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+VCORE
UH1F
+1P05V_VCCIO +V_VCCSA +1P1V_AXG +1P5V_SM
A12 F31
A13 VCC_1 VCC_81 F32
A16 VCC_4 VCC_84 G15 UH1G UH1H
D A18 VCC_5 VCC_85 G16 D
A24 VCC_6 VCC_86 G18 AB33 AJ13
A25 VCC_7 VCC_87 G19 A11 H10 AB34 VAXG_1 VDDQ_1 AJ14
A27 VCC_8 VCC_88 G21 A7 VCCIO_1 VCCSA_1 H11 AB35 VAXG_2 VDDQ_2 AJ20
A28 VCC_9 VCC_89 G22 AA3 VCCIO_2 VCCSA_2 H12 AB36 VAXG_3 VDDQ_3 AJ23
B15 VCC_10 VCC_90 G24 AB8 VCCIO_3 VCCSA_3 J10 AB37 VAXG_4 VDDQ_6 AJ24
B16 VCC_11 VCC_91 G25 AF8 VCCIO_4 VCCSA_4 K10 AB38 VAXG_5 VDDQ_4 AR20
B18 VCC_12 VCC_92 G27 AG33 VCCIO_5 VCCSA_5 K11 AB39 VAXG_6 VDDQ_5 AR21
B24 VCC_13 VCC_93 G28 AJ16 VCCIO_6 VCCSA_6 L11 AB40 VAXG_7 VDDQ_7 AR22
B25 VCC_14 VCC_94 G30 AJ17 VCCIO_7 VCCSA_7 L12 AC33 VAXG_8 VDDQ_8 AR23
B27 VCC_15 VCC_95 G31 AJ26 VCCIO_8 VCCSA_8 M10 AC34 VAXG_9 VDDQ_9 AR24
B28 VCC_16 VCC_96 G32 AJ28 VCCIO_9 VCCSA_9 M11 AC35 VAXG_10 VDDQ_10 AU19
B30 VCC_17 VCC_97 G33 AJ32 VCCIO_10 VCCSA_10 M12 AC36 VAXG_11 VDDQ_11 AU23
B31 VCC_18 VCC_98 H13 AK15 VCCIO_11 VCCSA_11 AC37 VAXG_12 VDDQ_12 AU27
B33 VCC_19 VCC_99 H14 AK17 VCCIO_12 AC38 VAXG_13 VDDQ_13 AU31
B34 VCC_20 VCC_100 H15 AK19 VCCIO_13 AC39 VAXG_14 VDDQ_14 AV21
C15 VCC_21 VCC_101 H16 AK21 VCCIO_14 AC40 VAXG_15 VDDQ_15 AV24
C16 VCC_22 VCC_102 H18 AK23 VCCIO_15 T33 VAXG_16 VDDQ_16 AV25
C21 VCC_25 VCC_105 H22 AK30 VCCIO_18 T36 VAXG_19 VDDQ_19 AW31
C22 VCC_26 VCC_106 H24 B9 VCCIO_19 T37 VAXG_20 VDDQ_20 AY23
C24 VCC_27 VCC_107 H25 D10 VCCIO_20 T38 VAXG_21 VDDQ_21 AY26
CPU POWER
MCH POWER
C25 VCC_28 VCC_108 H27 D6 VCCIO_21 T39 VAXG_22 VDDQ_22 AY28
C27 VCC_29 VCC_109 H28 E3 VCCIO_22 T40 VAXG_23 VDDQ_23
C28 VCC_30 VCC_110 H30 E4 VCCIO_23 U33 VAXG_24
C30 VCC_31 VCC_111 H31 G3 VCCIO_24 U34 VAXG_25
C31 VCC_32 VCC_112 H32 G4 VCCIO_25 U35 VAXG_26
C33 VCC_33 VCC_113 J12 J3 VCCIO_26 U36 VAXG_27
C C34 VCC_34 VCC_114 J15 J4 VCCIO_27 +1P8V_SFR U37 VAXG_28 C
C36 VCC_35 VCC_115 J16 J7 VCCIO_28 U38 VAXG_29
CPU POWER
D13 VCC_36 VCC_116 J18 J8 VCCIO_29 U39 VAXG_30

D14 VCC_37 VCC_117 J19 L3 VCCIO_30 U40 VAXG_31
D15 VCC_38 VCC_118 J21 L4 VCCIO_31 AK11 W33 VAXG_32
D16 VCC_39 VCC_119 J22 L7 VCCIO_32 VCCPLL_1 AK12 W34 VAXG_33
D18 VCC_40 VCC_120 J24 M13 VCCIO_33 VCCPLL_2 W35 VAXG_34
D19 VCC_41
VCC_42
VCC_121
VCC_122
J25 N3 VCCIO_34
VCCIO_35
* CH4
1uF W36 VAXG_35
VAXG_36
D21 J27 N4 16V, X5R, +/-10% W37
D22 VCC_43 VCC_123 J28 N7 VCCIO_36 W38 VAXG_37
D24 VCC_44 VCC_124 J30 R3 VCCIO_37 Y33 VAXG_38
D25 VCC_45 VCC_125 K15 R4 VCCIO_38 Y34 VAXG_39
D27 VCC_46 VCC_126 K16 R7 VCCIO_39 Y35 VAXG_40
D28 VCC_47 VCC_127 K18 U3 VCCIO_40 Y36 VAXG_41
D33 VCC_50 VCC_130 K22 V8 VCCIO_43 VAXG_44
D34 VCC_51 VCC_131 K24 W3 VCCIO_44
D35 VCC_52 VCC_132 K25 VCCIO_45
D36 VCC_53 VCC_133 K27
E15 VCC_54 VCC_134 K28
E16 VCC_55 VCC_135 K30
E18 VCC_56 VCC_136 L13 8/10
E19 VCC_57 VCC_137 L14
VCC_58 VCC_138 PE115527-4041-0DF
E21 L15
E22 VCC_59 VCC_139 L16
E24 VCC_60 VCC_140 L18
E25 VCC_61 VCC_141 L19
E27 VCC_62 VCC_142 L21 +1P05V_VCCIO +1P5V_SM
B E28 VCC_63 VCC_143 L22 B
E30 VCC_64 VCC_144 L24
E31 VCC_65 VCC_145 L25
E33 VCC_66 VCC_146 L27
E34 VCC_67
VCC_68
VCC_147
VCC_148
L28 7/10 * CH5
4.7uF * CH6
0.1uF * CH7
0.1uF * CH8
22uF * CH9
22uF
6.3V, X5R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
E35 L30
VCC_69 VCC_149 PE115527-4041-0DF
F15 M14
F16 VCC_70 VCC_150 M15
F18 VCC_71 VCC_151 M16
F19 VCC_72 VCC_152 M18
F21 VCC_73 VCC_153 M19
F22 VCC_74 VCC_154 M21
F24 VCC_75 VCC_155 M22
F25 VCC_76 VCC_156 M24 CLOSE TO CPU CLOSE TO CPU
F27 VCC_77 VCC_157 M25
F28 VCC_78 VCC_158 M27
F30 VCC_79 VCC_159 M28
VCC_80 VCC_160 M30
VCC_161
6/10
PE115527-4041-0DF
+3V_S5 +5V_S5
CD48
A
* CD50
0.1uF
UD5 Dummy
+1P5V_SM
* 1uF
6.3V,X5R,+/-10% A
16V, X7R, +/-10% Dummy
8
Dummy
1 5 3
*
*
VDD RW + 1 RD32 2.2 RD33 0
2 Dummy Dummy H_SM_VREF [11]
*
4 6 - Title
RD30 12.1K UD6A
[16,18,24,32,38,39,58,59] S_SMBDATA_PCI SDA RH +/-1% LM358 *RD26
1K
*
CD49
1uF
CPU-5: Power
4
[16,18,24,32,38,39,58,59] S_SMBCLK_PCI
3
SCL GND
2 Dummy RD31
*
12.1K * CD47
100pF
Dummy +/-1%
Dummy
6.3V,X5R,+/-10%
Dummy
+/-1% Dummy DWG NO Rev
Dummy 50V, NPO, +/-5% A00
ISL90727WIE627Z-TK Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
UH1I UH1J
A17 AM27 AT8 F37

A23 VSS_1 VSS_91 AM3 AT9 VSS_171 VSS_257 F39
A26 VSS_2 VSS_92 AM30 AU1 VSS_172 VSS_258 F5
AA33 VSS_5 VSS_95 AM38 AU34 VSS_175 VSS_261 G11
D AA35 VSS_7 VSS_97 AM4 AU6 VSS_177 VSS_263 G17 D
AA37 VSS_9 VSS_99 AM5 AV10 VSS_179 VSS_265 G23
AA38 VSS_10 VSS_100 AN10 AV11 VSS_180 VSS_266 G26
AA6 VSS_11 VSS_101 AN11 AV14 VSS_181 VSS_267 G29
AB5 VSS_12 VSS_102 AN14 AV17 VSS_182 VSS_268 G34
AC1 VSS_13 VSS_103 AN17 AV3 VSS_183 VSS_269 G7
AC6 VSS_14 VSS_104 AN19 AV35 VSS_184 VSS_270 G8
AD33 VSS_15 VSS_105 AN22 AV38 VSS_185 VSS_271 H1
AD36 VSS_16 VSS_106 AN24 AV6 VSS_186 VSS_272 H17
AD38 VSS_17 VSS_107 AN27 AW10 VSS_187 VSS_273 H2
AE3 VSS_22 VSS_112 AN34 AW6 VSS_192 VSS_278 H33
AE33 VSS_23 VSS_113 AN35 AY11 VSS_193 VSS_279 H35
AE36 VSS_24 VSS_114 AN36 AY14 VSS_194 VSS_280 H37
AF1 VSS_25 VSS_115 AN5 AY18 VSS_195 VSS_281 H39
AF40 VSS_29 VSS_119 AN9 AY8 VSS_199 VSS_285 J11
AF5 VSS_30 VSS_120 AP1 B10 VSS_200 VSS_286 J17
AG36 VSS_33 VSS_123 AP17 B17 VSS_203 VSS_289 J26
AH2 VSS_34 VSS_124 AP22 B23 VSS_204 VSS_290 J29
AH3 VSS_35 VSS_125 AP25 B26 VSS_205 VSS_291 J32
C AH33 VSS_36 VSS_126 AP27 B29 VSS_206 VSS_292 K1 C
AH36 VSS_37 VSS_127 AP30 B32 VSS_207 VSS_293 K12
VSS_41 VSS_131 VSS_211 VSS_297
GND
AH40 AP40 C11 K2

AH5 VSS_42 VSS_132 AP5 C12 VSS_212 VSS_298 K20
AH8 VSS_43 VSS_133 AR11 C17 VSS_213 VSS_299 K23
AJ12 VSS_44 VSS_134 AR14 C20 VSS_214 VSS_300 K26
VSS_49 VSS_139 VSS_219 VSS_305
GND
AJ27 AR30 C35 K39
AK1 VSS_52 VSS_142 AT1 D17 VSS_222 VSS_308 L10
AK31 VSS_59 VSS_149 AT2 D37 VSS_229 VSS_315 M1
AK34 VSS_62 VSS_152 AT28 D5 VSS_232 VSS_318 M20 MLH1 MLH2 MLH3 MLH4
AK35 VSS_63 VSS_153 AT29 D9 VSS_233 VSS_319 M23 2D lable
VSS_64 VSS_154 VSS_234 VSS_320 MLH MLH MLH MLH
AK36 AT3 E11 M26
B AK37 VSS_65 VSS_155 AT30 E12 VSS_235 VSS_321 M29 B
AK4 VSS_66 VSS_156 AT31 E17 VSS_236 VSS_322 M33
AK40 VSS_67 VSS_157 AT32 E20 VSS_237 VSS_323 M35 UH1_1
AL11 VSS_73 VSS_163 AT38 E7 VSS_243 VSS_329 N8
AL14 VSS_74 VSS_164 AT39 E8 VSS_244 VSS_330 P1
AL17 VSS_75 VSS_165 AT4 F1 VSS_245 VSS_331 P2
AL30 VSS_79 VSS_169 AT7 F17 VSS_249 VSS_335 P5 UH1_B
AL36 VSS_80 VSS_170 F2 VSS_250 VSS_336 P6 Backplate Backplate
AL5 VSS_81 F20 VSS_251 VSS_337 R33
VSS_82 B39 update to RSVD48; VSS_252 VSS_338
AM1 F23 R35
AM11 VSS_83 PDG 0.7-12/07/09 F26 VSS_253 VSS_339 R37
AM14 VSS_84 F29 VSS_254 VSS_340 R39
AM17 VSS_85 EDS: B39 defined "VSS_NCTF" F35 VSS_255 VSS_341 R8
AM2 VSS_86 VSS_256 VSS_342 T1
VSS_87 CRB: B39 defined "RSVD" VSS_343
AM21 TPH99 T5
AM23 VSS_88 Pin_B39 follow CRB pin define; B39 VSS_344 T6
AM25 VSS_89 A4 RSVD48 VSS_345 U8
VSS_90 CRB 0.7-12/10/09 VSS_NCTF2 VSS_346
AV39 V1
AY37 VSS_NCTF3 VSS_347 V2
9/10 VSS_NCTF4 VSS_348
B3 V33
VSS_NCTF5 VSS_349 V34
A PE115527-4041-0DF A
VSS_350 V35
VSS_351 V36
VSS_352 V37
VSS_353 V38
VSS_354 V39
VSS_355 V40 Title
VSS_356 V5
VSS_357
VSS_358
W6
Y5
CPU-6: GND
VSS_359 Y8 DWG NO Rev
10/10 VSS_360
A00
PE115527-4041-0DF Gold Coast_MT/DT
5 4 3 2 1
A
B
C
D
198 79
187 FREE1 RSVD 77
*
*
*
*
49 FREE2 ODT1 195
48 FREE3 ODT0
1uF
FREE4
CD8
CD1
CD13
CD11
0.1uF
0.1uF
4.7uF
+1P5V_SM
+1P5V_SM
+1P5V_SM
+1P5V_SM_VTT
240
Dummy
+1P5V_SM_VTT
VTT
RD3
RD1
120 68
VTT NC/PAR_IN 53
NC/ERR_OUT 167
NC/TEST4
6.3V,X5R,+/-10%
239
16V, X7R, +/-10%

16V, X7R, +/-10%
* *
6.3V, X5R, +/-10%

VSS D3_ODT_A0
D3_ODT_A1
235
*
232 VSS
*
229 VSS
1K
1K
[11]
[11]
1uF
VSS
CD2
CLOSE TO DIMM POWER PIN
226
+/-1%
+/-1%
VSS
CD9
5
5
223 39 D3_ECC_CB_A0
*
PLAECE CLOSE TO CH-A DIMM
0.1uF
VSS CB<0>
SMB ADDRESS:000
220 40 D3_ECC_CB_A1
*
VSS CB<1>
CHANNEL A BANK 1
217 45 D3_ECC_CB_A2
1K
VSS CB<2>
RD2
214 46 D3_ECC_CB_A3
1K
+/-1%
VSS CB<3>
6.3V,X5R,+/-10%
RD4
211 158 D3_ECC_CB_A4
+/-1%
208 VSS CB<4> 159
16V, X7R, +/-10%

D3_ECC_CB_A5
*
*
205 VSS CB<5> 164 D3_ECC_CB_A6
*
*
1uF
VSS CB<7>
CD3
199
CD12
0.1uF
166 VSS
CD10
0.1uF
163 VSS 7 D3_DQS_A0
CD14
0.1uF
160 VSS DQS0 6 D3_DQS_A#0
157 VSS DQS0
VSS
6.3V,X5R,+/-10%
154 16
16V, X7R, +/-10%

D3_DQS_A1
151 VSS DQS1 15
16V, X7R, +/-10%

D3_DQS_A#1
*
148 VSS DQS1
16V, X7R, +/-10%

145 VSS 25 D3_DQS_A2
*
1uF
VSS DQS2
CD4
142 24 D3_DQS_A#2
Change to 0.1uF; PDG 0.7-12/07/09

139 VSS DQS2
CD51
2.2uF
130 VSS DQS3
VSS
6.3V,X5R,+/-10%
D3_ECC_CB_A[7..0]
127 85 D3_DQS_A4
121 VSS DQS4
VSS 94 D3_DQS_A5
DQS5
[11,16]
116 93 D3_DQS_A#5
6.3V, Y5V, +80%/-20%

VSS DQS5
D3_CA_VREF_A
D3_DQ_VREF_A
113
110 VSS 103 D3_DQS_A6
[16]
[16]
104 VSS DQS6
101 VSS 112 D3_DQS_A7
*
+3V
Del CD52,CD53-12/29/09
4
4
95 VSS DQS7
1uF
VSS
CD6
92 43
89 VSS DQS8 42
86 VSS DQS8
83 VSS 125
80 VSS DM0/DQS9 126
16V, X5R, +/-10%

47 VSS DQS9
*
44 VSS 134
VSS DM1/DQS10
Add CD52,CD53; follow CRB 0.7-12/28/09

41 135
1uF
VSS DQS10
CD7
38
VSS
20100104: Remove CD5 10uF

35 143
CRB 0.7-12/29/09
CRB 0.7-12/10/09
32 VSS DM2/DQS11 144
29 VSS DQS11
26 VSS 152
VSS DM3/DQS12
6.3V,X5R,+/-10%
23 153
20 VSS DQS12
; CRB 0.7-12/10/09
17 VSS 203
11 VSS DQS13
SA_BS[2]-->Pin 52 (BA2)
SA_BS[0]-->Pin 71 (BA0)
8 VSS 212
SA_BS[1]-->Pin 190 (BA1)
5 VSS DM5/DQS14 213

D3_DQS_A[7..0]
VSS DQS14
D3_DQS_A#[7..0]
2
+1P5V_SM
VSS 221
197 DM6/DQS15 222
D3_DQS_A8 [11,16]
VDDQ DQS15
D3_DQS_A#8 [11,16]
194
[11,16]
[11,16]
191 VDDQ 230

189 VDDQ DM7/DQS16 231
[11]
[11]
[11]
[11]
186 VDDQ NC/DQS16
183 VDDQ 161
VDDQ DM8/DQS17
[16,17,18,20,32,52] S_SMBDATA_MAIN
[11,16] D3_BAA[2..0]
[16,17,18,20,32,52] S_SMBCLK_MAIN
182 162
Del CD47 , CD48, CD49, CD50, CD51 and Dummy;

Add CD47 , CD48, CD49, CD50, CD51 and Dummy;
[11,16] D3_MAA[15..0]
179 VDDQ DQS17
176 VDDQ 3 D3_DQ_A0
173 VDDQ DQ0 4 D3_DQ_A1
3
3
[11] D3_CKE_A0
[11] D3_CKE_A1
VDDQ DQ1
[11] D3_SCS_A#0
[11] D3_SCS_A#1
D3_MA_CLK0
D3_MA_CLK1
170 9 D3_DQ_A2
D3_MA_CLK#0
D3_MA_CLK#1

75 VDD DQ3 122 D3_DQ_A4
72 VDD DQ4 123 D3_DQ_A5
DDRIII
69 VDD DQ5 128 D3_DQ_A6

66 VDD DQ6 129 D3_DQ_A7
65 VDD DQ7 12 D3_DQ_A8
D3_BAA0
D3_BAA1
D3_BAA2
D3_MAA9
D3_MAA8
D3_MAA7
D3_MAA6
D3_MAA5
D3_MAA4
D3_MAA3
D3_MAA2
D3_MAA1
D3_MAA0
VDD DQ9
D3_MAA15
D3_MAA14
D3_MAA13
D3_MAA12
D3_MAA11
D3_MAA10 60 18 D3_DQ_A10
57 VDD DQ10 19 D3_DQ_A11
+3V
VDD DQ11
D3_CA_VREF_A
D3_DQ_VREF_A
54 131 D3_DQ_A12
51 VDD DQ12 132 D3_DQ_A13
236 VDD DQ13 137 D3_DQ_A14
[16] D3_DQ_VREF_A
VDDSPD DQ14 138 D3_DQ_A15
DQ15
D3_CA_VREF_A
21 D3_DQ_A16
67 DQ16 22 D3_DQ_A17
1 VREFCA DQ17 27 D3_DQ_A18
118 VREFDQ DQ18 28 D3_DQ_A19
Add RD25; PDG 0.7-12/07/09

238 SCL DQ19 140 D3_DQ_A20
RD25
* 119 SDA DQ20 141 D3_DQ_A21
237 SA2 DQ21 146 D3_DQ_A22
RD27
SA1 DQ22
000
117 147 D3_DQ_A23
Dummy
0
0 SA0 DQ23 30 D3_DQ_A24
Dummy DQ24 31 D3_DQ_A25
52 DQ25 36 D3_DQ_A26
190 BA2 DQ26 37 D3_DQ_A27
71 BA1 DQ27 149 D3_DQ_A28
BA0 DQ28 150 D3_DQ_A29
DQ29 155 D3_DQ_A30
169 DQ30 156 D3_DQ_A31
50 CKE1 DQ31 81 D3_DQ_A32
CKE0 DQ32 82 D3_DQ_A33
DQ33
2
2
76 87 D3_DQ_A34
193 S1 DQ34 88 D3_DQ_A35
D3_DQ_VREF_B
S0 DQ35
D3_DQ_VREF_B_CA
200 D3_DQ_A36
DQ36 201 D3_DQ_A37
64 DQ37 206 D3_DQ_A38
CK1/NU DQ38
[17,18]
63 207 D3_DQ_A39
CK1/NU DQ39
[17,18]
185 90 D3_DQ_A40
184 CK0* DQ40 91 D3_DQ_A41
CK0 DQ41 96 D3_DQ_A42
188 DQ42 97 D3_DQ_A43
181 A0 DQ43 209 D3_DQ_A44
61 A1 DQ44 210 D3_DQ_A45
180 A2 DQ45 215 D3_DQ_A46
59 A3 DQ46 216 D3_DQ_A47
58 A4 DQ47 99 D3_DQ_A48
Date:
178 A5 DQ48 100 D3_DQ_A49

Title
56 A6 DQ49 105 D3_DQ_A50

177 A7 DQ50 106 D3_DQ_A51
DWG NO
175 A8 DQ51 218 D3_DQ_A52

70 A9 DQ52 219 D3_DQ_A53
55 A10/AP DQ53 224 D3_DQ_A54
174 A11 DQ54 225 D3_DQ_A55
196 A12 DQ55 108 D3_DQ_A56
172 A13 DQ56 109 D3_DQ_A57
171 A14 DQ57 114 D3_DQ_A58
A15 DQ58 115 D3_DQ_A59
168 DQ59 227 D3_DQ_A60
74 RESET DQ60 228 D3_DQ_A61
CAS DQ61
Friday, December 24, 2010
192 233 D3_DQ_A62

73 RAS DQ62 234 D3_DQ_A63
WE DQ63
1
1
DDRIII
DIMM3
Sheet
15
Gold Coast_MT/DT
D3_DQ_A[63..0]
of
D3_WEA# [11,16]
D3_CASA# [11,16]
D3_RASA# [11,16]
Rev
70
D3_RESET# [11,16,17,18]
[11,16]
DDR3 Conn: CHA_1 (DIMM3)

A00
A
B
C
D
A
B
C
D
198 79
187 FREE1 RSVD 77
*
*
49 FREE2 ODT1 195
48 FREE3 ODT0
1uF
FREE4
CD19
CD15
4.7uF
+1P5V_SM
+1P5V_SM_VTT
240
+1P5V_SM_VTT
120 VTT 68
VTT NC/PAR_IN 53
NC/ERR_OUT 167
[13,18,24,32,38,39,58,59]
NC/TEST4
6.3V,X5R,+/-10%
239
[13,18,24,32,38,39,58,59]
6.3V, X5R, +/-10%
VSS
D3_ODT_A2
D3_ODT_A3
235
*
232 VSS
*
VSS
5
5
229
[11]
[11]
*
1uF
VSS
SMB ADDRESS:001

226
CD16
VSS
CHANNEL A BANK 2
223 39 D3_ECC_CB_A0
CD20
0.1uF
CD21
0.1uF
217 VSS CB<1> 45
Dummy
D3_ECC_CB_A2
S_SMBDATA_PCI
S_SMBCLK_PCI
VSS CB<3>
6.3V,X5R,+/-10%
211 158 D3_ECC_CB_A4
208 VSS CB<4> 159
16V, X7R, +/-10%

D3_ECC_CB_A5
*
205 VSS CB<5> 164
16V, X7R, +/-10%

D3_ECC_CB_A6
1uF
199 VSS CB<7>
CD17
+3V_S5
166 VSS
163 VSS 7 D3_DQS_A0
3
4
1
157 VSS DQS0
VSS
6.3V,X5R,+/-10%
154 16 D3_DQS_A1
SCL
SDA
VDD
*
148 VSS DQS1
1uF
UD1 Dummy
CD18
139 VSS DQS2
RW
GND
RH
ISL90728WIE627Z-TK
130 VSS DQS3
6
5
2
VSS
6.3V,X5R,+/-10%
D3_ECC_CB_A[7..0]
127 85 D3_DQS_A4
121 VSS DQS4
VSS 94 D3_DQS_A5
DQS5
[11,15]
116 93 D3_DQS_A#5
113 VSS DQS5
+1P5V_SM
110 VSS 103 D3_DQS_A6
CD22
Dummy for cost down-11/23/09

104 VSS DQS6
4
4
* 101 VSS 112 D3_DQS_A7

95 VSS DQS7
Dummy
92 VSS 43
89 VSS DQS8 42
12.1K
+/-1%
86 VSS DQS8
83 VSS 125
80 VSS DM0/DQS9 126
*
47 VSS DQS9
44 VSS 134
CD23
12.1K
+/-1%
Dummy
38 VSS DQS10
*
35 VSS 143
29 VSS DQS11
RD12
SA_BS[0]-->Pin
100pF
26 VSS 152
Dummy
20 VSS DQS12
; CRB 0.7-12/10/09
17 VSS 203
2
3
VSS DM4/DQS13
50V, NPO, +/-5%

14 204
VSS DQS13
-
+
4 8 11
SA_BS[2]-->Pin 52 (BA2)
71 (BA0)
8 VSS 212
SA_BS[1]-->Pin 190 (BA1)
+5V_S5
5 VSS DM5/DQS14 213
D3_DQS_A[7..0]
VSS DQS14
D3_DQS_A#[7..0]
2
+1P5V_SM
VSS 221
1
*
UD2A
LM358
197 DM6/DQS15 222
Dummy
D3_DQS_A8 [11,15]
[11]
[11]
[11]
[11]
VDDQ DQS15
D3_DQS_A#8 [11,15]
194
[11,15]
1uF
[11,15]
VDDQ
RD5
191 230
Dummy
186 VDDQ NC/DQS16
183 VDDQ 161
1K
[11] D3_CKE_A2
[11] D3_CKE_A3
[11,15] D3_MAA[15..0]
[15] D3_DQ_VREF_A
[15] D3_CA_VREF_A
VDDQ DQS17
6.3V,X5R,+/-10%
RD7
[15,17,18,20,32,52] S_SMBDATA_MAIN
[11,15] D3_BAA[2..0]
[15,17,18,20,32,52] S_SMBCLK_MAIN
[11] D3_SCS_A#2
[11] D3_SCS_A#3
D3_MA_CLK2
D3_MA_CLK3
179
3
3
*RD10
+/-1%
D3_MA_CLK#2
D3_MA_CLK#3
176 VDDQ 3 D3_DQ_A0
Dummy
* 170 VDDQ DQ1 9 D3_DQ_A2
75 VDD DQ3 122
Dummy
D3_DQ_A4
72 VDD DQ4 123 D3_DQ_A5
2.2
DDRIII
69 VDD DQ5 128 D3_DQ_A6

66 VDD DQ6 129 D3_DQ_A7
*
D3_BAA0
D3_BAA1
D3_BAA2
D3_MAA9
D3_MAA8
D3_MAA7
D3_MAA6
D3_MAA5
D3_MAA4
D3_MAA3
D3_MAA2
D3_MAA1
D3_MAA0
1uF
VDD DQ9
D3_MAA15
D3_MAA14
D3_MAA13
D3_MAA12
D3_MAA11
D3_MAA10
60 18 D3_DQ_A10
CD24
VDD DQ10
RD8
57 19 D3_DQ_A11
Dummy
+3V
54 VDD DQ11 131 D3_DQ_A12

51 VDD DQ12 132 D3_DQ_A13
* 236 VDD DQ13 137 D3_DQ_A14
6.3V,X5R,+/-10%
VDDSPD DQ14 138 D3_DQ_A15
Dummy
DQ15 21 D3_DQ_A16
0
67 DQ16 22 D3_DQ_A17
VREFCA DQ17
RD6
1 27 D3_DQ_A18
118 VREFDQ DQ18 28 D3_DQ_A19
238 SCL DQ19 140 D3_DQ_A20
*
* 119 SDA DQ20 141 D3_DQ_A21
237 SA2 DQ21 146 D3_DQ_A22
117 SA1 DQ22 147
16V, X7R, +/-10%

D3_DQ_A23
001
CD52
0.1uF
0
SA0 DQ23 30
Dummy
D3_DQ_A24
DQ24 31 D3_DQ_A25
* 52
BA2
DQ25
DQ26
36 D3_DQ_A26
190 37 D3_DQ_A27
71 BA1 DQ27 149 D3_DQ_A28
CD53
0.1uF
BA0 DQ28 150

Dummy
D3_DQ_A29
DQ29 155 D3_DQ_A30
169 DQ30 156 D3_DQ_A31
CKE1 DQ31
2
2
50 81 D3_DQ_A32
CKE0 DQ32 82
16V, X7R, +/-10%
D3_DQ_A33
76 DQ33 87 D3_DQ_A34
193 S1 DQ34 88 D3_DQ_A35
D3_DQ_VREF_A
S0 DQ35 200 D3_DQ_A36

DQ36 201 D3_DQ_A37
DQ37
[15]
64 206 D3_DQ_A38
H_CPU_DIMM_VREF_A
CK1/NU DQ38
63 207 D3_DQ_A39
185 CK1/NU DQ39 90 D3_DQ_A40
[9]
184 CK0* DQ40 91 D3_DQ_A41

CK0 DQ41 96 D3_DQ_A42
188 DQ42 97 D3_DQ_A43
181 A0 DQ43 209 D3_DQ_A44
61 A1 DQ44 210 D3_DQ_A45
180 A2 DQ45 215 D3_DQ_A46
Date:
59 A3 DQ46 216 D3_DQ_A47

Title
58 A4 DQ47 99 D3_DQ_A48
178 A5 DQ48 100 D3_DQ_A49
DWG NO
56 A6 DQ49 105 D3_DQ_A50

177 A7 DQ50 106 D3_DQ_A51
175 A8 DQ51 218 D3_DQ_A52
70 A9 DQ52 219 D3_DQ_A53
55 A10/AP DQ53 224 D3_DQ_A54
174 A11 DQ54 225 D3_DQ_A55
196 A12 DQ55 108 D3_DQ_A56
172 A13 DQ56 109 D3_DQ_A57
171 A14 DQ57 114 D3_DQ_A58
A15 DQ58 115 D3_DQ_A59
DQ59
168 227 D3_DQ_A60

74 RESET DQ60 228 D3_DQ_A61
192 CAS DQ61 233 D3_DQ_A62
73 RAS DQ62 234 D3_DQ_A63
WE DQ63
1
1
Sheet
DDRIII
DIMM1
16
Gold Coast_MT/DT
of
Rev
D3_DQ_A[63..0]
D3_WEA# [11,15]
D3_CASA# [11,15]
D3_RASA# [11,15]
70
DDR3 Conn: CHA_2 (DIMM1)
D3_RESET# [11,15,17,18]
A00
[11,15]
A
B
C
D
A
B
C
D
198 79
187 FREE1 RSVD 77
*
*
*
*
49 FREE2 ODT1 195
48 FREE3 ODT0
1uF
FREE4
CD33
CD31
CD29
CD25
0.1uF
0.1uF
4.7uF
+1P5V_SM
+1P5V_SM
+1P5V_SM
+1P5V_SM_VTT
240
Dummy
+1P5V_SM_VTT
120 VTT 68
RD15
RD13
VTT NC/PAR_IN 53
NC/ERR_OUT 167
NC/TEST4
6.3V,X5R,+/-10%
239
16V, X7R, +/-10%

16V, X7R, +/-10%
* *
6.3V, X5R, +/-10%

VSS
D3_ODT_B0
D3_ODT_B1
235
*
232 VSS
*
229 VSS
1K
1K
[12]
[12]
1uF
VSS
5
5

226
CD26
+/-1%
+/-1%
VSS
SMB ADDRESS:010
223 39 D3_ECC_CB_B0
CD30
0.1uF
VSS CB<0>
CHANNEL B BANK 1
220 40 D3_ECC_CB_B1
*
*
PLAECE CLOSE TO CH-B DIMM
217 VSS CB<1> 45 D3_ECC_CB_B2
1K
1K
VSS CB<3>
6.3V,X5R,+/-10%
211 158 D3_ECC_CB_B4
RD16
RD14
+/-1%
+/-1%
208 VSS CB<4> 159
16V, X7R, +/-10%

D3_ECC_CB_B5
*
*
*
1uF
199 VSS CB<7>
CD27
166 VSS
163 VSS 7 D3_DQS_B0
CD34
CD32
0.1uF
0.1uF
160 VSS DQS0 6 D3_DQS_B#0
157 VSS DQS0
VSS
6.3V,X5R,+/-10%
154 16 D3_DQS_B1
*
148 VSS DQS1
16V, X7R, +/-10%

16V, X7R, +/-10%
145 VSS 25 D3_DQS_B2
*
1uF
CD28
139 VSS DQS2
CD56
2.2uF
Change to 0.1uF; PDG 0.7-12/07/09
130 VSS DQS3
VSS
6.3V,X5R,+/-10%
D3_ECC_CB_B[7..0]
127 85 D3_DQS_B4
121 VSS DQS4
VSS 94 D3_DQS_B5
DQS5
[12,18]
116 93 D3_DQS_B#5
6.3V, Y5V, +80%/-20%

VSS DQS5
D3_CA_VREF_B
113
VSS
D3_DQ_VREF_B
110 103 D3_DQS_B6
[18]
104 VSS DQS6
101 VSS 112 D3_DQS_B7
4
4
[15,18]
95 VSS DQS7
Del CD54,CD5512/29/09
92 VSS 43
89 VSS DQS8 42
86 VSS DQS8
83 VSS 125
80 VSS DM0/DQS9 126
47 VSS DQS9
44 VSS 134
VSS DQS10

38
35 VSS 143
29 VSS DQS11
26 VSS 152
20 VSS DQS12
17 VSS 203
; CRB 0.7-12/10/09

11 VSS DQS13
8 VSS 212
SB_BS[2]-->Pin 52 (BA2)
SB_BS[0]-->Pin 71 (BA0)
5 VSS DM5/DQS14 213

SB_BS[1]-->Pin 190 (BA1)
D3_DQS_B[7..0]
VSS DQS14
D3_DQS_B#[7..0]
2
+1P5V_SM
VSS 221
197 DM6/DQS15 222
D3_DQS_B8 [12,18]
VDDQ DQS15
D3_DQS_B#8 [12,18]
194
[12,18]
[12,18]
191 VDDQ 230

186 VDDQ NC/DQS16
183 VDDQ 161
[12] D3_CKE_B0
[12] D3_CKE_B1
[12,18] D3_MAB[15..0]
VDDQ DQS17
[15,16,18,20,32,52] S_SMBDATA_MAIN
[15,16,18,20,32,52] S_SMBCLK_MAIN
[12,18] D3_BAB[2..0]
[12] D3_SCS_B#0
[12] D3_SCS_B#1
[12] D3_MB_CLK0
[12] D3_MB_CLK1
179
[12] D3_MB_CLK#0
[12] D3_MB_CLK#1
VDDQ
D3_CA_VREF_B
176 3 D3_DQ_B0
3
3
173 VDDQ DQ0 4 D3_DQ_B1

[15,18] D3_DQ_VREF_B

75 VDD DQ3 122 D3_DQ_B4
* 72 VDD DQ4 123 D3_DQ_B5
DDRIII
69 VDD DQ5 128 D3_DQ_B6
RD28
66 VDD DQ6 129
Dummy
D3_DQ_B7
0
65 VDD DQ7 12 D3_DQ_B8
D3_BAB0
D3_BAB1
D3_BAB2
D3_MAB9
D3_MAB8
D3_MAB7
D3_MAB6
D3_MAB5
D3_MAB4
D3_MAB3
D3_MAB2
D3_MAB1
D3_MAB0
VDD DQ9
D3_MAB15
D3_MAB14
D3_MAB13
D3_MAB12
D3_MAB11
D3_MAB10
60 18 D3_DQ_B10
57 VDD DQ10 19 D3_DQ_B11
+3V
VDD DQ11
D3_CA_VREF_B
D3_DQ_VREF_B
54 131 D3_DQ_B12
51 VDD DQ12 132 D3_DQ_B13
236 VDD DQ13 137 D3_DQ_B14
VDDSPD DQ14 138 D3_DQ_B15
DQ15 21 D3_DQ_B16
67 DQ16 22 D3_DQ_B17
1 VREFCA DQ17 27 D3_DQ_B18
118 VREFDQ DQ18 28 D3_DQ_B19
238 SCL DQ19 140 D3_DQ_B20
119 SDA DQ20 141 D3_DQ_B21
D3_DQ_VREF_B_CA
237 SA2 DQ21 146 D3_DQ_B22
117 SA1 DQ22 147 D3_DQ_B23
010
SA0 DQ23 30 D3_DQ_B24

DQ24 31 D3_DQ_B25
[15,18]
52 DQ25 36 D3_DQ_B26
190 BA2 DQ26 37 D3_DQ_B27
71 BA1 DQ27 149 D3_DQ_B28
BA0 DQ28 150 D3_DQ_B29
DQ29 155 D3_DQ_B30
169 DQ30 156 D3_DQ_B31
50 CKE1 DQ31 81 D3_DQ_B32
CKE0 DQ32
2
2
82 D3_DQ_B33
76 DQ33 87 D3_DQ_B34
193 S1 DQ34 88 D3_DQ_B35
S0 DQ35 200 D3_DQ_B36
DQ36 201 D3_DQ_B37
64 DQ37 206 D3_DQ_B38
63 CK1/NU DQ38 207 D3_DQ_B39
185 CK1/NU DQ39 90 D3_DQ_B40
184 CK0* DQ40 91 D3_DQ_B41
CK0 DQ41 96 D3_DQ_B42
188 DQ42 97 D3_DQ_B43
181 A0 DQ43 209 D3_DQ_B44
61 A1 DQ44 210 D3_DQ_B45
180 A2 DQ45 215 D3_DQ_B46
59 A3 DQ46 216 D3_DQ_B47
Date:
58 A4 DQ47 99 D3_DQ_B48
Title
178 A5 DQ48 100 D3_DQ_B49

56 A6 DQ49 105 D3_DQ_B50
DWG NO
177 A7 DQ50 106 D3_DQ_B51

175 A8 DQ51 218 D3_DQ_B52
70 A9 DQ52 219 D3_DQ_B53
55 A10/AP DQ53 224 D3_DQ_B54
174 A11 DQ54 225 D3_DQ_B55
196 A12 DQ55 108 D3_DQ_B56
172 A13 DQ56 109 D3_DQ_B57
171 A14 DQ57 114 D3_DQ_B58
A15 DQ58 115 D3_DQ_B59
168 DQ59 227 D3_DQ_B60
RESET DQ60
74 228 D3_DQ_B61
192 CAS DQ61 233 D3_DQ_B62
73 RAS DQ62 234 D3_DQ_B63
WE DQ63
1
1
DDRIII
DIMM4
Sheet
17
Gold Coast_MT/DT
of
D3_DQ_B[63..0]
D3_WEB# [12,18]
D3_CASB# [12,18]
D3_RASB# [12,18]
Rev
70
D3_RESET# [11,15,16,18]
[12,18]
DDR3 Conn: CHB_1 (DIMM4)

A00
A
B
C
D
A
B
C
D
198 79
187 FREE1 RSVD 77
*
*
49 FREE2 ODT1 195
48 FREE3 ODT0
1uF
FREE4
CD41
CD35
4.7uF
+1P5V_SM
+1P5V_SM_VTT
240
+1P5V_SM_VTT
120 VTT 68
VTT NC/PAR_IN 53
NC/ERR_OUT 167
NC/TEST4
6.3V,X5R,+/-10%
239
6.3V, X5R, +/-10%

VSS
D3_ODT_B2
D3_ODT_B3
235
*
232 VSS
*
229 VSS
[12]
[12]
1uF
226 VSS
CD36
[13,16,24,32,38,39,58,59]
VSS
5
5
223 39 D3_ECC_CB_B0
CD42
[13,16,24,32,38,39,58,59]
0.1uF
VSS CB<0>
SMB ADDRESS:011
220 40 D3_ECC_CB_B1
VSS CB<1>
CHANNEL B BANK 2

217 45 D3_ECC_CB_B2
VSS CB<3>
6.3V,X5R,+/-10%
211 158 D3_ECC_CB_B4
208 VSS CB<4> 159
16V, X7R, +/-10%

D3_ECC_CB_B5
*
*
1uF
199 VSS CB<7>
S_SMBDATA_PCI
CD43
CD37
S_SMBCLK_PCI
0.1uF
166 VSS
Dummy
163 VSS 7 D3_DQS_B0
157 VSS DQS0
VSS
6.3V,X5R,+/-10%
154 16
16V, X7R, +/-10%

D3_DQS_B1
*
148 VSS DQS1
+3V_S5
1uF
CD38
3
4
1
139 VSS DQS2
SCL
SDA
VDD
130 VSS DQS3
VSS
6.3V,X5R,+/-10%
D3_ECC_CB_B[7..0]
127 85 D3_DQS_B4
121 VSS DQS4
UD3 Dummy
VSS 94 D3_DQS_B5
DQS5
[12,17]
116 93 D3_DQS_B#5
RW
GND
RH
113 VSS DQS5
ISL90727WIE627Z-TK
110 VSS 103 D3_DQS_B6
2
6
5
104 VSS DQS6
101 VSS 112 D3_DQS_B7
4
4
95 VSS DQS7
92 VSS 43
+1P5V_SM
89 VSS DQS8 42
RD21
86 VSS DQS8
[15,16,17,20,32,52]
[15,16,17,20,32,52]
83 VSS 125
* 80 VSS DM0/DQS9 126
47 VSS DQS9
DIMMs
44 VSS 134
Dummy
D3_DQ_VREF_B_R
38 VSS DQS10
12.1K
+/-1%
VSS
Dummy for cost down-11/23/09

35 143
* 32 VSS DM2/DQS11 144
29 VSS DQS11
; CRB 0.7-12/10/09
S_SMBCLK_MAIN
RD29
*
VSS
S_SMBDATA_MAIN
26 152
Dummy
0
Decouple Cap for all 4
RD23
12.1K
+/-1%
20 VSS DQS12
Dummy
SB_BS[2]-->Pin 52 (BA2)
SB_BS[0]-->Pin 71 (BA0)
17 VSS 203
SB_BS[1]-->Pin 190 (BA1)
*
50V, NPO, +/-5% 14 VSS DM4/DQS13 204
11 VSS DQS13
8 VSS 212
CD45
100pF
5 VSS DM5/DQS14 213
Dummy
D3_DQS_B[7..0]
22pF
VSS DQS14
D3_DQS_B#[7..0]
2
Dummy
+1P5V_SM
VSS 221
197 DM6/DQS15 222
6
5
D3_DQS_B8 [12,17]
VDDQ DQS15
50V, NPO, +/-5%

D3_DQS_B#8 [12,17]
194
[12,17]
22pF
* CD39 * CD40
[12,17]
VDDQ
-
+
4 8 191 230
Dummy
VDDQ DM7/DQS16
D3_DQ_VREF_B_CA
189 231
+5V_S5
50V, NPO, +/-5% 186 VDDQ NC/DQS16
183 VDDQ 161
7
*
UD2B
[12,17] D3_MAB[15..0]
LM358
VDDQ DQS17
[15,17]
179
Dummy
176 VDDQ 3 D3_DQ_B0
1uF
3
3
CD44
170 VDDQ DQ1 9
Dummy
D3_DQ_B2
[12]
[12]
[12]
[12]

75 VDD DQ3 122 D3_DQ_B4
72 VDD DQ4 123 D3_DQ_B5
1K
DDRIII
VDD DQ5
6.3V,X5R,+/-10%
69 128 D3_DQ_B6
*RD22
+/-1%
66 VDD DQ6 129
Dummy
* D3_DQ_B7
[17] D3_CA_VREF_B
[15,17] D3_DQ_VREF_B
[12] D3_CKE_B2
[12] D3_CKE_B3
VDD DQ8
[12,17] D3_BAB[2..0]
[12] D3_SCS_B#2
[12] D3_SCS_B#3
62 13
D3_MB_CLK2
D3_MB_CLK3
D3_DQ_B9
D3_MAB9
D3_MAB8
D3_MAB7
D3_MAB6
D3_MAB5
D3_MAB4
D3_MAB3
D3_MAB2
D3_MAB1
D3_MAB0
D3_MB_CLK#2
D3_MB_CLK#3
VDD DQ9
D3_MAB15
D3_MAB14
D3_MAB13
D3_MAB12
D3_MAB11
D3_MAB10
60 18 D3_DQ_B10
RD18
57 VDD DQ10 19 D3_DQ_B11
Dummy
+3V
54 VDD DQ11 131 D3_DQ_B12

51 VDD DQ12 132 D3_DQ_B13
236 VDD DQ13 137 D3_DQ_B14
*
VDDSPD DQ14 138 D3_DQ_B15
DQ15 21 D3_DQ_B16
1uF
67 DQ16 22 D3_DQ_B17
CD46
VREFCA DQ17
Dummy
2.2 D3_DQ_VREF_B_R
1 27 D3_DQ_B18
118 VREFDQ DQ18 28 D3_DQ_B19
D3_BAB0
D3_BAB1
D3_BAB2
238 SCL DQ19 140 D3_DQ_B20

* 119 SDA DQ20 141 D3_DQ_B21
6.3V,X5R,+/-10%
237 SA2 DQ21 146 D3_DQ_B22
SA1 DQ22
011
117 147 D3_DQ_B23
0
SA0 DQ23 30
Dummy
D3_DQ_B24
RD19
DQ24 31 D3_DQ_B25
RD17
52 DQ25 36 D3_DQ_B26
*
190 BA2 DQ26 37 D3_DQ_B27
* 71 BA1 DQ27 149 D3_DQ_B28
BA0 DQ28 150
16V, X7R, +/-10%

D3_DQ_B29
CD55
0.1uF
Dummy DQ29 155 D3_DQ_B30
0
169 DQ30 156 D3_DQ_B31

*
50 CKE1 DQ31 81 D3_DQ_B32
CKE0 DQ32 82 D3_DQ_B33
DQ33
2
2
76 87 D3_DQ_B34
CD54
0.1uF
193 S1 DQ34 88
Dummy
D3_DQ_B35
S0 DQ35 200 D3_DQ_B36
DQ36 201 D3_DQ_B37
64 DQ37 206 D3_DQ_B38
63 CK1/NU DQ38 207
16V, X7R, +/-10%
D3_DQ_B39
185 CK1/NU DQ39 90 D3_DQ_B40
D3_DQ_VREF_B
184 CK0* DQ40 91 D3_DQ_B41

CK0 DQ41 96 D3_DQ_B42
DQ42
188 97 D3_DQ_B43
H_CPU_DIMM_VREF_B
181 A0 DQ43 209 D3_DQ_B44

[15,17]
61 A1 DQ44 210 D3_DQ_B45

[9]
180 A2 DQ45 215 D3_DQ_B46

59 A3 DQ46 216 D3_DQ_B47
58 A4 DQ47 99 D3_DQ_B48
Date:
178 A5 DQ48 100 D3_DQ_B49

Title
56 A6 DQ49 105 D3_DQ_B50

177 A7 DQ50 106 D3_DQ_B51
DWG NO
175 A8 DQ51 218 D3_DQ_B52

70 A9 DQ52 219 D3_DQ_B53
55 A10/AP DQ53 224 D3_DQ_B54
174 A11 DQ54 225 D3_DQ_B55
196 A12 DQ55 108 D3_DQ_B56
172 A13 DQ56 109 D3_DQ_B57
171 A14 DQ57 114 D3_DQ_B58
A15 DQ58 115 D3_DQ_B59
168 DQ59 227 D3_DQ_B60
74 RESET DQ60 228 D3_DQ_B61
CAS DQ61
192 233 D3_DQ_B62

73 RAS DQ62 234 D3_DQ_B63
WE DQ63
1
1
DDRIII
DIMM2
Sheet
18
Gold Coast_MT/DT
D3_DQ_B[63..0]
of
D3_WEB# [12,17]
D3_CASB# [12,17]
D3_RASB# [12,17]
Rev
70
D3_RESET# [11,15,16,17]
[12,17]
DDR3 Conn: CHB_2 (DIMM2)

A00
A
B
C
D
5 4 3 2 1
- PCI2/TME (Pin4) Trust Mode Enable.

+3V_CLK - PCI4/SRC5_EN (Pin6) Output Mode select. H= overclocking disabled. Latch @
H=SRC5, L=CPU/PCI Stop#. Latch @ Power-On Power-On
RC32 +3V +3V_CLK - PCIF5/ITP_EN (Pin7) Output Mode Select. - PCI3/CFGP (Pin5) Clock Config Strapping.
15 FBC1 FB 100 Ohm
+/-1% H=CPU_ITP, L= SRC8. Latch @ Power-On Details refer to CLK-Gen CFG table
Dummy * Dummy Latch @ Power-On
* CC2
* CC3
* CC5
* CC6
* CC7
* CC8
C
QC1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF +3V +3V
*
CLOSE TO PIN2
CLOSE TO PIN9
CLOSE TO PIN16
CLOSE TO PIN31
CLOSE TO PIN47
CLOSE TO PIN53
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

C_V_OUT RC36 33 B MMBT3904-7-F +3V_CLK_IO
D Dummy * CC4
10uF D
Dummy
* CC26 10V, X5R, +/-10% 20100112: Dummy
E
100pF FBC2 FB 100 Ohm Dummy
* *RC1 *RC2 RC4; IDT *RC3 *RC4
50V, NPO, +/-5%
Dummy Dummy
* CC27
10uF +3V_CLK +3V_CLK
10K
Dummy
10K
Dummy
suggestion 10K
Dummy
10K
Dummy
10V, Y5V, +80%/-20% C_CK505_33M_PCI5 C_CK505_33M_PCI2
Dummy C_CK505_33M_PCI4 C_CK505_33M_PCI3
1
* ECC1
120uF
* CC1
0.1uF
Dummy Dummy Dummy Dummy Dummy Dummy
16V, +/-20% 16V, X7R, +/-10% *RC5 *RC6 *RC7 *RC8
2
Dummy Dummy 10K 10K 10K 10K
Dummy Dummy Dummy Dummy
Intel requirement stuff CR8
+3V_CLK_IO Dummy CK505 circuit for Cost down

Add CK505 buffer thru mode circuit-20091225
+3V_CLK_IO
+3V_CLK UC1
46
16 CPUT0 45 TPC13
C 9 VDD_PLL3 CPUC0 TPC14 C
* CC18
10uF * CC19
10uF * CC23
10uF * CC24
0.1uF * CC20
0.1uF * CC21
0.1uF * CC22
0.1uF * CC25
0.1uF 2 VDD_48MHZ
VDD_PCI CPUT1
43
TPC9
Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy 53 42
VDD_REF CPUC1 TPC10
CLOSE TO PIN12
CLOSE TO PIN20
CLOSE TO PIN26
CLOSE TO PIN37
CLOSE TO PIN41
10V, X5R, +/-10%
10V, X5R, +/-10%
10V, X5R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

31 Dummy
**
47 VDD_SRC 39 C_CK505_ITP_R RC17 33
+3V_CLK_IO VDD_CPU SRCT8/CPU_ITPT 38 C_CK505_ITP#_R RC20 33
C_CK505_ITP [52]
12 SRCC8/CPU_ITPC Dummy C_CK505_ITP# [52]
20 VDD_IO
VDD_PLL3_IO Buffer thru mode
26 Dummy
**
37 VDD_SRC_IO_1 13 C_96M_PCH_R RC23 33
VDD_SRC_IO_2 DOT96T/SRCT0 14 C_96M_PCH#_R RC24 33 C_96M_PCH [22,27]
DOT96C/SRCC0 Dummy C_96M_PCH# [22,27]
41 17
IDTCV184-2APAG8
VDD_CPU_IO SRCT1/SE1 18 TPC1
Dummy
SRCC1/SE2
*
TPC2
+3V_S5 RC94 10K Dummy Buffer thru mode
**
C_V_OUT 40 21 C_SATA_PCH_R RC37 33
IO_VOUT SATAT/SRCT2 22 C_SATA_PCH#_R RC40 33 C_SATA_PCH [23,27]
20100107: Swap net SATAC/SRCC2 C_SATA_PCH# [23,27]
Dummy
name same as IC pin 24
3
SRCT3/CR#_C 25 TPC5
out. C_XTAL_14M_IN 52 SRCC3/CR#_D TPC6
QH2
XTAL_IN
MMDT5551
+3V Dummy 27
SRCT4 28 TPC3
Dummy 20100107: Swap pin 21/22 and pin27/28 pin out; PDG 0.8
XC1 XTAL-14.318MHz SRCC4 TPC4
4
1 2 C_XTAL_14M_OUT 51
*RH3 XTAL_OUT
50V, NPO, +/-5%
50V, NPO, +/-5%
7.5K P_VR_READY_R
+/-1% CC29 30 C_CK505_SRC5_DP
PCI_STOP#/SRCT5 29 C_CK505_SRC5_DN
Dummy
* CC28
* 27pF 20100107: Remove Test Point
*
B
RH36 7.5K 27pF Dummy
CPU_STOP#/SRCC5 B
P_VR_READY_R 48 33
*RH46
3KOhm
* CC38
+/-1%
Dummy
Dummy
C_CK_BSEL1 49 CKPWRGD/PD#
FSB/TEST_MODE
SRCT6
SRCC6
32 TPC15
TPC16
+/-1% 1uF Dummy
**
Dummy 16V, X5R, +/-10% 56 36 C_DMI_PCH_R RC55 33
[15,16,17,18,32,52] S_SMBCLK_MAIN 55 SCL SRCT7/CR#_F 35 C_DMI_PCH#_R RC58 33 C_DMI_PCH [22,27]
Dummy
[15,16,17,18,32,52] S_SMBDATA_MAIN SDA SRCC7/CR#_E C_DMI_PCH# [22,27]
Dummy
50V, NPO, +/-5%
Dummy * CC34 * CC35 6 C_CK505_33M_PCI4

Buffer thru mode
*
RC92 10K 22pF 22pF PCI4/SRC5_EN 5 C_CK505_33M_PCI3

P_VR_READY_R S_SLP_S3# [24,32,64,66,69,70] Dummy Dummy PCI3/CFGP 4 C_CK505_33M_PCI2
PCI2/TME 3 C_CK505_33M_PCI1
PCI1/CR#_B TPC11
50V, NPO, +/-5% 15 1 C_CK505_33M_PCI0
19 VSS_IO PCI0/CR#_A TPC12
3
11 VSS_PLL3
QH1 44 VSS_48MHZ 7 C_CK505_33M_PCI5
8 VSS_CPU PCIF5/ITP_EN 10 C_CK_BSEL0
MMDT5551
*
Dummy 50 VSS_PCI USB_48/FSA 54 C_CK_BSEL2 RC84 33
23 VSS_REF REF/FSC/TEST_SEL Dummy C_14M_MCH [27]
34 VSS_SRC1
Buffer thru mode
4
VSS_SRC2
*
RC91 10K IDTCV184-2APAG8 +3V_CLK 20100107: RC84 change to 33ohm; PDG 0.8
+3V_S5
Dummy Dummy Dummy
**
C_CK505_SRC5_DP RC90 10K
C_CK505_SRC5_DN RC93 10K

+3V Dummy
+3V +3V
A Dummy RC73 and add RC11 A
FREQ BSEL0 BSEL1 BSEL2 C_CK_BSEL1 10K
* 10K * RC87 pull-up to +3V; CRB 0.7-12/28/09

RC86 RC89 Dummy
Dummy * 10K +3V Dummy Dummy Dummy Dummy
100 1 0 1
C_CK_BSEL0
Dummy C_CK_BSEL2
* CC30
1uF
16V, X5R, +/-10%
* CC31
1uF * CC32
1uF * CC33
0.1uF Title
16V, X5R, +/-10%
16V, X5R, +/-10%
16V, X7R, +/-10%

133 1 0 0 * 10K *RC11 Clock GEN
RC95 1K
Dummy +/-1% DWG NO Rev
Dummy A00
Gold Coast_MT/DT
*
RC73 0 P_VR_READY_R
[24,33,52,64,67] P_VR_READY
Dummy +/-5%
5 4 3 2 1
5 4 3 2 1
D D
+3V
RNK1
K_AD[31..0] [58]
Change AV14 to BH8
US1A
BF15 K_AD0
K_INTA#
K_INTB#
*1 2
[58] K_PAR BH9 PAR AD0 BF17 K_AD1 K_INTC# 3 4
K_PCIRST#_SLOT-12/28/09 [58] K_DEVSEL# BD15 DEVSEL# AD1 BT7 K_AD2 K_INTD# 5 6
[27] C_PCI_SB AV14 CLKIN_PCILOOPBACK AD2 BT13 K_AD3 7 8
[58] K_PCIRST#_SLOT BF11 PCIRST# AD3 BG12 K_AD4 8.2K
[58] K_IRDY# AV15 IRDY# AD4 BN11 K_AD5
[58] K_PME# BR6 PME# AD5 BJ12 K_AD6 RNK2
[58] K_SERR# SERR# AD6
[58] K_STOP#
BC12
BA17 STOP# AD7
BU9
BR12
K_AD7
K_AD8
K_INTF# change to PCIE_MINI_CPUSB_DETECT# *1 2
[58] K_LOCK# BC8 PLOCK# AD8 BJ3 K_AD9
V_DDSP_C_HPD-12/30/09V_GPI_VGA_CBL_DET# 3 4
[58] K_TRDY# BM3 TRDY# AD9 BR9 K_AD10 PCIE_MINI_CPPE_DETECT# 5 6
[58] K_PERR# PERR# AD10 20100108: Remove 7 8
BC11 BJ10 K_AD11
[58] K_FRAME# FRAME# AD11 BM8 K_AD12 V_DDSP_C_HPD pull-up 8.2K
AD12
PCI
GNT [3:0] have Internal Pull-High to 3.3V BF3 K_AD13
AD13 BN2 K_AD14
AD14
****
BA15 BE4 K_AD15 K_REQ#0 RS7 8.2K +/-5%
[58] K_GNT#0 K_GNT#1 AV8 GNT0# AD15 BE6 K_AD16 K_REQ#1 RS8 8.2K +/-5%
K_GNT#2 BU12 GNT1# / GPIO51 AD16 BG15 K_AD17 K_REQ#2 RS9 8.2K +/-5%
K_GNT#3 BE2 GNT2# / GPIO53 AD17 BC6 K_AD18 K_REQ#3 RS10 8.2K +/-5%
GNT3# / GPIO55 AD18 BT11 K_AD19
AD19 BA14 K_AD20
AD20 BL2 K_AD21
K_REQ#0 BG5 AD21 BC4 K_AD22 RNK4
[58] K_REQ#0 REQ0# AD22
K_REQ#1
K_REQ#2
BT5
BK8 REQ1# / GPIO50 AD23
BL4
BC2
K_AD23
K_AD24
K_FRAME#
K_IRDY#
*1 2
C K_REQ#3 AV11 REQ2# / GPIO52 AD24 BM13 K_AD25 K_TRDY# 3 4 C
REQ3# / GPIO54 AD25 BA9 K_AD26 K_DEVSEL# 5 6
AD26 BF9 K_AD27 7 8
AD27 BA8 K_AD28 8.2K
BK10 AD28 BF8 K_AD29
[58] K_INTA# BJ5 PIRQA# AD29 AV17 K_AD30 RNK5
[58] K_INTB# PIRQB# AD30
[58] K_INTC#
BM15
BP5 PIRQC# AD31
BK12 K_AD31 K_STOP#
K_LOCK#
*1 2 +3V
[58] K_INTD# BN9 PIRQD# K_C/BE#[3..0] [58] 3 4
PCIE_MINI_CPUSB_DETECT# K_PERR#
AV9 PIRQE# / GPIO2 BN4 K_C/BE#0 K_SERR# 5 6
[26,41] V_DDSP_C_HPD BT15 PIRQF# / GPIO3 C/BE0# BP7 7 8
K_C/BE#1
[42] V_GPI_VGA_CBL_DET# BR4 PIRQG# / GPIO4 C/BE1# BG2 K_C/BE#2 8.2K
PCIE_MINI_CPPE_DETECT# PIRQH# / GPIO5 C/BE2#
C/BE3#
BP13 K_C/BE#3 *RS13
1/12 +3V_PCIAUX
1K
BD82Q67 Dummy
K_GNT#0
*
K_PME# RS198 8.2K +/-5%
Dummy
K_PME# add RS198 to pull-up *RS18
+3V_PCIAUX; CRB 0.7-12/28/09
1K
20100108: Dummy RS198; Dummy
PDG 0.8
20091209: Have to check with Intel

B B
S_SATA1GP has external 10k pull-up; CRB 0.7 20091230: Reserved RS171 and
*
F_LPC_DEBUG RS11 8.2K +/-5%

*RS12 +3V RS201 for Boot select
1K GNT3# Internal pull-up.
S_SATA1GP +/-5%
Boot BIOS Select

*RS14 *
3
RS171
**
QS1 10K K_GNT#2 RS15 1K
1K
Dummy Boot Device GNT1 SATA1GP Dummy
MMDT5551 Dummy K_GNT#3 RS17 4.7K
LPC 0 0 Dummy
K_GNT#1 DG 0.7
PCI 1 0
4
6
*
RS16 K_GNT#1
GNT3 is top block swap mode:
1K +/-5%
[23] S_SATA1GP NAND 0 1 connect to ground with 4.7k ohm weak
*
RS19 8.2K +/-5%

F_LPC_DEBUG [53] SPI 1 1 pull down resistor for top block swap mode
CS1
* 1uF *RS20 *RS201 GNT2#/GPIO53:ESI strap for server platform
16V, X5R, +/-10%
1K 1K
Dummy ONLY,Do not pull low.
Dummy Dummy
A A
Title
PCH-1: PCI
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
USB0 ~ 1 --> LAN/USB Conn

USB2 ~ 5 --> REAR Conn
USB6 ~ 7 --> FRONT USB
USB8 ~ 9 --> INT USB @MT If not use , USB OC Pin need external pull up
USB10 ~ 11 --> FRONT USB
USB12 --> Mini PCIe
USB13 --> NA +3V_S5
D US1B D
D33 BF36
[10] H_DMI_TXN0 B33 DMI0RXN USBP0N BD36 U_USB0N [35]
[10] H_DMI_TXP0 J36 DMI0RXP USBP0P BC33 U_USB0P [35]
In DT should be Stuff
[10]
[10]
H_DMI_RXN0
H_DMI_RXP0
H36 DMI0TXN
DMI0TXP
USBP1N
USBP1P
BA33 U_USB1N
U_USB1P
[35]
[35]
*RS21
8.2K *RS23
8.2K *RS196
8.2K
In MT should be Empty for INT USB
A36 BM33 +/-5% +/-5% +/-5%
[10] H_DMI_TXN1 B35 DMI1RXN USBP2N BM35 U_USB2N [45]
Dummy Dummy
[10] H_DMI_TXP1 P38 DMI1RXP USBP2P BT33 U_USB2P [45]
[10] H_DMI_RXN1 R38 DMI1TXN USBP3N BU32 U_USB3N [45]
[10] H_DMI_RXP1 B37 DMI1TXP USBP3P BR32 U_USB3P [45]
[10] H_DMI_TXN2 C36 DMI2RXN USBP4N BT31 U_USB4N [45] U_USB_OC_R_#1 CU1 0.1uF Dummy
***
[10] H_DMI_TXP2 H38 DMI2RXP USBP4P BN29 U_USB4P [45]
16V, X7R, +/-10%
[10] H_DMI_RXN2 J38 DMI2TXN USBP5N BM30 U_USB5N [45] U_USB_OC_R_#2 CU2 0.1uF Dummy
[10] H_DMI_RXP2 DMI2TXP USBP5P U_USB5P [45]
DMI
E37 BK33 16V, X7R, +/-10%
[10] H_DMI_TXN3 F38 DMI3RXN USBP6N BJ33 U_USB6N [56] U_USB_OC_R_#3 CU3 0.1uF Dummy
+1P05V_PCH
[10] H_DMI_TXP3 M41 DMI3RXP USBP6P BF31 U_USB6P [56]
16V, X7R, +/-10%
[10] H_DMI_RXN3 P41 DMI3TXN USBP7N BD31 U_USB7N [56]
[10] H_DMI_RXP3 B31 DMI3TXP USBP7P BN27 U_USB7P [56]
*
RS24 49.9 +/-1% S_DMI_COMP E31 DMI_IRCOMP USBP8N BR29 U_USB8N [61] U_USB_OC_R_#4 CU18 0.1uF Dummy
**
DMI_ZCOMP USBP8P BR26 U_USB8P [61]
L<0.5" USBP9N U_USB9N [61]
16V, X7R, +/-10%
20091211:0.7 CRB and PDG are BT27 U_USB_OC_R_#5 CU4 0.1uF Dummy
P33 USBP9P BK25 U_USB9P [61]
16V, X7R, +/-10%
suggested to connect to [20,27] C_DMI_PCH# R33 CLKIN_DMI_N USBP10N BJ25 U_USB10N [56]
V_1P05_PCH [20,27] C_DMI_PCH CLKIN_DMI_P USBP10P BJ31 U_USB10P [56]
USBP11N U_USB11N [56]
USB
BK31 GPO_WLOM CU6 0.1uF Dummy
*
USBP11P BF27 U_USB11P [56]
20091228: Pin B31, E31 connect to U_USB12N 16V, X7R, +/-10%
USBP12N BD27 U_USB12P TPS13
+1P05V_PCH via RS24 X_1X1_RXN J20 USBP12P BJ27 TPS14
TPS15 X_1X1_RXP L20 PERN1 USBP13N BK27
C TPS16 P20 PERP1 USBP13P C
TPS6 PERN2 20100106: Change to GPO_WLOM
R20
TPS7 H17 PERP2 BM43
[59] X_2X1_RXN PERN3 OC0# / GPIO59 U_USB_OC_R_#0 [35] OC 0 --> Port 0,1 -LAN/USB Conn
J17 BD41 OC 1 --> Port 2,3 -REAR Conn
[59] X_2X1_RXP P17 PERP3 OC1# / GPIO40 BG41 U_USB_OC_R_#1 [45]
[34] X_L1X1_RXN PERN4 OC2# / GPIO41 U_USB_OC_R_#2 [45] OC 2 --> Port 4,5 -REAR Conn
M17 BK43 OC 3 --> Port 6,7 -FRONT IO
[34] X_L1X1_RXP N15 PERP4 OC3# / GPIO42 BP43 U_USB_OC_R_#3 [56]
[39] X_1X4_RXN0 PERN5 OC4# / GPIO43 U_USB_OC_R_#4 [61] OC 4 --> Port 8,9 -INT USB@MT
M15 BJ41 OC 5 --> Port 10,11 -FRONT IO
[39] X_1X4_RXP0 J15 PERP5 OC5# / GPIO9 BT45 U_USB_OC_R_#5 [56]
[39] X_1X4_RXN1 PERN6 OC6# / GPIO10
X_WLAN_WAKE# OC 6 --> NA
L15 BM45 OC 7 --> NA
[39] X_1X4_RXP1 J12 PERP6 OC7# / GPIO14 GPO_WLOM [59]
[39] X_1X4_RXN2 PERN7 20100106: Change to GPO_WLOM
H12
[39] X_1X4_RXP2 H10 PERP7
[39] X_1X4_RXN3 J10 PERN8 PCI-E BP25 S_USBRBIAS_PCH RS25 22.6
[39] X_1X4_RXP3
X_1X1_TXN F25 PERP8 USBRBIAS# BM25
TPS17 PETN1 USBRBIAS
L <=200 MILS +/-1%
X_1X1_TXP F23
TPS26 C22 PETP1 BD38
TPS11 A22 PETN2 CLKIN_DOT_96N BF38 C_96M_PCH# [20,27]
TPS12 E21 PETP2 CLKIN_DOT_96P C_96M_PCH [20,27]
*
[59] X_2X1_TXN B21 PETN3 A32 RS26 750
[59] X_2X1_TXP F18 PETP3 DMI2RBIAS +/-1%
[34] X_L1X1_TXN E17 PETN4 AG12
[34] X_L1X1_TXP B17 PETP4 L_BKLTCTL AG18 TPS8
[39] X_1X4_TXN0 C16 PETN5 L_BKLTEN AG17 TPS9
[39] X_1X4_TXP0 A16 PETP5 L_VDD_EN TPS10
[39] X_1X4_TXN1 B15 PETN6
[39] X_1X4_TXP1 F15 PETP6
[39] X_1X4_TXN2 F13 PETN7 +3V_S5
[39] X_1X4_TXP2 B13 PETP7
[39] X_1X4_TXN3
*
B D13 PETN8 X_WLAN_WAKE# RS82 10K
B
[39] X_1X4_TXP3 PETP8 2/12
BD82Q67
PCIe 1: mini PCIe
PCIe 2: NA
PCIe 3: PCIe x1 slot
PCIe 4: LAN
PCIe 5 ~ 8: PCIe x4 slot
A A
Title
PCH-2: DMI/PCIe/USB
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
*
S_INIT3_3VB RS27 1K
Dummy
US1C
AC56
20100107:Remove test points AE49 SATA0RXN AB55 T_SATA_RXN0 [43]
TP13 SATA0RXP T_SATA_RXP0 [43] This signal should not be pulled low on
CLINK
AE41 AE46
TP14 SATA0TXN AE44 T_SATA_TXN0 [43] EDS 0.5- Sherlock 10/27/09
BA50 SATA0TXP AA53 T_SATA_TXP0 [43]
20100105:Remove TPS45 S_CLINK_CLK_LAN
S_CLINK_DATA_LAN BF50 CL_CLK1 SATA1RXN AA56 T_SATA_RXN1 [43]
TPS46 CL_DATA1 SATA1RXP T_SATA_RXP1 [43]
Test Point S_CLINK_RST_LAN# BF49 AG49
TPS47 CL_RST1# SATA1TXN T_SATA_TXN1 [43]
D 20100107: Remove RS47, RS48 and AG47 D
BC46 SATA1TXP AL50 T_SATA_TXP1 [43]
connect S_PCH_MEPWROK_R to [66] PCH_MEPWRGD APWROK SATA2RXN AL49 T_SATA_RXN2 [43]
SATA2RXP AL56 T_SATA_RXP2 [43]
S_PCH_MEPWROK directly SATA2TXN AL53 T_SATA_TXN2 [43]
+3V
SATA2TXP AN46 T_SATA_TXP2 [43]
20100104: Add TPS23,TPS25 and SATA3RXN T_SATA_RXN3 [60]
TPS23 S_TP_CPUFAN_PWM BN21 AN44
remove RS29,RS30,RS33, RS34 since S_TP_CHAFAN1_PWM BT21 PWM0 SATA3RXP AN56 T_SATA_RXP3 [60]
TPS25 PWM1 SATA3TXN T_SATA_TXN3 [60]
S_TP_CHAFAN2_PWM BM20 AM55
useless this function TPS18
SATA
S_TP_CHAFAN3_PWM BN19 PWM2 SATA3TXP AN49 T_ESATA_RXN4 T_SATA_TXP3 [60]
TPS19 PWM3 SATA4RXN TPS34
BT17 AN50 T_ESATA_RXP4
*******
[31] S_GPI_CHASSIS_ID1 BR19 TACH0 / GPIO17 SATA4RXP AT50 TPS52
T_ESATA_TXN4 O_KB_RST# RS28 10K
[31] S_GPI_CHASSIS_ID0 BA22 TACH1 / GPIO1 SATA4TXN AT49 T_ESATA_TXP4 TPS54 O_GA20 RS31 10K
[30] S_GPI_PCH_HS_DET# BR16 TACH2 / GPIO6 SATA4TXP AT46 TPS56
F_SERIRQ# RS32 10K
[31] S_GPI_SKU2 TACH3 / GPIO7 SATA5RXN AT44 TPS20 S_GPIO48_PU RS56 10K
SATA5RXP AV50 TPS21
S_GPI_PCH_HS_DET# RS58 10K
SATA5TXN TPS22
FAN
BU16 AV49 O_PRT_DET# RS109 10K
[31] S_GPI_BRD_REV2 BM18 TACH4 / GPIO68 SATA5TXP AF55 TPS24
RS61 10K
[62] O_PRT_DET# BN17 TACH5/ GPIO69 CLKIN_SATA_N / CKSSCD_N AG56 C_SATA_PCH# [20,27] [56] A_FP_PRES#
[56] S_FP_CHAS_DET# BP15 TACH6 / GPIO70 CLKIN_SATA_P / CKSSCD_P C_SATA_PCH [20,27]
+3V RS144 10K
TACH7 / GPIO71 BF57
Add RS 144 and pull-up
*
SATALED# AJ55 T_SATALED# [56] +1P05V_PCH
to +3V; CRB SATAICOMPI
check : using 37.4 ohm in DG , 49.9 ohm in CRB
*
BC43 AJ53 S_SATARBIAS_PCH RS36 37.4 Ohm 20091209: CRB0.7 and PDG0.7 are
0.7-12/07/09 TPS28 SST SATAICOMPO +/-1% 20091214:
FAN control from BC54 suggested RS36
37.4 ohmchange to 37.4 ohm
SATA0GP / GPIO21 AY52 S_GPI_BRD_REV0 [31]
SMSC 5544 SATA1GP / GPIO19 BB55 S_SATA1GP [21]
SATA2GP / GPIO36 TPS27 20091209: CRB0.7 V_DDSP_C_HPD is connected to PCH
BG53
without using SST SATA3GP / GPIO37 AU56
TPS39
pin N2 only , no connected to GPIO19,check whether
C H_SKTOCC_R_# C
SATA4GP / GPIO16 BA56
SATA5GP / GPIO49 TMIN_SHIFT [32] RS35 need stuff for meet Intel PDG ?
+1P05V_PCH
20091230: Change to S_SATA1GP for Boot
*
AE54 RS37 49.9
*
SATA3COMPI AC52 RS38 750 +/-1% Select
SATA3RBIAS
GPIO
S_PCH_CONFIG_JUMPER BA53 AE52 +/-1%
A_FP_PRES# BF55 SCLOCK / GPIO22 SATA3RCOMPO
S_GPIO48_PU AW53 SDATAOUT0 / GPIO39 20100107:Remove test points
BE54 SDATAOUT1 / GPIO48
[31] S_GPI_CHASSIS_ID2 SLOAD / GPIO38 AB18
TP8
BB57
A54 A20GATE BN56 O_GA20 [32]
TPS30 A52 NC_1 INIT3_3V# BG56 S_INIT3_3VB [53]
TPS31 F57 NC_2 RCIN# AV52 O_KB_RST# [32]
TPS32 D57 NC_3 3/12 SERIRQ E56 F_SERIRQ# [32,46]
*
TPS33 NC_4 THRMTRIP# H_THERMTRIP# [9]
HOST
AY20 H48 RS39 0
NC_5 PECI F55 H_PECI [9,32]
PMSYNCH
Dummy Dummy RS39; SMSC suggestion-12/08/09
H_PM_SYNC [9]
BD82Q67
+3V
+3V
B PCH_CONFIG B
*RS55 * RS53
1K 10K
20100107: Remove RS47, RS48 and connect
S_PCH_MEPWROK_R to S_PCH_MEPWROK directly
*
S_PCH_CONFIG_JUMPER H_SKTOCC_R_# RS57 0
H_SKTOCC# [9,24]
Dummy
*RS60 *RS59
4.7K STUFF RS57 FOR ME ON CPU
Dummy 10K
Dummy PRESENT DETECTION
A A
Title
PCH-3: SATA/HOST/FAN
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
CLOCK VALIDATION STRAP
SPKR Control Option of SIO / PCH +3V +3V +3V_S5
+3V +3V
EMPTY JUMPER FOR BUFFER THROUGH MODE
* * ****
Internal pull-up RS62 0 S_SPKR RS63 1K High: Disable Intergrated Clock Chip H_SKTOCC# RS64 100K
[31] S_SPKR_OUT Dummy O_IO_PME# RS68 10K
Low: Enable Intergrated Clock Chip
S_SPKR *RS67 X1_WAKE#
*RS65
10K *RS66
10K
Pop To Enable No-Reboot 10K
Has a weak Internal Pull-High S_PCIAUX_GATE
RS69
RS173
10K
10K
Dummy Dummy 20100106: Add RS173
20091223: signal rename US1D Iinternal pull-down.
+3V_DUAL L_DRQ1# BA20 AW55 S_WAKE# RS79 1K
to S_SUSWARN# BK15 LDRQ1# / GPIO23 BMBUSY# / GPIO0 BP51 S_TP_GP8 S_PECI_REQ# [32]
Dummy 20091221: Dummy RS80 follow CRB0.7
[32,46,53] F_LAD0 FWH0 / LAD0 GPIO8 TPS40
* ** ***** *
RS81 10K S_SUSWARN# BJ17 BH49 S_SUS_PWR_ACK# RS80 10K
*
+3V_S5 [32,46,53] F_LAD1 BJ20 FWH1 / LAD1 SLP_LAN# / GPIO29 BU46 S_SLP_LAN# [35] S_GP27_PD RS71 1K Dummy
[32,46,53] F_LAD2 BG20 FWH2 / LAD2 SUSWARN# / SUSPWRDNACK / GPIO30 BK50 S_SUSWARN# [64] Dummy
RS72 10K S_MFG_MODE_OR
RS83 10K S_SMLINK1_CLK [32,46,53] F_LAD3 BK17 FWH3 / LAD3 LAN_PHY_PWR_CTRL / GPIO12 BA25 L_LAN_DISABLE# [34]
D D
LDRQ0# HDA_DOCK_RST# / GPIO13
* * * **
S_SMLINK1_DATA [32] F_LDRQ# BG17 BM55 S_PCH_GP15 X1_WAKE# [59] S_PCH_GP72_PU
RS73 10K RS174 10K
[32,46,53] F_FRAME# FWH4 / LFRAME# GPIO15
LPC
RS85 2.2K S_SMLINK0_CLK 20091223: BU46 signal S_SLP_LAN# RS75 1K
RS86 2.2K S_SMLINK0_DATA AV43 Dummy
PCIECLKRQ2# / GPIO20 BP53 S_FLEXBAY_HDR_CBL_DET# [27,61] rename to S_SUSWARN#
Dummy
RS74 10K F_SPI_CS1# MEM_LED / GPIO24 H_SKTOCC# [9,23] S_PCH_SYSPWROK RS193 10K
RS76 10K X4_WAKE# 20091223: BP53 signal name Dummy
Dummy
RS89 1K BJ43 S_GP27_PD change to H_SKTOCC# . S_PCH_GP28_PU RS84 10K
A_Z_SDOUT_R [31] GPIO27
**
RS77 33 A_Z_BITCLK_R BU22 BJ55 S_PCH_GP28_PU
[36] A_Z_BITCLK RS78 33 A_Z_RST#_R BC22 HDA_BCLK GPIO28 BG43 RS151 1K
[36] A_Z_RST# BD22 HDA_RST# GPIO31 BC56 S_PSWD_CLR [31]
AUDIO
CPT FLASH DESCRIPT OR [36] A_Z_SDIN0 S_GPI_SKU0 [31]
Dummy
BF22 HDA_SDIN0 CLKRUN#/GPIO32 BC25
OVERRIDE.HIGH FOR OVERRIDE TPS35 HDA_SDIN1 HDA_DOCK_EN#/GPIO33 TPS38 20100106: Reserved RS151 for
BK22 BL56 PCH_GPIO34
TPS36 BJ22 HDA_SDIN2 STP_PCI# / GPIO34 BJ57 Disable 1.05V Regulator
**
TPS37
RS90 0 A_Z_SDOUT_R BT23 HDA_SDIN3 GPIO35 BL54 S_GPI_SKU1 [31]
[36] A_Z_SDOUT HDA_SDO PCIECLKRQ5# / GPIO44 S_INTRUD_CBL_DET# [27,31]
RS92 33 A_Z_SYNC_R BP23 AV44 High: Enable 1.05V Regulator
[36] A_Z_SYNC HDA_SYNC PCIECLKRQ6# / GPIO45 BP55 O_COM_SER2_DET# [27,55]
PCIECLKRQ7# / GPIO46 S_GPI_BRD_REV1 [31] Low: Disable 1.05V Regulator
Dummy
*
RS91 1K A_Z_SYNC_R Has a weak Internal Pull-High

FVS BT53 S_GPIO57_PD
GPIO57 20091221: BD43 removed Reserved for CPU VR and TPM type
OD PLL VR SUPPLY SEL(internal pull down)
1.8V SUPPLY WHEN SAMPLED LOW 1 L_DRQ1# D53 TPS38 and rename signal
1 PROCPWRGD H_PWRGD [9,52,64]
1.5V SUPPLY WHEB SAMPLED HIGH to S_SLP_SUS# ; BT37
20091216: RS87 used 1k , PDG0.7
Dummy BD43 rename S_RSMRST# to +3V_S5
SLP_SUS# BJ53 S_PCH_SYSPWROK S_SLP_SUS# [64,65]
20091223: Add RS151, RS197 TEST POINT S_PCH_DPWROK_R ; BP45
S_SUSWARN# SYS_PWROK BT43
* *
DS mode: PWRBTN# BJ48 O_PWRBTN#IN [32,52,53,56]
rename to S_PCH_GP15 RS87 1K
BR39 RI# BN54 O_IO_PME# [32]
RTC
C S_PCH_RTCX1 S_LPCPD# +3V_DUAL C
* RS197
20100104: Remove RS151,
S_PCH_RTCX2 BN39 RTCX1
RTCX2
SUS_STAT# / GPIO61
SUSCLK / GPIO62
BA47
S_SUSCLK [32]
S_SUS_PWR_ACK
1K P.64 has same circuit BT41 BE52 S_GP27_PD RS88 10K
[29,31] S_RTCRST# S_SRTRST# BN37 RTCRST# SYS_RESET# BK48 FP_RST# [9,52,53]
Dummy +3V
SRTCRST# PLTRST# BC44 S_PLTRST# [9,32,34,46,52,53]
**
WAKE# BM38 S_WAKE# [38] PCH_GPIO34 RS119 10K
BN49 INTRUDER# BJ38 S_INTRUDER# [31]
[39] X4_WAKE# BT47 SMBALERT# / GPIO11 PWROK BK38 PWRGD_3V [32,52] FP_RST# RS199 10K
[13,16,18,32,38,39,58,59] S_SMBCLK_PCI BR49 SMBCLK RSMRST# BN41 S_RSMRST# [64]
SMB
S_INTVRMEN 20091224: change to
13,16,18,32,38,39,58,59] S_SMBDATA_PCI BU49 SMBDATA INTVRMEN BE56 S_SPKR
CS2 CS3 [40] GPIO_WIRELESS_DISABLE# BT51 SML0ALERT# / GPIO60 SPKR BP45 S_SUS_PWR_ACK# +3V
[34] S_SMLINK0_CLK BM50 SML0CLK SUSACK# S_SUS_PWR_ACK# [64]
+3V_S5
22pF
Dummy * * 22pF
Dummy [34] S_SMLINK0_DATA
[31] S_MFG_MODE_OR
BR46 SML0DATA BM53
S_SLP_S3# [20,32,64,66,69,70]
SML1ALERT#/PCHHOT#/GPIO74 SLP_S3#
50V, NPO, +/-5%
50V, NPO, +/-5%
BJ46 BN52
[32] S_SMLINK1_CLK BK46 SML1CLK / GPIO58 SLP_S4# BH50 S_SLP_S4# [32,65,70] 20100104: Dummy RS87;
RF1
[32] S_SMLINK1_DATA SML1DATA / GP75 SLP_S5# / GPIO63 BC41 S_PCIAUX_GATE [65] follow CRB 0.7
* 10K 20091223: BU49 signal name
SLP_A#
BR42
S_SLP_M# [32,65,66]
Dummy DSWODVREN
change to X_WLAN_WAKE# DSWVRMEN AV46 S_PCH_GP72_PU
S_GPIO57_PD BATLOW#/GPIO72 BG46
*** *
*
RS101 0 F_SPI_MOSI AU53 DRAMPWROK BT37 S_PCH_DPWROK_R H_DRAMPWRGD [11] RS195 0 S_PCH_SYSPWROK
[51] F_SPI_MOSI_PRI_SEC_FLSH AT55 SPI_MOSI DPWROK [20,33,52,64,67] P_VR_READY
SPI
*RF2 [51] F_SPI_MISO
[51] F_SPI_CS0#_ISOLATE
RS102 0 F_SPI_CS0# AT57 SPI_MISO
SPI_CS0# JTAG_RST/TP12
BC49
F_PCH_JTAG_RST# [52] * RS194 CS43
F_SPI_CLK AR54 BA43
47K
[51] F_SPI_CLK_PRI_SEC_FLSH
[51] F_SPI_CS1#_ISOLATE
RS103
RS104
0
0 F_SPI_CS1# AR56 SPI_CLK
SPI_CS1#
JTAG_TCK
JTAG_TDI
BC52 F_PCH_JTAG_TCK_FILTER
F_PCH_JTAG_TDI [52]
[52]
10K
Dummy * 22uF
6.3V,X5R,+/-20%
BF47 Dummy
JTAG_TDO BC50 F_PCH_JTAG_TDO [52]
CLOSE TO PCH JTAG_TMS F_PCH_JTAG_TMS [52]
0 OHM FOR DEFENSIVE DESIGN 4/12
B 66MHZ SPI TOPOLOGY, 20091224: S_TP_SLP_S5# change to B
Integrated TPM BD82Q67
+3V S_PEG_B_CLKREQ#
High to Enable
*
* *
1K S_PCH_DPWROK +VCCRTC RS146 0 S_PCH_DPWROK
*
Low to Disable [32] O_RSMRST# RS112 S_INTVRMEN RS107 390KOhm

C
Internal +/-5% Dummy

*RF3
8.2K
pull-down
*RS113
10K
BAT54HT1G
*RS108 S_PCH_DPWROK_R RS149 0 S_RSMRST#
+/-5% +/-1% 1K 20091221: Add RS146, RS149
Dummy DS3 Dummy
DS mode: RS146 pop, RS149 dis-pop +3V_S5
A
F_SPI_MOSI Internal 1.1V and VCCME regulator non-DS mode: RS146 dis-pop, RS149 pop +1P5V_SM
SMSC recommend S_RSMRST#
enable(high)/disable(low) PWRGD_3V
01/13/11 RS93
+VCCRTC 200 Ohm
+/-1%
CS72
470pF
*
*
*
+5VSB DSWODVREN RS114 390KOhm S_LPCPD# RO1 8.2K +/-5% Dummy
+/-5% Dummy H_DRAMPWRGD 50V, X7R, +/-10%
*
RS115 4.7K
RTC
*RS116
2KOhm *RS94
3KOhm
+/-1% X'TAL CLR_SRTC
+/-1%
S_PCH_RTCX2 Dummy
*RS117
3
10K S_PCH_RTCX1
QS2 +/-1% 20091214: CS4 stuffed
MMDT5551 RS118 10M
SMSC recommend +/-5% +VCCRTC
+3V
A 01/13/11 A
C
+5VSB
4
S_PCH_DPWROK B QS3 Near to Pch

MMBT3904-7-F XTAL 32.768KHz * RS105
XS1 20K
E
*
1 4
RS120 1K RS121 5.6K
+/-1% S_SRTRST# * CS5
0.1uF * CS6
0.1uF * CS7
0.1uF Title
*RS123
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

* CS8
*RS122 PCH-4: LPC/HDA/RTC/SMB/SPI
2
1uF
+/-10%
1.1KOhm
+/-1%
2KOhm
+/-1% * CS9
10pF * CS10
10pF
* CS4
Dummy 50V, NPO, +/-5% 50V, NPO, +/-5% 1uF DWG NO Rev
16V, X5R, +/-10% A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
D D
20100106: Remove ONFI function since not support
S_NVR_CLE internal pull-down.

US1E
M48 AB50
R47 NV_ALE NV_DQ0 / NV_IO0 Y50
[9] M_NVR_CLE NV_CLE NV_DQ1 / NV_IO1
Y41 AB49
M50 NV_RB# NV_DQ2 / NV_IO2 AB44
M49 NV_RE#_WRB0 NV_DQ3 / NV_IO3 U49
20100107:remove test points
U43 NV_RE#_WRB1 NV_DQ4 / NV_IO4 R44
J57 NV_WE#_CK0 NV_DQ5 / NV_IO5 U50
NV_WE#_CK1 NV_DQ6 / NV_IO6 U46
NV_DQ7 / NV_IO7 U44
NV_DQ8 / NV_IO8 H50 20100107:remove test points
NV_DQ9 / NV_IO9 K46
NV_DQ10 / NV_IO10 L56
NV_DQ11 / NV_IO11 J55
NV_DQ12 / NV_IO12 F53
NV_DQ13 / NV_IO13 H52
NV_DQ14 / NV_IO14 E52
NV_DQ15 / NV_IO15
K50
NV_CE#0 K49
NV_CE#1 AB46
C NV_CE#2 G56 C
NV_CE#3
NVRAM Y44
NV_DQS0 L53
NV_DQS1
R50 S_TP_NV_RCOMP
NV_RCOMP TPS29
5/12
BD82Q67
US1G
C42
FDI_RXN0 B43 H_FDI_TXN0 [10]
FDI_RXP0 F45 H_FDI_TXP0 [10]
FDI_RXN1 F43 H_FDI_TXN1 [10]
FDI_RXP1 H41 H_FDI_TXP1 [10]
FDI_RXN2 J41 H_FDI_TXN2 [10]
FDI_RXP2 C46 H_FDI_TXP2 [10]
FDI_RXN3 D47 H_FDI_TXN3 [10]
FDI_RXP3 B45 H_FDI_TXP3 [10]
FDI_RXN4 A46 H_FDI_TXN4 [10]
FDI_RXP4 B47 H_FDI_TXP4 [10]
FDI_RXN5 C49 H_FDI_TXN5 [10]
FDI_RXP5 J43 H_FDI_TXP5 [10]
FDI LINK
B FDI_RXN6 H43 H_FDI_TXN6 [10] B

FDI_RXP6 M43 H_FDI_TXP6 [10]
FDI_RXN7 P43 H_FDI_TXN7 [10]
FDI_RXP7 H_FDI_TXP7 [10]
B51
FDI_FSYNC0 E49 H_FDI_FSYNC0 [10]
FDI_LSYNC0 C52 H_FDI_LSYNC0 [10]
FDI_FSYNC1 D51 H_FDI_FSYNC1 [10]
FDI_LSYNC1 H_FDI_LSYNC1 [10]
H46
FDI_INT H_FDI_INT [10]
7/12
BD82Q67
A A
Title
PCH-5/7: NVRAM/FDI
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
D D
20100108: Dummy RS128,RS129: CRB 0.7 20100107: Correct pin T1 and M1 net name to
S_DDPB_HPD_PD and S_DDPD_HPD_PD
US1F
**
RS128 1K +/-1% Dummy S_DDPB_HPD_PD T1 AR4 V_HSYNC
N2 DDPB_HPD CRT_HSYNC AR2 V_VSYNC
[21,41] V_DDSP_C_HPD S_DDPD_HPD_PD M1 DDPC_HPD CRT_VSYNC
RS129 1K +/-1% Dummy
DDPD_HPD AN6
R8 CRT_RED AN2 V_RED [42]
TP_DDSP_B_AUX_DN R9 DDPB_AUXP CRT_GREEN AM1 V_GREEN [42]
TPS41 U14 DDPB_AUXN CRT_BLUE V_BLUE [42]
[41] V_DDSP_C_AUX_DP U12 DDPC_AUXP AM6
[41] V_DDSP_C_AUX_DN TP_DDPD_AUXP N6 DDPC_AUXN CRT_IRTN
TPS42 R6 DDPD_AUXP
TP_DDPD_AUXN
TPS43 DDPD_AUXN
AW1
TP_DDPB_0P R14 CRT_DDC_DATA AW3 V_DDCA_DATA [42]
C TPS44 R12 DDPB_0P CRT_DDC_CLK V_DDCA_CLK [42] C
M11 DDPB_0N AT3 V_DACREFSET RS130 1KOhm
M12 DDPB_1P DAC_IREF L<500 MILS +/-0.5%
TP_DDPB_2P H8 DDPB_1N
TPS48 TP_DDPB_2N K8 DDPB_2P
TPS49 DDPB_2N
NON-Graphic sku : Change to O ohm
TP_DDPB_3P L5
TPS50 TP_DDPB_3N M3 DDPB_3P
TPS51 L2 DDPB_3N
[41] V_DDSP_C_DP_0_DP J3 DDPC_0P
[41] V_DDSP_C_DP_0_DN G2 DDPC_0N
[41] V_DDSP_C_DP_1_DP G4 DDPC_1P
[41] V_DDSP_C_DP_1_DN F3 DDPC_1N
[41] V_DDSP_C_DP_2_DP F5 DDPC_2P
[41] V_DDSP_C_DP_2_DN E4 DDPC_2N
[41] V_DDSP_C_DP_3_DP E2 DDPC_3P
[41] V_DDSP_C_DP_3_DN D5 DDPC_3N DISPLAY
TP_DDPD_0N B5 DDPD_0P
TPS53 C6 DDPD_0N
TP_DDPD_1N D7 DDPD_1P
TPS55 B7 DDPD_1N
TP_DDPD_2N C9 DDPD_2P
TPS57 TP_DDPD_3P E11 DDPD_2N
TPS58 B11 DDPD_3P
TP_DDPD_3N
TPS59 DDPD_3N AL12
DDPC_CTRLCLK AL14 V_DDPC_CTRL_CLK [41]
DDPC_CTRLDATA V_DDPC_CTRL_DATA [41]
TP_SDVO_INTP U2 AL9 TP_DDPD_CTRLCLK
TPS60 TP_SDVO_INTN T3 SDVO_INTP DDPD_CTRLCLK AL8 TP_DDPD_CTRLDATA TPS61
TPS62 SDVO_INTN DDPD_CTRLDATA TPS63
B W3 AL15 B
TP_SDVO_STALLP TP_SDVO_CTRLCLK
TPS64 TP_SDVO_STALLN U5 SDVO_STALLP SDVO_CTRLCLK AL17 TP_SDVO_CTRLDATA TPS65
TPS66 SDVO_STALLN SDVO_CTRLDATA TPS67
TP_SDVO_TVCLKINP U8
TPS68 TP_SDVO_TVCLKINN U9 SDVO_TVCLKINP
TPS69 SDVO_TVCLKINN
6/12
BD82Q67
V_RED NON-Graphic sku : Change to O ohm

**
V_GREEN V_HSYNC RS131 33

V_HSYNC_3V [42]
V_BLUE V_VSYNC RS132 33
V_VSYNC_3V [42]
RS133 RS134 RS135 L<750 MILS
A
* 150 *
150 * 150
*RS136 *RS137 NON-Graphic sku : Stuff O ohm
A
+/ -1% +/ -1% +/ -1% 0 0

Dummy Dummy
Title
CLOSE TO PCH: L<250 MILS
PCH-6: Display
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
D D
20100106: Remove RS96; CRB 0.7

20100106: Swap C_PCH_PCI0_R and C_PCI_SL1_R; CRB 0.7
20100106: Disconnect AT11 and left Test point; CRB 0.7
20100106: Change to US1H
AT11 W53 C_PCH_CSI#
22ohm; PDG 0.8 CLKOUT_PCI0 CLKIN_GND0_N V52 C_PCH_CSI
CLKIN_GND0_P
** **
RC97 22 C_LPC_TPM_R AN14
[46,53] C_LPC_TPM CLKOUT_PCI1 R52
RC98 22 C_PCI_PCH_R AT12 CLKOUT_ITPXDP_N N52 C_PCH_ITP# [52]
[21] C_PCI_SB CLKOUT_PCI2 CLKOUT_ITPXDP_P C_PCH_ITP [52]
RC99 22 C_LPC_SIO_R AT17 AE2
[32] C_LPC_SIO CLKOUT_PCI3 CLKOUT_PCIE7N AF1
RC100 22 C_PCI_SL1_R AT14 CLKOUT_PCIE7P
**
[58] C_PCI_SL1 CLKOUT_PCI4 P31 C_PE_100M_MCP#_R RS202 0
CLKOUT_DMI_N R31 C_PE_100M_MCP_R C_PE_100M_MCP# [9]
20100107: Swap CLKOUTFLEX CLK out; PDG 0.8 CLKOUT_DMI_P
RS203 0
C_PE_100M_MCP [9]
S_TP_CLKOUTFLEX0 AT9 R27 C_DMI2_PCH#
* **
TPS129 RC101 22 C_14M_SIO_R BA5 CLKOUTFLEX0 / GPIO64 CLKIN_GND1_N P27 C_DMI2_PCH
[32] C_14M_SIO S_TP_CLKOUTFLEX2 AW5 CLKOUTFLEX1 / GPIO65 CLKIN_GND1_P
TPS130 RC102 22 C_14M_TPM_R BA2 CLKOUTFLEX2 / GPIO66
[46] C_14M_TPM CLKOUTFLEX3 / GPIO67
20100108: Change N56 S_TP_CK_DP_PCH_DN
AL2 CLKOUT_DP_N / CLKOUT_BCLK1_N M55 S_TP_CK_DP_PCH_DP TPS126
RC104 91 Ohm XCLK_RCOMP
Power Source +1P05V_PCH
+/-1%
XCLK_RCOMP CLKOUT_DP_P / CLKOUT_BCLK1_P TPS125
AN8 AE6 S_TP_CK_SRC0_PCH_DN
[20] C_14M_MCH REFCLK14IN CLKOUT_PCIE0N AC6 S_TP_CK_SRC0_PCH_DP TPS78
C CLKOUT_PCIE0P TPS124 C
AA5
CLKOUT_PCIE1N W5 C_SRC1_PCH# [52]
CLKOUT_PCIE1P C_SRC1_PCH [52]
AB12
CLKOUT_PCIE2N AB14 C_PCIE_L1# [34]
C_XTAL_25M_OUT AJ5 CLOCK CLKOUT_PCIE2P C_PCIE_L1 [34]
C_XTAL_25M_IN AJ3 XTAL25_OUT AB9 S_TP_CK_SRC3_PCH_DN
RC107 1M XTAL25_IN CLKOUT_PCIE3N AB8 S_TP_CK_SRC3_PCH_DP TPS72
CLKOUT_PCIE3P TPS73
+/-1%
XC2 DON'T CHANGE TO 0402 Y9 S_TP_CK_SRC4_PCH_DN
1 2 CLKOUT_PCIE4N Y8 S_TP_CK_SRC4_PCH_DP TPS74
CLKOUT_PCIE4P TPS75
XTAL 25MHz AF3
CLKOUT_PCIE5N AG2 C_PCIEX1#_2 [59]
CLKOUT_PCIE5P C_PCIEX1_2 [59]
* CC36
27pF * CC37
27pF AB3 C_PCIEX1#_1
TPS76
CLKOUT_PCIE6N AA2 C_PCIEX1_1
CLKOUT_PCIE6P TPS77
50V, NPO, +/-5%
50V, NPO, +/-5%
**
AG8 C_PCIEX16#_1_R RS205 0
CLKOUT_PEG_A_N AG9 C_PCIEX16_1_R RS204 0 C_PCIEX16#_1 [38]
8/12 CLKOUT_PEG_A_P C_PCIEX16_1 [38]
AE12
CLKOUT_PEG_B_N AE11 C_PCIEX4#_1 [39]
CLKOUT_PEG_B_P C_PCIEX4_1 [39]
BD82Q67
B B
C_LPC_TPM
C_14M_TPM
C_14M_SIO
C_LPC_SIO
C_PCI_SB
+3V
*
*
RC108 10K S_FLEXBAY_HDR_CBL_DET# RC109 10K Dummy
S_FLEXBAY_HDR_CBL_DET# [24,61]
20091216 PCIECLKRQ1#/GPIO18 is
mobile chip only, RC110, RC111 and
signal net "S_PCIECLKREQ#1" * CC10
10pF * CC12
10pF * CC13
10pF * CC14
10pF * CC15
10pF
removed. +3V_S5 Dummy Dummy Dummy Dummy Dummy
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%

20100106: GPO_WLOM move to GPIO14
**
RC116 10K
S_INTRUD_CBL_DET# [24,31]
S_INTRUD_CBL_DET#
O_COM_SER2_DET#
RC117
** 10K Dummy
RC118 10K RC119 10K Dummy

O_COM_SER2_DET# [24,55]
******
A RC129 10K A
*****
[20,22] C_96M_PCH# C_14M_MCH

Pull-down for Integrated clock gen-11/25/09 RC120 10K
20100105: Dummy all pull-down resistors since [20,22] C_96M_PCH
RC130 10K
C_PCH_CSI# RC121 10K
use buffer thru mode RC131 10K
[20,22] C_DMI_PCH#
20100106: Reserved RC123,RC124; CRB 0.7 C_PCH_CSI RC122 10K
20100107: RC121,RC122 mount; PDG 0.8 RC132 10K Title
[20,22] C_DMI_PCH
C_DMI2_PCH# RC123 10K
[20,23] C_SATA_PCH#
RC133 10K PCH-8: Clock
C_DMI2_PCH RC124 10K
RC134 10K DWG NO Rev
[20,23] C_SATA_PCH
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+1P05V_PCH +1P05V_PCH
US1I
+1P05V_PCH AV24 AC24
AV26 VCCIO_1 VCCCORE_1 AC26
AY25 VCCIO_2 VCCCORE_2 AC28
VCCIO_3 VCCCORE_3 * CS11
* CS15
* CS16
* CS17
16V, X5R, +/-10%
16V, X5R, +/-10%
16V, X5R, +/-10%

CS12 CS13 CS14 AY27 AC30 1uF 1uF 10uF 10uF
AC20 VCCIO_4 VCCCORE_4 AC32
* 1uF
* 1uF
* 1uF
AE20 VCCSC_1
VCCSC_2
VCCCORE_5
VCCCORE_6
AE24
16V, X5R, +/-10%
16V, X5R, +/-10%
10V, X5R, +/-10%
10V, X5R, +/-10%
D AG41 AE28 D
AL40 VCCIO_7 VCCCORE_7 AE30
AN40 VCCIO_8 VCCCORE_8 AE32
VCCIO_9 VCCCORE_9 20100104- CS11 change to
AN41 AE34
AJ38 VCCIO_10 VCCCORE_10 AE36 1uF; follow CRB 0.8
20100104- CS13,CS14 change to VCCIO_11 VCCCORE_11
Y36 AG32
1uF; follow CRB 0.8 V36 VCCIO_12 VCCCORE_12 AG34
Y28 VCCIO_13 VCCCORE_13 AJ32
PLACE SOLDER SIDE VCCIO_14 VCCCORE_14
AE15 AJ34
AE17 VCCDIFFCLKN_1 VCCCORE_15 AJ36
20100104- Remove CS72 follow VCCDIFFCLKN_2 VCCCORE_16
AG15 AL32
CRB 0.8 AE40 VCCDIFFCLKN_3 VCCCORE_17 AL34
BA38 VCCIO_18 VCCCORE_18 AN32
+1P05V_PCH AG38 VCCIO_19 VCCCORE_19 AN34
AG40 VCCIO_20 VCCCORE_20 AR32
AA34 VCCIO_21 VCCCORE_21 AR34
AA36 VCCIO_22 VCCCORE_22
* CS79
1uF 20100104- Remove CS18 follow F20 VCCIO_23
16V, X5R, +/-10% F30 VCCIO_24
+1P05V_PCH CRB 0.8 +V_1.05_PCH_LR_10 V25 VCCIO_25 AE43
LS1 V27 VCCIO_26 TP15 AE50
*
*
RS138 0 +/-5% V31 VCCIO_27 TP16 BA36
10uH V33 VCCIO_28 TP17 AY36
VCCIO_29 TP18 Y14
Close to AL40 * CS19
10uF * CS20
1uF TP19 Y12 20100107: Remove test points
6.3V,X5R,+/-10% TP20 H31
TP21 J27
10V, X5R, +/-10% TP22 J25
TP23 L22
CS19 Dummy and CS20 change to 1uF-11/30 TP24
C 20100105: CS19 mounted and CS20 Dummy; J31 C
TP25 L27
PDG 0.8 TP26 L25
TP27 J22
20100107: CS20 Mount; PDG 0.8 TP28 C29
TP29 F28
+1P05V_VCCIO TP30 C26
TP31 B25
E41 TP32 E29
B41 VCCDMI_01 TP33 E27
VCCDMI_02 TP34 B27
* CS21
1uF
TP35
TP36
D25
BP1
16V, X5R, +/-10% POWER VSS_NCTF_14 TPS101
+1P05V_PCH
P22
+V_1.05_PCH_LR_10 TP1 L31
Y24 TP2 L33
Y26 VCCIO_30 TP3 M38
+1P05V_PCH Dummy for Cost down-11/23 Y30 VCCIO_31 TP4 L36
Y32 VCCIO_32 TP5 Y18
VCCIO_33 TP6
*
LS2 10uH VCCSATAPLL_L_10 Y34 Y17

Dummy CS22 CS23 V22 VCCIO_34 TP7 AB17
Y20 VCCIO_35 TP9 P25
Follow CRB move CS24,CS25
* 10uF
Dummy * 1uF
16V, X5R, +/-10% Y22 VCCIO_36
VCCIO_37
VSS_296
VSS_295
R25
10V, X5R, +/-10% Dummy AJ20 R36
between RS139 and LS3-11/30 VCCCLKDMI VSS_293 AL44
VSS_292 AL43
*
LS3 1uH VCCAPLLEXP_L_10 RS139 0 VSS_291 BM46

B
Dummy TP10 BA27 B
TP11 P36
* CS24
10uF * CS25
1uF 6.3V,X5R,+/-10% VSS_294
10V, X5R, +/-10%
CRB 0.7 LS3,CS24,CS25 is reserved and RS139 is

U56
+1P05V_PCH Dummy, need to tracking-11/30 VCCAPLLSATA Pin R25,R36,AL44,AL43,P36
change to VSS and connect to
VCCAPLLEXP_LR_10 B53
GND-11/27
Dummy for follow CRB-11/30
VCCAPLLEXP
*
RS140 0 VCCFDIPLL_R_10 C54

Dummy VCCFDIPLL
A19
VCCAPLLDMI2
AL5
VCCACLK
*
LS4 1uH RS141 0 VCCAPLLDMI2_LR_10

Dummy Dummy
Dummy for Cost down-11/23
20100106: CS27 change to
CS26
10uF * * CS27
1uF
9/12
1uF: PDG 0.8 10V, X5R, +/-10% Dummy
Dummy 6.3V,X5R,+/-10% BD82Q67
A 20100104- Remove CS28,CS30,CS31 follow A

*
RS142 0 VCCACLK_R_10
Dummy
CRB 0.8
Dummy for follow CRB-11/30
Title
PCH-9: Power 1
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+1P8V_SFR +V_NAND_IO
Coherent with GPIO28
RS2 0 +5V +3V +5V_S5 +3V_S5
Delet RS144,RS146,RS149 and 1.05V power source; follow CRB 0.7-11/30
A
US1J
* **
+REF5V AJ1 RS143 0 DS1 DS2
VCCVRM_1
VCCVRM_4
R2 RS145 0
+1P8V_SFR
+1P8V_SFR
*RS150 SD103AW *RS147 SD103AW
BF1 R54 10 +REF5V 10 Dummy +REF5V_SUS
+REF5V_SUS V5REF VCCVRM_3 R56 RS148 0 +1P8V_SFR
C
VCCVRM_2
+3V_S5 BT25 +V_NAND_IO
V5REF_SUS
D
AV28 T55 CS32 0.1uF Near T55
* CS33
1uF
* CS39
0.1uF
D
VCCSUSHDA VCCPNAND_1
*
T57 16V, X7R, +/-10%
VCCPNAND_2 16V, X5R, +/-10% 16V, X7R, +/-10%
* CS34
0.1uF 20100106- Dummy
16V, X7R, +/-10%
+3V
CS35,CS44,CS45; follow
+3V +3V CRB 0.8
BD17 CS35 0.1uF
VCC3P3_3
* * *
AF57 BD20 16V, X7R, +/-10% +VCCRTC
VCC3P3_1 VCC3P3_4
CS46
0.1uF * BC17
VCC3P3_2
CS36
Dummy
0.1uF Near AL38
16V, X7R, +/-10% 16V, X7R, +/-10% Near BU42
CS37
0.1uF * * CS38
0.1uF VCC3P3_5
AL38 CS40 0.1uF Near A12
* CS41
1uF * CS42
0.1uF
6.3V,X5R,+/-10%
Close to AF57 16V, X7R, +/-10% AN38 16V, X7R, +/-10%
16V, X7R, +/-10% VCC3P3_6 16V, X7R, +/-10%
20100104- Change to AU22
VCC3P3_7 A12
0.1uF; follow CRB 0.8 Close to BC17 VCC3P3_8 AU20 CS44 0.1uF
VCC3P3_9
*
16V, X7R, +/-10%
Dummy for Cost down-11/23 Dummy
AV20
VCC3P3_10 CS45 0.1uF
Delet LS5,RS151,CS46,CS47; follow CRB 0.7-11/30
*
16V, X7R, +/-10%
Dummy
+3V Near AU20 +3V
C * CS73
1uF * CS75
1uF
+1P8V_SFR
C
16V, X5R, +/-10% 16V, X5R, +/-10%
Dummy Dummy
20100104- Add CS78,CS80 and CS76,CS77
change to 0403; follow CRB 0.8
* CS48
1uF
16V, X5R, +/-10%
Dummy
+1P05V_ME 20100104- CS73,CS75 change to
Near AJ24,AN22
POWER
1uF; follow CRB 0.8
Near AV30 20100104- Remove CS49,CS50 follow
U31
* CS71
1uF * CS80
10uF * CS78
1uF * CS77
1uF * CS76
1uF
+1P05V_ME
VCCSUS3P3_1
+3V_S5 20100104- CS56 change to
2.2uF; follow CRB 0.8
CRB 0.8
6.3V, X5R, +/-20%
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy AU32 AV30

VCCASW_1 VCCSUS3P3_2
16V, X5R, +/-10%
AV36 AV32 CS51 NEAR U31

AU34 VCCASW_2 VCCSUS3P3_3 AY31
AG24 VCCASW_3 VCCSUS3P3_4 AY33 * CS51
0.1uF * CS56
2.2uF
CS56 NEAR AV30,AT40
AG26 VCCASW_4 VCCSUS3P3_5 BJ36 25V, X7R, +/-10% 6.3V, Y5V, +80%/-20%
+3V AG28 VCCASW_5
VCCASW_6
VCCSUS3P3_6
VCCSUS3P3_7
BK36 VBAT
AJ24 BM36
AJ26 VCCASW_7 VCCSUS3P3_8 AT40 +VCCRTC_SIO +3V_DUAL
L<100 MILS AJ28 VCCASW_8 VCCSUS3P3_9 AU38 CS52 0.1uF QS4 QS5 +VCCRTC
*
FBS1 RS152 AL24 VCCASW_9 VCCSUS3P3_10 BT35 16V, X7R, +/-10% BAT54C BAT54C
*
S_VCCADAC_LR_10 AL28 VCCASW_10 VCCSUS3P3_11 1 1

1
VCCASW_11
Near BT35
FB 600 Ohm AN22 3 3
VCCASW_12
20100106:- FBS1 * CS53
* CS54
* CS55 * ECS3 AN24
AN26 VCCASW_13
2 2 CS57
change to FB:
2.2uF 10uF 0.1uF 220uF
AN28 VCCASW_14 * 1uF
*RS153
6.3V, Y5V, +80%/-20%
10V, X5R, +/-10%
16V, X7R, +/-10%
16V, X5R, +/-10%

16V, +/-20% +1P05V_VCCIO 20100104- Remove 20K
B
PDG 0.8 AR24 VCCASW_15
VCCASW_16 CS74 follow CRB
BATTERY_1 *RS154 B
AR26 CS58 4.7uF 1K
***
AR28 VCCASW_17 6.3V, X5R, +/-10% 0.8 S_RTCRST#
AR30 VCCASW_18 S_RTCRST# [24,31]
CS59 0.1uF LI TH IU M BA TT
+
AR36 VCCASW_19
+3V_DUAL AR38 VCCASW_20
VCCASW_21
CS60
16V, X7R, +/-10%
0.1uF BATTERY * CS61
1uF
AU30 16V, X7R, +/-10% Battery Battery Holder 10V, X5R, +/-10%
AU36 VCCASW_22
Near D55
-
VCCASW_23 D55
* CS70
0.1uF
+3V_DUAL
AV40 V_PROC_IO_1 B56
16V, X7R, +/-10% VCCDSW3_3 V_PROC_IO_NCTF_1 +3V_EPW +VCCRTC
+1P05V_PCH Close to AV40 AN52
AT1 VCCSPI BU42
VCCADAC VCCRTC BT56 CS62 0.1uF 16V, X7R, +/-10%
DCPRTC_NCTF Near BR54
*
LS6 BR54
*
RS155 0 S_VCCADPLLA_LR_10 AB1 DCPRTC AA32

VCCADPLLA DCPSUS_1 AT41 TPS117
10uH
DCPSUS_2 TPS118 Change to 1uF; follow CRB 0.7-12/03
ECS1 A39
CS64
* CS63 0.1uF 16V, X7R, +/-10% 20100104: Change to 0.1uF; follow PDG 0.8
**
DCPSUS_3
RS156
0 ** 220uF 1uF
16V, +/-20%16V, X5R, +/-10%
AC2
VCCADPLLB DCPSUSBYP
DCPSST
AV41
BA46 TPS119
CS65 0.1uF 16V, X7R, +/-10%
Dummy
10/12
LS7 BD82Q67
*
RS157 0 S_VCCADPLLB_LR_10
10uH
*
ECS2
220uF
CS66
1uF * +3V_EPW
16V, +/-20%16V, X5R, +/-10%
A * CS29
1uF
A
6.3V,X5R,+/-10%
Near AN52
Title
PCH-10: Power 2
20100104: CS29 change to 1uF; DWG NO Rev
follow PDG 0.8 A00
Gold Coast_MT/DT
5 4 3 2 1
A
B
C
D
8
7
8
7
US1_1
M6
Heatsink
M8 VSS_246 AE56 BB52
M9 VSS_247 BR36 VSS_1 VSS_122 BB6
VSS_248 VSS_2 VSS_123
5
5
N4 C12 BC14
N54 VSS_249 AY22 VSS_3 VSS_124 BC15
R11 VSS_250 A26 VSS_4 VSS_125 BC20
3
4
PCH Heatsink
R15 VSS_251 A29 VSS_5 VSS_126 BC27

R17 VSS_252 A42 VSS_6 VSS_127 BC31
3
4
R22 VSS_253 A49 VSS_7 VSS_128 BC36

R4 VSS_254 A9 VSS_8 VSS_129 BC38
R41 VSS_255 AA20 VSS_9 VSS_130 BC47
R43 VSS_256 AA22 VSS_10 VSS_131 BC9
VSS_257 AA24 VSS_11 VSS_132 BD25
AA26 VSS_12 VSS_133 BD33
TPS110 A4 AA28 VSS_13 VSS_134 BF12
A6 VSS_NCTF_1 AA30 VSS_14 VSS_135 BF20
CLIPS2
CLIPS1
Clip_2P
Clip_2P
2
1
2
1
B2 VSS_NCTF_2 U15 AA38 VSS_15 VSS_136 BF25

BM1 VSS_NCTF_3 VSS_263 U17 AB11 VSS_16 VSS_137 BF33
TPS111 BM57 VSS_NCTF_4 VSS_264 U20 AB15 VSS_17 VSS_138 BF41
BP57 VSS_NCTF_5 VSS_265 U22 AB40 VSS_18 VSS_139 BF43
BT2 VSS_NCTF_6 VSS_266 AB41 VSS_19 VSS_140 BF46
BU4 VSS_NCTF_7 AB43 VSS_20 VSS_141 BF52
BU52 VSS_NCTF_8 U25 AB47 VSS_21 VSS_142 BF6
BU54 VSS_NCTF_9 VSS_267 U27 AB52 VSS_22 VSS_143 BG22
BU6 VSS_NCTF_10 VSS_268 U33 AB57 VSS_23 VSS_144 BG25
D1 VSS_NCTF_11 VSS_269 U36 AB6 VSS_24 VSS_145 BG27
VSS_NCTF_12 VSS_270 VSS_25 VSS_146
20091209: CRB0.7 pin

F1 U38 AC22 BG31
VSS_NCTF_13 VSS_271 R46 AC34 VSS_26 VSS_147 BG33
A4,BM57 are test points

VSS_272 U53 AC36 VSS_27 VSS_148 BG36
AU2 VSS_273 V20 AC38 VSS_28 VSS_149 BG38
VSSADAC VSS_274 V38 AC4 VSS_29 VSS_150 BH52
VSS_275 V6 AC54 VSS_30 VSS_151 BH6
VSS_276 W1 AE14 VSS_31 VSS_152 BJ1
S_GPI_PCH_HS_DET#
VSS_277 W55 AE18 VSS_32 VSS_153 BJ15

VSS_278 W57 AE22 VSS_33 VSS_154 BK20
GND VSS_279 VSS_34 VSS_155
[23]
Y11 AE26 BK41
4
4
VSS_280 Y15 AE38 VSS_35 VSS_156 BK52

VSS_281 Y38 AE4 VSS_36 VSS_157 BK6
U41 VSS_282 Y40 AE47 VSS_37 VSS_158 BM10
U47 VSS_258 VSS_283 R49 AE8 VSS_38 VSS_159 BM12
T52 VSS_259 VSS_284 Y43 AE9 VSS_39 VSS_160 BM16
T6 VSS_260 VSS_285 Y46 AF52 VSS_40 VSS_161 BM22
U11 VSS_261 VSS_286 Y47 AF6 VSS_41 VSS_162 BM23
VSS_262 VSS_287 Y49 AG11 VSS_42 VSS_163 BM26
VSS_288 Y52 AG14 VSS_43 VSS_164 BM28
VSS_289 AG20 VSS_44 VSS_165 BM32
AG22 VSS_45 VSS_166 BM40
Y6 AG30 VSS_46 VSS_167 BM42
VSS_290 AG36 VSS_47 VSS_168 BM48
AG43 VSS_48 VSS_169 BM5
12/12 AG44 VSS_49 VSS_170 BN31
AG46 VSS_50 VSS_171 BN47
AG5 VSS_51 VSS_172 BN6
VSS_52 VSS_173
US1L
AG50 BP3
AG53 VSS_53 VSS_174 BP33
BD82Q67
AH52 VSS_54 VSS_175 BP35
AH6 VSS_55 VSS_176 BR22
AJ22 VSS_56 GND VSS_177 BR52
AJ30 VSS_57 VSS_178 BU19
AJ57 VSS_58 VSS_179 BU26
Pin Y6 connect to GND-11/27

AK52 VSS_59 VSS_180 BU29
AK6 VSS_60 VSS_181 BU36
AL11 VSS_61 VSS_182 BU39
AL18 VSS_62 VSS_183 C19
AL20 VSS_63 VSS_184 C32
AL22 VSS_64 VSS_185 C39
AL26 VSS_65 VSS_186 C4
AL30 VSS_66 VSS_187 D15
AL36 VSS_67 VSS_188 D23
3
3
AL41 VSS_68 VSS_189 D3

AL46 VSS_69 VSS_190 D35
AL47 VSS_70 VSS_191 D43
AM3 VSS_71 VSS_192 D45
AM52 VSS_72 VSS_193 E19
AM57 VSS_73 VSS_194 E39
AN11 VSS_74 VSS_195 E6
AN12 VSS_75 VSS_196 E9
AN15 VSS_76 VSS_197 F10
AN17 VSS_77 VSS_198 F12
AN18 VSS_78 VSS_199 F16
AN20 VSS_79 VSS_200 F22
AN30 VSS_80 VSS_201 F26
AN36 VSS_81 VSS_202 F32
AN4 VSS_82 VSS_203 F33
AN43 VSS_83 VSS_204 F35
AN47 VSS_84 VSS_205 F36
AN54 VSS_85 VSS_206 F40
AN9 VSS_86 VSS_207 F42
AR20 VSS_87 VSS_208 F46
AR22 VSS_88 VSS_209 F48
AR52 VSS_89 VSS_210 F50
AR6 VSS_90 VSS_211 E54
AT15 VSS_91 VSS_212 F8
AT18 VSS_92 VSS_213 G54
AT43 VSS_93 VSS_214 H15
AT47 VSS_94 VSS_215 H20
AT52 VSS_95 VSS_216 H22
AT6 VSS_96 VSS_217 H25
AT8 VSS_97 VSS_218 H27
AU24 VSS_98 VSS_219 H33
AU26 VSS_99 VSS_220 H6
VSS_100 VSS_221
2
2
AU28 J1
AU5 VSS_101 VSS_222 J33
AV12 VSS_102 VSS_223 J46
AV18 VSS_103 VSS_224 J48
AV22 VSS_104 VSS_225 J5
AV34 VSS_105 VSS_226 J53
AV38 VSS_106 VSS_227 K52
AV47 VSS_107 VSS_228 K6
AV6 VSS_108 VSS_229 K9
AW57 VSS_109 VSS_230 L12
AY38 VSS_110 VSS_231 L17
AY6 VSS_111 VSS_232 L38
B23 VSS_112 VSS_233 L41
BA11 VSS_113 VSS_234 L43
BA12 VSS_114 VSS_235 M20
Date:
BA31 VSS_115 VSS_236 M22

Title
BA41 VSS_116 VSS_237 M25

BA44 VSS_117 VSS_238 M27
DWG NO
BA49 VSS_118 VSS_239 M31

BB1 VSS_119 VSS_240 M33
BB3 VSS_120 VSS_241 M36
VSS_121 VSS_242 M46
VSS_243 M52
VSS_244 M57
VSS_245
11/12
US1K
BD82Q67
1
1
Sheet
PCH-11: GND
30
Gold Coast_MT/DT
of
Rev
70
A00
A
B
C
D
5 4 3 2 1
Clear Password CLR_CMOS Chassis Intruder

+3V_DUAL
1-2: NORMAL +VCCRTC

Header_1X2
EMPTY: CLEAR PASSWORD *RS159
8.2K
[24,29] S_RTCRST#
2
+/-5% 1
D
1
PSWD *RS158 D
1M INTRUDER
[24] S_PSWD_CLR 2
RTCRST Jumper Type 3
PSWD_JUMPER(1-2) * 4.7K
Dummy Default
[24,27] S_INTRUD_CBL_DET# 2 3
*
RS166 RS160 10K 1 2
Header_1X2 [24] S_INTRUDER# 1
Pop CLR_CMOS
* CS67
0.1uF
Header_1X3
Jumper_2P_Blu 16V, X7R, +/-10%
SERVICE_MODE
BEEP
+3V_S5 +3V_S5
C C
*RS206
1K
*RS161
+/-5% 1K
+/-5% +5V
E
QS6 RNS1 BEEP

[24] S_MFG_MODE_OR
RS162 10K B MMBT3906
SERVICE_MODE
*1 2
+
*
1 3 4
BUZZER
C
2 5 6 -
[24] A_Z_SDOUT_R 7 8
100 Ohm Buzzer
Header_1X2
C
**
B
[24] S_SPKR_OUT
RS164 1K +/-1% QS7
MMBT3904-7-F * CS68
1uF
RS165 1K +/-1% 25V, X5R, +/-10%
E
[32,33] O_SPEAKER
B
SKU ID Chassis ID BOARD ID B
+3V +3V_S5 +3V

+3V
* RS95 * RS96 * RS97

RS106 * * RS40 * RS41
10K 10K 10K
10K 10K 10K Dummy Dummy Dummy
@Z @N Dummy
[23] S_GPI_BRD_REV2
[23] S_GPI_SKU2
Rev2 Rev1 Rev0 Type [24] S_GPI_BRD_REV1
[24] S_GPI_SKU1
+3V
check : need to update table 0 0 0 Default [23] S_GPI_BRD_REV0
[24] S_GPI_SKU0
* * *
0 0 1 Reserved RS111
220
* * *
RS42 RS43
RS100 RS98 RS99 20100106: change 1K 10K
220 220 220
0 1 0 Reserved +/-5%
+/-5% +/-5% +/-5%
ID2 ID1 ID0 Type
* *
RS44 *
RS45 RS46
0 1 1 Reserved
to 1k since have
@S,J,N @S,Z,J 10K 10K 10K internal pull-up
Dummy Dummy Dummy
1 0 0 Reserved 10k
1 0 1 SFF [23] S_GPI_CHASSIS_ID0
1 0 1 Reserved
[23] S_GPI_CHASSIS_ID1
SKU ID 1 1 0 Reserved
1 0 0 Tambor [23] S_GPI_CHASSIS_ID2
1 1 1 Reserved
A A
SKU1 SKU0 Type
0 0 TPM
0 0 0 MT/DT * *
RS49 *
RS50 RS51
1K 1K 10K
0 1 TCM Title
0 1 1 USFF
1 0 non TPM/TCM PCH MISC Conn/BUZ/ID
1 1 Reserved DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+3V_DUAL
Delet RO2; SMSC suggestion-12/08/09 PWRGD_3V
+VCCRTC_SIO
Reserved for pin 24,34,57,79,106,122
* * **
S_SMBDATA_PCI S_SMLINK1_DATA_R
RO4 0 +/-5%
Dummy +3V Delet RO6; SMSC
CO1
100pF * *RO3
8.2K
S_SMBCLK_PCI S_SMLINK1_CLK_R For Swap SMBUS used
RO5 0 +/-5%
Dummy +3V_DUAL *RO8
2MOhm
* CO10
CO2
0.1uF
CO3
0.1uF
CO4
0.1uF
CO5
0.1uF
CO6
0.1uF
CO7
0.1uF
CO8
0.1uF
suggestion-12/08/09 50V, NPO, +/-5% +/-5%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

S_SMLINK1_DATA RO7 0 +/-5% S_SMBDATA_PCI_R close to Pin 6 +3V_DUAL +/-5% 1uF
Dummy close to Pin 47 16V, X5R, +/-10%
S_SMLINK1_CLK RO9 0 +/-5% S_SMBCLK_PCI_R +3V_DUAL 20100107: change to
Dummy CO9
0.1uF 0.1uF +3V_DUAL for layout
16V, X7R, +/-10% CO11
D
* D
122
106
79
57
34
24
16V, X7R, +/-10%
47
UO1 RO107
23
6
Add SMBus 10K
+/-1%
VCC
VBAT
VTR_6
VTR_5
VTR_4
VTR_3
VTR_2
VTR_1
HVTR
T_ESATA_DET# 78 switch
GP42 / DRVDEN0
circuit-11/25/09
76 80 20100105: Mount
4
[33] O_INDEX# 75 INDEX# SLCT 81 O_SLCT [62]
MTR0# PE O_PE [62]
**
S_SMBDATA_PCI RO15 0 +/-5% S_SMBDATA_PCI_R 74 82 SMBus control QO16
73 GP40 / SMBDAT1 BUSY 83 O_BUSY [62] +12V
DS0# ACK# O_ACK# [62] circuit by
Floppy
S_SMBCLK_PCI RO16 0 +/-5% S_SMBCLK_PCI_R 72 84 O_PD7
71 GP36 / SMBCLK1 PD7 85 O_PD6 B_ATX_PWROK MMDT5551
70 DIR# PD6 86 O_PD5
* RO106
3
68 STEP# PD5 87 O_PD4
WDATA# PD4
Parallel Port
67 88 O_PD3 8.2K
66 WGATE# PD3 / TMS 89 O_PD2 S_SMB_SW
[33] O_TRK0# 65 TRK0# SCH5544-NS PD2 / TDO 90 O_PD1 RO108 10K
[33] O_WPT# 64 WRTPRT# PD1 / TDI 91 [63,70] B_ATX_PWROK
O_PD0
*
[33] O_RDATA# 63 RDATA# PD0 / TCK 93 O_PD[7..0]
62 HDSEL# SLCTIN# 94 O_SLIN# [62] O_PD[7..0] [62]
[33] O_DSKCHG# DSKCHG# INIT# 95 O_INIT# [62]
ERROR# 96 O_ERR# [62]
9 ALF# 97 O_AFD# [62] S_SMB_SW
[27] C_14M_SIO 10 CLOCKI STROBE# O_STB# [62]
QO4
G
[24,46,53] F_LAD0 11 LAD0 2N7002
[24,46,53] F_LAD1 12 LAD1 98
[24,46,53] F_LAD2 13 LAD2 DCD1# / GP43 / MCDAT 99 O_DCD1#_R [50] S D
[24,46,53] F_LAD3 LAD3 DSR1# / GP044 / MCCLK O_DSR1#_R [50] [15,16,17,18,20,52] S_SMBCLK_MAIN S_SMBCLK_PCI [13,16,18,24,38,39,58,59]
Serial Port 1
LPC
14 100
[24,46,53] F_FRAME# 15 LFRAME# RXD1 / GP45 101 O_RXD1_R [50]
[24] F_LDRQ# LDRQ# RTS1# / GP46 O_RTS1#_R [50]
C 16 102 S_SMB_SW C
[9,24,34,46,52,53] S_PLTRST# 17 LRESET# / GP74 GP47 / TXD1 103 O_TXD1_R [50]
QO5
G
18 SPI_DO / GP04 CTS1# / GP50 104 O_CTS1#_R [50]
2N7002
[27] C_LPC_SIO 1 PCICLK DTR1# [TEST_EN] /GP51 105 O_DTR1#_R [33,50]
[23,46] F_SERIRQ# 77 SER_IRQ RI1# / GP52 O_RI1#_R [50] S D
[24] O_IO_PME# GP41 / IO_PME# [15,16,17,18,20,52] S_SMBDATA_MAIN S_SMBDATA_PCI [13,16,18,24,38,39,58,59]
107
GP53 / DCD2# 108 O_DCD2#_R [55]
GP54 / DSR2# O_DSR2#_R [55]
Serial Port 2
109
O_RXD2_R [55]
**
GP55 / RXD2
SMB SPI
RO31 0 +/-5% S_SMLINK1_DATA_R 27 110
[24] S_SMLINK1_DATA 28 SMBDAT2 / GP10 GP56 / RTS2# 111 O_RTS2#_R [55]
RO32 0 +/-5% S_SMLINK1_CLK_R +3V
[24] S_SMLINK1_CLK SPI_DI 29 SMBCLK2 / GP11 GP57 / TXD2 112 O_TXD2_R [33,55] +3V_DUAL
30 SPI_DI / GP12 GP60 / CTS2# 113 O_CTS2#_R [55]
SPI_CK / GP13 GP61 / DTR2# 114 O_DTR2#_R [33,55]
Delet RO33,RO34; SMSC suggestion-12/08/09 GP62 / RI2# O_RI2#_R [55] +12V_CPU
*RO12 *RO19
4 30K
[56] O_DIAG_LED3# GP00 / DIAG_LED3#
5 30K +/-1%
[56] O_DIAG_LED1# GP01 / DIAG_LED1#
7 121 +/-1%
*RO23
C
[56] O_DIAG_LED2# GP02 / DIAG_LED2# GP64 / A20M O_GA20 [23] O_RTS2#_R [55]
8 120
[56] O_DIAG_LED4# GP03 / DIAG_LED4# GP63 / KBDRST# O_KB_RST# [23]
36 118 8.2K B QO2
KB / MS
[24,52,53,56] O_PWRBTN#IN PWRBTN# / GP15 MDAT 117 O_MS_DATA [49] MMBT3904-7-F
+/-5%
MCLK
*
RO36 0 +/-5% 21 116 O_MS_CLK [49]
C
[24] S_SUSCLK O_KB_DATA [49]
E
25 CLK32 KDAT 115
[56] O_YELLOW# 26 YELLOW# / GP06 KCLK O_KB_CLK [49] B QO3 +3V_DUAL
[56] O_GREEN# GREEN# / GP07 MMBT3904-7-F
Miscellaneous
52
* * ** * * * *
[56] O_FP_CBL_DET# 53 GP25 / BC_DAT
X_PLTRST_PCIE_SLOT#_R RO17 8.2K +/-5% S_SMLINK1_DATA_R
*RO28
E
54 PCI_RST_SYS# / GP26 Dummy
[9] H_RESET# 55 PCI_RST_SLOTS# / GP27 S_SMLINK1_CLK_R
698 RO10 8.2K +/-5%
[63,70] O_PSON# 56 PS_ON# / GP30 39 +/-1%
[37] O_AUD_PCSPKR_DET# Dummy
B 58 GP31 / BC_INT# TACH1 / GP17 40 O_SEN_CPUFAN [48] B
SPI_CS# / GP32 TACH2 / GP20 O_SEN_CHAFAN
20100111:
[48]
RO11 8.2K +/-5% S_SMBDATA_PCI_R
59 41 Dummy
[24,52] PWRGD_3V 60 PWR_GOOD_3V / GP33 TACH3 / GP21 49 Remove PSU S_SMBCLK_PCI_R
RO18 8.2K +/-5%
[24] O_RSMRST# 123 RSMRST# / GP34 GP22 / PWM1 50 O_CPUFAN_PWM [48] PWM control
Net change to [20,24,64,66,69,70] S_SLP_S3# Dummy
HW Monitor
124 SLP_S3# / GP65 GP23 / PWM2 51 O_CHAFAN_PWM [48] O_AUD_PCSPKR_DET#

H_RESET#-12/28/09 [24,65,70] S_SLP_S4# SLP_S4_S5# / GP66 GP24 / PWM3
DO1 change to RO109; SMSC RO20 8.2K +/-5%
125 RO21 8.2K +/-5% O_BC_CLK
[63,70] B_ATX_PWROK PWRGD_PS / GP67 suggestion-12/08/09
TRST# 126 22 O_PECI_REQ# RO109 1 2
127 TRST# GP05 / PECI_REQUEST# 48 S_PECI_REQ# [24] RO22 8.2K +/-5% SPI_DI
Dummy
[31,33] O_SPEAKER 128 GP70 / PWM4 V_IN O_CPUFAN_ID [48]
[24,65,66] S_SLP_M# GP71 / IO_SMI# 43 RO38 100K+/-5% T_ESATA_DET#
+1P05V_VCCIO REMOTE1+ 44 O_TR_CPU+ [47] Dummy
33 REMOTE1- 45 O_TR_CPU- [47]
GP35 / BC_CLK
*
[33] O_GP73_PU PECI_AVAIL / LVSMBDAT1 / GP73 REMOTE2+ O_TR_MB+ [47]

PECI
RO35 33+/-5% H_PECI_R 32 46 +3V

[9,23] H_PECI 31 PECI / LVSMBCLK1 / GP72 REMOTE2- O_TR_MB- [47]
****
PECI VREF Delet RO36,RO37 and connect Tmin_Shift to PCH directly; SMSC suggestion-12/08/09 RO24 4.7K +/-5% S_SMBDATA_MAIN
CO12 Reserved RO35; SMSC suggestion-12/08/09 35 RO25 4.7K +/-5% S_SMBCLK_MAIN
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
GP14 TMIN_SHIFT [23]

HVSS
AVSS
38
CAP1
0.1uF RO26 30K +/-1% O_TXD1_R

PROCHOT# / PWM5 / GP16 H_PROCHOT# [9,67] TMIN_SHIFT
16V, X7R, +/-10% RO27 8.2K +/-5%
+3V_S5
2
3
69
19
37
61
92
42
20
119
+3V_DUAL
**
O_BC_CLK RO13 4.7K +/-5% S_SMBDATA_PCI
RO14 4.7K +/-5% S_SMBCLK_PCI
* CO13 O_TR_MB+
5
4.7uF UO4
VCC
1
A OE# 22 Ohm * CO14 50V, NPO, +/-5%
100pF A
*
4 RO41 O_TR_MB-
X_PLTRST_PCIE_SLOT# [38,39,59]
Place Near Y close to 5544 pin45,46
+12V_CPU S_SLP_S3# X_PLTRST_PCIE_SLOT#_R 2 +/-1%
TRST#
SIO pin.123
A
GND O_TR_CPU+
Title
CO15
*RO39 * CO16 74LVC1G125GW
3
0.1uF 1K 1nF
Dummy +/-5% 50V, X7R, +/-10%
* CO17 50V, NPO, +/-5% SIO-SCH5544-1
16V, X7R, +/-10% Dummy 100pF
O_TR_CPU- DWG NO Rev
close to 5544 pin43,44 A00
Gold Coast_MT/DT
*
RO40 0 +/-5%
Dummy
5 4 3 2 1
SCH5544 Decoupling 5 4 3 2 1
+3V +3V
+3V_DUAL +VCCRTC_SIO +3V
*RO43
30K *RO44
30K
+/-1% +/-1%
* CO18
0.1uF
* CO19
0.1uF
* CO20
0.1uF
* CO21
0.1uF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% O_TXD2_R O_DTR2#_R
D
+1P05V_VCCIO +3V
+3V_DUAL +3V_DUAL
* RO45 +5V
8.25K RO46 RO48
+/-1% * 8.2K * 8.2K
+/-5% +/-5%
[32,55] O_TXD2_R Dummy 20100107: Remove RO47, RO53 and Dummy
+3V
* O_RTS1#_R strapping, SMSC
6
4
RO49 RNO1
*RO50
2
4
6
8
QO6 7.15K O_SPEAKER [31,32] suggestion O_DTR1#_R [32,50] 1K
1K
RO51 MMDT5551 +/-1% +/-5%
* +/-5%
* 13
5
7
2KOhm
+/-1% RO52 RO54
* 8.25K * 30K
O_INDEX# [32]
1
O_TXD2_R +/-1% +/-1%
*RO55 O_DSKCHG# [32]

33KOhm +3V_EPW
O_TRK0# [32]
+/-1%
O_WPT# [32]
SPEAKER DTR1#
C Diag_En Flash_en
O_RDATA# [32]
+1P05V_PCH +3V
PULL
Disable Flash Enable
HIGH
* RO56
8.25K
+/-1%
PULL
O_TXD2_R Enable Parallel
LOW
Enable
* SIO STRAPING
6
RO57
QO7 6.8K
+1P05V_ME +/-1%
MMDT5551
1
O_TXD2_R
+1P5V_SM +3V
20100104: Removed useless dummied
* RO58
components, and only left O_PECI_READY pull-up
8.25K
+/-1%
O_TXD2_R
+1P05V_VCCIO
*
6
+3V RO61
QO9 10K
+/-1% * RO60
1K
* RO62 MMDT5551
30K
1
+/-1%
O_GP73_PU [32]
O_DTR2#_R [32,55]
[20,24,52,64,67] P_VR_READY
A 5544 PRE-POST DIAG PG GENERATION
Title
SIO-SCH5544-2 (MISC)
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+3V_LAN
20091216 Intel 82579 schematic check list 0.5:

Change net name from CLK_REQ_N to S_FLEXBAY_HDR_CBL_DET#
*RL1
D 10K UL1 D
20100105: Remove RL2 and S_FLEXBAY_HDR_CBL_DET#
48 13
connection since useless; PDG 0.8 36 CLK_REQ_N MDI_PLUS_0 14 L_MDI_0+ [35]
[9,24,32,46,52,53] S_PLTRST# PE_RST_N MDI_MINUS_0 L_MDI_0- [35]
near the PCIe transmitter. 44 17
[27] C_PCIE_L1 45 PE_CLKP MDI_PLUS_1 18 L_MDI_1+ [35]
[27] C_PCIE_L1# PE_CLKN MDI_MINUS_1 L_MDI_1- [35]
CL1 0.1uF
*** *
[22] X_L1X1_RXP
MDI
X_L1X1_RXP_C 38 20
PCIE
16V, X7R, +/-10%
CL3 0.1uF X_L1X1_RXN_C 39 PETP MDI_PLUS_2 21 L_MDI_2+ [35] +3V_LAN
[22] X_L1X1_RXN 16V, X7R, +/-10% PETN MDI_MINUS_2 L_MDI_2- [35]
CL2 0.1uF X_L1X1_TXP_C 41 23
[22] X_L1X1_TXP X_L1X1_TXN_C 42 PERP MDI_PLUS_3 24 L_MDI_3+ [35]
16V, X7R, +/-10%
CL4 0.1uF PERN MDI_MINUS_3 L_MDI_3- [35]
[22] X_L1X1_TXN 16V, X7R, +/-10% *RL4 *RL5
6 3.3K 3.3K
28 RSVD_NC
[24] S_SMLINK0_CLK SMB_CLK
SMBUS
31 1
[24] S_SMLINK0_DATA SMB_DATA RSVD_1/VCCP3P3_1 2
RSVD_2/VCCP3P3_2 5
VDD3P3_IN +3V_LAN Place near pin
L_LAN_DISABLE_R_# 3
LAN_DISABLE_N 4 VDD3P3
VDD3P3_OUT
26 15
[35] L_ACTLEDN
[35] L_LINK100#
27 LED0 VDD3P3_1 19 * CL5
1uF * CL6
1uF 6.3V,X5R,+/-10%
LED
25 LED1 VDD3P3_2 29 Dummy
[35] L_LINK10# LED2 VDD3P3_3 6.3V,X5R,+/-10%
ALWAYS DUMMY 47
+3V_LAN
*
+3V_LAN RL6 10K 32 VDD1P0_7 46 +1P05V_PCH
C Dummy 34 JTAG_TDI VDD1P0_8 37 C
**
TPL1 JTAG_TDO VDD1P0_9
JTAG
RL7 10K Dummy 33 +3V_LAN
35 JTAG_TMS 43
20091216 CRB0.7 :Connect a series CL24 Dummy
JTAG_TCK VDD1P0_1
(10 pF) capacitor to XTAL_OUT (pin 9). RL8 10K Place close
11
*
Dummy RL9
RL15 0 9
10 XTAL_OUT
VDD1P0_2
40
to PHY
0 *RL10
+/-5% 10K
XTAL_IN VDD1P0_3 22
XL1 less than 325 mils VDD1P0_4
Dummy
1 2 16
*
VDD1P0_5 8 VDD1P0 RL11 0 L_LAN_DISABLE_R_#
*
30 VDD1P0_6 [24] L_LAN_DISABLE#
XTAL 25MHz RL12 1K L_LAN_TESTEN
TEST_ENABLE LL1
*
7
* CL7
* CL8 L_LAN_1P0_CTRL 4.7uH
*RL14
*
33pF 33pF RL13 3.01K 12 CTRL_1P0
+/-1%
RBIAS 49 10K
VSS_EPAD
50V, NPO, +/-10%
50V, NPO, +/-10%
82579 * CL9
22uF * CL10
0.1uF
Dummy
16V, X7R, +/-10%

Net VDD1P0 and 6.3V,X5R,+/-20%
L1_LAN_1P0_CTRL
keep short and wide 20100107: Dummy RL9 and
Mount LL1; CRB 0.7
B B
Close to PIN5 (VDD)
+3V_LAN 20091216 follow CRB0.7 and 82579 cheklist: does not require
any MDI termination.(delete => RL15, RL16, RL17, RL18, RL19,
RL20, RL21, RL22, CL11, CL12, CL13, CL14)
* CL24
10uF * CL15
22uF * CL16
0.1uF
10V, X5R, +/-10% 16V, X7R, +/-10%
Dummy 6.3V,X5R,+/-20%
A A
Title
DWG NO
LAN:Intel Lewisvillies Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
LAN CONNECTOR VCT

1uF should be closed to the
Connector -10/01/09-Sherlock
+5V_DUAL_USBKB USB_PWR0_F_50
*
FU1 1 * 2 Fuse 2A
* CL17
1uF
RU1 10K
+/-1% 1
U_USB_OC_R_#0 [22]
25V, X5R, +/-10% * ECU1
470uF
* CU7
0.1uF RU2
+3V_LAN 6.3V, +/-20% 16V, X7R, +/-10% 15K
+/-1%
2
D
* CL18
0.1uF D
* CL19
0.1uF
16V, X7R, +/-10%
NIC_USB
16V, X7R, +/-10% LU1
U_USB0N_R 1 4
U_USB0N [22]
USB_PWR0_F_50
28 U_USB0P_R 2 3
14 29 U_USB0P [22]
GRN_LED
ORG_LED
30 Common Choke 90 Ohm
31
USB-2
USB-1
**
RL23 150 +/ -1% 13
[34] L_LINK10#
**
RL24 150 +/ -1% 15 RU3 0
[34] L_LINK100#
16 Dummy
6 20 RU4 0
2
CL20
* * CL21
[34] L_MDI_0+ 3 17
Dummy
RJ45-MJ2
470pF 470pF U_USB1N_R
[34] L_MDI_0- 4 21 U_USB0N_R
50V, X7R, +/-10% 50V, X7R, +/-10%
[34] L_MDI_1+ 5 LU2
[34] L_MDI_1- 7 18 U_USB1P_R U_USB1N_R 1 4
[34] L_MDI_2+ 8 22 U_USB1N [22]
U_USB0P_R
[34] L_MDI_2- 9 U_USB1P_R 2 3
[34] L_MDI_3+ 10 19 U_USB1P [22]
[34] L_MDI_3- 1 23 Common Choke 90 Ohm
YLW_LED
+3V_LAN
**
12 24 RU5 0
*
RL25 150 11 25 Dummy
[34] L_ACTLEDN
+/ -1% 26 RU6 0
27
C
CL22
470pF * * CL23
470pF
Dummy
C
50V, X7R, +/-10% 50V, X7R, +/-10%
USB_PWR0_F_50
CONN - USBX2_RJ45
Change to BAT54A and remove CL24 for UU1
Cost down-11/23/09 U_USB0N_R 1 6 U_USB0P_R
2 5
DL1
1 U_USB1N_R 3 4 U_USB1P_R
[34] L_LINK100#
3
2 L_FP_LAN_LED_GRN# [56]
[34] L_LINK10# IP4223CZ6
BAT54A
Dummy for Cost down-11/23/09
stuff on 20100723-EMC request
LAN POWER
+3V_S5 +3V +3V_EPW +3V_LAN
B B
+5V_S5
QL1
SI4835DDY-T1-GE3
3 8 RL27 RL28
* RL26 2 7 0 0
1K 1 6 Dummy Dummy
5
L_VREG_LANDUAL_PCH
1
* ECL1
* CL25
4
120uF 0.1uF
C
20100728: RL30 change to 8.2kOhm 16V, +/-20% 16V, X7R, +/-10%

*
2
RL29 4.7K B QL2
[24] S_SLP_LAN#
MMBT3904-7-F
RL30
E
L_VREG_Gate
*RL31
100K
Dummy 1K
+/-1%
* CL26
1uF
6.3V,X5R,+/-10%
A A
+3V +3V_S5
Title
* CL27
* CL28 LAN Power & LAN/USB Conn
1uF 1uF
16V, X5R, +/-10% 16V, X5R, +/-10% DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+5V Amplifer Power from 5V +5VA
FBA1 VCC_AUD +5V_S5
*
A_BIAS_MIC1_L CA5 10uF 6.3V, X5R, +/-20%
*
FB 600 Ohm close to pin 39
* CA1
* CA2
* CA3
* CA4 close to pin 28 Discret
FBA2
10uF 0.1uF 10uF 0.1uF
A
6.3V, X5R, +/-20%
16V, X7R, +/-10%
6.3V, X5R, +/-20%
16V, X7R, +/-10%

A_GND Dummy Analog
DA1
D co-lay with 269-VB

Pop with 269-VA
* SD103AW Power
Improve all output THD+N
C
FB 600 Ohm
RA1 0 +/-5% +12V
Dummy Front HP
RA2
Cap-saving, if HP-OUT port no use *
*
A_FRONT_L [37]
10 RA3 10+/-5%
+/-1% Dummy
A_FRONT_R [37]
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

40 mils Dummy DA2 Dummy UA2
A_BIAS_MIC1_L_VB [37] C A 1 3
A_BIAS_MIC1_R [37] OUT IN
FBA3
* FB 120 Ohm
1
A_BIAS_MIC2 [37]
* CA9
0.1uF *
CA10SD103AW * CA11 Dummy
GND
A_BIAS_MIC1_L [37]
* CA6
* CA7 10uF Dummy 120uF Dummy for cost
16V, Y5V, +80%/-20%
6.3V, X5R, +/-20%

Dummy down-11/23/09
2
2.2uF 2.2uF VCC_AUD
* CA8 L78L05N 16V, +/-20%
2
10uF DIGITAL
6.3V, X5R, +/-20%

A_GND A_GND A_GND
35
29
27
33
30
26
31
A_GND A_GND
32
ANALOG
36
28
34
25
UA1
A_GND A_GND
CBN
VREF
CPVREF
MIC2-VREFO
CBP
HP-OUT-R
CPVEE
AVSS1
MIC1-VREFO-R
AVDD1
HP-OUT-L
MIC1-VREFO-L
37 24
A_GND AVSS2 LINE1-R
VCC_AUD 38 23
AVDD2 LINE1-L
39 22
+5VA PVDD1 MIC1-R A_MIC1_R [37]
Front MIC
C [37] CLASSD_R+
[37] CLASSD_R-
RA6
RA7
0
+/-5%
0
40
41
SPK-L+
SPK-L- MONO-OUT
MIC1-L
21
20 TPA1
A_MIC1_L [37]
VCC_AUD decouple
+/-5% VCC_AUD
*
42 19 RA8 20K +/-1% close to
PVSS1 JDREF A_GND
43 18 pin 38
PVSS2 Sense-B B_SENSE [37]
TPA2
44 17
A_MIC2_R [37]
close to * CA17
0.1uF * CA18
0.1uF * CA19
10uF
SPK-R- MIC2-R Rear pin 25
+3V +3V_S5 +3V_VA 45 16
TPA3 SPK-R+ MIC2-L A_MIC2_L [37]
16V, X7R, +/-10%
16V, X7R, +/-10%
6.3V, X5R, +/-20%

46 15 A_GND A_GND A_GND
Digital Power from 3V +5VA PVDD2 LINE2-R A_LOUT_R [37]
GPIO0/DMIC-DATA
*RA5 *RA4
GPIO1/DMIC-CLK
0 0 47 14
TPA4 SPDIFO2/EAPD LINE2-L A_LOUT_L [37]
+/-5% +/-5%
48 13
SDATA-OUT
Dummy
TPA5 SPDIFO Sense A A_SENSE [37]
SDATA-IN
FBA4
DVDD-IO
*
PCBEEP
BIT-CLK
RESET#
DVDD1
ANALOG
DVSS2
SYNC
49
PD#
GND
close to pin 1
* CA12
0.1uF
FB 600 Ohm
* CA16
0.1uF * CA14
10uF * CA15
0.1uF
DIGITAL
16V, X7R, +/-10%
16V, X7R, +/-10%
6.3V, X5R, +/-20%
16V, X7R, +/-10%
ALC269Q-VB3-GR
1
10
11
12
+3V_VA
A_Z_SDIN0_R
BIT_CLK
TPA6 TPA7 TPA8
B PD#
A_Z_RST# [24]
*
[24] A_Z_SDOUT RA12 22+/-5% A_Z_SYNC [24]

[24] A_Z_BITCLK +3V_VA
*
RA13 33+/-5%
A_Z_SDIN0 [24]
* CA20
22pF
Dummy
50V, NPO, +/-5%
*
A_Z_RST# RA9 0 +/-5% PD#

Dummy
+3V_VA
*
RA10 0 +/-5% PD#

Dummy
+3V_S5 +5V_S5
Pop RA10: always H
Pop RA11 : control by BIOS (GPIO)
Pop RA9 : for De-pop during powr on.
PD#= L : Power down Class D SPK amplifer * RA41
1K
G
PD#= H : Power up Class D SPK amplifer

A_Z_RST# S D PD#
A +3V_VA
*
RA14 4.7K +/-5% A_Z_RST# QA1

Dummy 2N7002
Pop is RST signal glitched Title
Realtek recommend -01/15/10 Audio ALC269Q

DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 Front Audio 4 3 Rear2 Audio Jack 1
[36] A_BIAS_MIC1_R
[36] A_BIAS_MIC1_L
close to codec
*
[36] A_BIAS_MIC1_L_VB
[36] A_LOUT_L CA21 22uF A_LOUT_L_C RA15 75+/-1% RA16 0 A_LOUT_L_L
Audio Jack
*
+/-10%
*RA17 *RA18 *RA19
2.2KOhm 2.2KOhm 2.2KOhm
*
+/-1% +/-1% +/-1% [36] A_LOUT_R CA22 22uF A_LOUT_R_C RA20 75+/-1% RA21 0 A_LOUT_R_L LINE_OUT
*
Dummy +/-10% D
Rear Line In / Mic
D 6.3V, X5R, +/-10%
Front MIC
[36] A_BIAS_MIC2 LINE_IN / MIC_IN
**
*
CA23 1 2 4.7uF A_MIC1_R_C RA22 1K +/-1% RA23 0 close to codec C
* *
[36] A_MIC1_R
3
A_MIC1_R_L [56]
*
[36] A_MIC1_L CA24 1 2 4.7uF A_MIC1_L_C RA24 1K +/-1% RA25 0 DA3
A_MIC1_L_L [56]
BAT54A
6.3V, X5R, +/-10%
CA48 CA49 AUDIO
* 330pF
*CA25 *CA26 * 330pF
2
Dummy Dummy 22 INSULATOR
470pF 470pF 23
50V, NPO, +/-5%
50V, NPO, +/-5%

24
50V, X7R, +/-10%
50V, X7R, +/-10%

A_JD_LOUT
RA26 * *RA27 25
4.7KOhm 4.7KOhm 26
+/-1% +/-1% 27
6.3V, X5R, +/-10% 28
*
A_GND A_GND A_GND A_GND [36] A_MIC2_L CA27 1 2 4.7uF A_MIC2_L_C RA28 1K RA29 0 A_MIC2_L_L 29
*
+/-1% 2
Improve HP-OUT 32-Ohmˇs Cross-Talk and THD+N 3
It can be reserved if A_JD_MIC2 4
*
output de-coupled [36] A_MIC2_R CA28 1 2 4.7uF A_MIC2_R_C RA30 1K RA31 0 A_MIC2_R_L 5
*
+/-1% 1
cap used SMD type. Front HP 6.3V, X5R, +/-10%
CA29
* * CA30 CA31
* * CA32 CONN-Audio Port A_GND
**
[36] A_FRONT_R RA32 22 Ohm +/-1% RA33 ** 0

A_FRONT_R_L [56]
470pF 470pF 470pF 470pF
50V, X7R, +/-10%
50V, X7R, +/-10%

CA35 10nF
50V, X7R, +/-10%

50V, X7R, +/-10%
*
RA34 22 Ohm +/-1% RA35 0 25V, X7R, +/-10%
[36] A_FRONT_L A_FRONT_L_L [56]
A_GND
C Port A Support Capless HP

Change to 22ohm; follow *
CA47
330pF
* CA33
* CA34
*
CA46
330pF CA36 10nF
A_GND
*
Dummy 470pF 470pF Dummy 25V, X7R, +/-10%
Wembley-12/25/09
50V, X7R, +/-10%
50V, X7R, +/-10%

50V, NPO, +/-5%
50V, NPO, +/-5%

A_GND
CPA2 A_GND A_GND A_GNDA_GND
CA37 10nF 2 1
*
25V, X7R, +/-10% A_LOUT_L_L A_MIC2_L_L
COPPER
A_GND Dummy A_LOUT_R_L A_MIC2_R_L
A_GND A_GND A_GND A_GND CPA4
CA38 10nF 2 1
*
25V, X7R, +/-10%
2
COPPER
A_GND Dummy DA5 DA4
**
RA36 39.2K +/-1% Front HP CPA5 PESD5V0L2BT PESD5V0L2BT

[36] A_SENSE A_JD_FRONT [56] CA39 10nF 2 1
*
RA37 20K +/-1% Front MIC 25V, X7R, +/-10% Dummy Dummy
A_JD_MIC1 [56] COPPER
A_GND Dummy
Close to Pin A_GND
3
33
A_GND A_GND
A_MIC1_R_L A_FRONT_R_L
**
A_MIC1_L_L A_FRONT_L_L RA38 20K +/-1% A_JD_MIC2 Rear MIC In/LINE IN
B [36] B_SENSE
RA39 39.2K +/-1% A_JD_LOUT Rear Line out
1
Close to Pin 33
DA6 DA7
PESD5V0L2BT PESD5V0L2BT
Dummy Dummy
3
A_GND A_GND
Place connector CHASSIS

* CA42
100pF SPEAKER
Place near
Audio Chip
* CA41
1nF
50V, NPO, +/-5%
Dummy
50V, X7R, +/-10%
INT_SPKR Header 1x5 cut2
CLASSD_R- 1
[36] CLASSD_R-
Pin.1--> Left-
A CA43 1uF 3 Pin.2--> NC key

*
4 Pin.3--> GND
[32] O_AUD_PCSPKR_DET# 5
Dummy 10V, X5R, +/-10% CLASSD_R+ Pin.4--> SPK det#
[36] CLASSD_R+
Pin.5--> Left+
close to AR12, AR13
* CA45
1nF
Header_1X5_K2
Title
50V, X7R, +/-10%
* CA44
100pF Audio Conn
50V, NPO, +/-5%
Dummy DWG NO Rev
A00
Place connector Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
20100108: Swap pin for layout

+3V
RNX1
*1 2
X16_TRST
X16_TDI
[10] X_1X16_TXP[15..0] 3 4 X16_TMS
+3V_PCIAUX +3V +12V +12V +3V 5 6 X16_TCLK
[10] X_1X16_TXN[15..0] 7 8
D SLOT1 4.7K Ohm D
+/-5%
B1 A1
B2 12V1 PRSNT1# A2
B3 12V2 12V3 A3
B4 RSVD8 12V4 A4
**
RX1 0 Dummy B5 GND1 GND68 A5 X16_TRST +12V
[13,16,18,24,32,39,58,59] S_SMBCLK_PCI B6 SMCLK JTAG2 A6 X16_TDI X_1X16_RXP[15..0] [10]
RX2 0 Dummy
[13,16,18,24,32,39,58,59] S_SMBDATA_PCI B7 SMDAT JTAG3 A7
B8 GND2 JTAG4 A8 X16_TMS X_1X16_RXN[15..0] [10]
X16_TCLK B9 3.3V3 JTAG5 A9
B10 JTAG1 3.3V1 A10
B11 3.3VAUX 3.3V2 A11
[24] S_WAKE# WAKE# PWRGD X_PLTRST_PCIE_SLOT# [32,39,59]
KEY
* ECX1
470uF * CX1
0.1uF * CX2
0.1uF
Change capacitor 220nf;CRB 0.7-12/31/09 B12 A12 16V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10%
B13 RSVD1 GND67 A13
X_1X16_TXP0 CX36 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DP0 B14 GND3 REFCLK+ A14 C_PCIEX16_1 [27]
C_PCIEX16#_1 [27]
**
X_1X16_TXN0 CX37 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DN0 B15 HSOP0 REFCLK- A15
B16 HSON0 GND66 A16 X_1X16_RXP0
B17 GND4 HSIP0 A17 X_1X16_RXN0
B18 PRSNT2_B17# HSIN0 A18
GND5 GND65 +3V
X_1X16_TXP1 CX34 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DP1 B19 A19

** ** **
X_1X16_TXN1 CX35 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DN1 B20 HSOP1 RSVD7 A20
HSON1 GND64
B21
B22 GND6 HSIP1
A21
A22
X_1X16_RXP1
X_1X16_RXN1
* ECX2
470uF * CX8
0.1uF * CX9
0.1uF
C X_1X16_TXP2 CX32 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DP2 B23 GND7 HSIN1 A23 6.3V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10% C
X_1X16_TXN2 CX33 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DN2 B24 HSOP2 GND63 A24
X_1X16_TXP3 CX30 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DP3 B27 GND9 HSIN2 A27
B31 RSVD2 HSIN3 A31
B32 PRSNT2_B31# GND59 A32 +3V_PCIAUX
GND11 RSVD6
** ** ** **
HSON4 GND58
B35
B36 GND12 HSIP4
A35
A36
X_1X16_RXP4
X_1X16_RXN4
* ECX3
470uF * CX16
0.1uF
X_1X16_TXP5 CX26 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DP5 B37 GND13 HSIN4 A37 6.3V, +/-20% 16V, X7R, +/-10%
GND19 GND51 SLOT1_LATCH
B B
** ** ** ** ** ** ** **
B52 HSON8 GND50 A52 X_1X16_RXP8 G G
GND20 HSIP8
2
B53 A53 X_1X16_RXN8
X_1X16_TXP9 CX18 220nF 25V, X7R, +/-10% X_EXP_A_TX_C_DP9 B54 GND21 HSIN8 A54 Retention Module
2
X_1X16_TXP11 X_EXP_A_TX_C_DP11 B62 GND25 HSIN10 A62
CX13 220nF 25V, X7R, +/-10%
A A
RSVD3 GND35 Title
Slot-PCIE-16X
340303U00-600-G Slot1: PCIe 16x
340304R00-278-G DWG NO Rev
340304J00-317-G A00
340306Y00-GRS-G Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+3V
RNX2
*1 2
X4_TDI
X4_TMS
3 4 X4_TCLK
5 6 X4_TRST
7 8 Change SLOT4 for Cost
4.7K Ohm down-12/07/09
+/-5%
+3V_PCIAUX +3V +12V +12V +3V
D SLOT4 D
B1 A1
B2 12V1 PRSNT1# A2
B3 12V2 12V3 A3
RX4 B4 RSVD8 12V4 A4
**
0 Dummy B5 GND1 GND68 A5 X4_TRST Dummy ECX4,CX38 for Cost
[13,16,18,24,32,38,58,59] S_SMBCLK_PCI 0 Dummy B6 SMCLK JTAG2 A6 X4_TDI +12V down-11/23/09
[13,16,18,24,32,38,58,59] S_SMBDATA_PCI B7 SMDAT JTAG3 A7
RX3 B8 GND2 JTAG4 A8 X4_TMS
X4_TCLK B9 3.3V3 JTAG5 A9
B10 JTAG1 3.3V1 A10
B11 3.3VAUX 3.3V2 A11
[24] X4_WAKE# WAKE# PWRGD X_PLTRST_PCIE_SLOT# [32,38,59]
B12
KEY
A12
* ECX4
470uF * CX38
0.1uF * CX39
0.1uF
B13 RSVD1 GND67 A13 16V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10%
CX47 0.1uF 16V, X7R, +/-10% X_1X4_TXP0_C B14 GND3 REFCLK+ A14 C_PCIEX4_1 [27] Dummy Dummy
[22] X_1X4_TXP0 C_PCIEX4#_1 [27]
**
CX49 0.1uF 16V, X7R, +/-10% X_1X4_TXN0_C B15 HSOP0 REFCLK- A15
[22] X_1X4_TXN0 B16 HSON0 GND66 A16
B17 GND4 HSIP0 A17 X_1X4_RXP0 [22]
PRSNT2_B17# HSIN0 X_1X4_RXN0 [22]
B18 A18
GND5 GND65
CX40 0.1uF 16V, X7R, +/-10% X_1X4_TXP1_C B19 A19

** ** **
[22] X_1X4_TXP1 CX41 0.1uF 16V, X7R, +/-10% X_1X4_TXN1_C B20 HSOP1 RSVD7 A20
[22] X_1X4_TXN1 B21 HSON1 GND64 A21 +3V
B22 GND6 HSIP1 A22 X_1X4_RXP1 [22]
GND7 HSIN1 X_1X4_RXN1 [22]
C CX42 0.1uF 16V, X7R, +/-10% X_1X4_TXP2_C B23 A23 Dummy ECX5 for Cost C
[22] X_1X4_TXP2 X_1X4_TXN2_C B24 HSOP2 GND63 A24
CX43 0.1uF 16V, X7R, +/-10% down-11/23/09
[22] X_1X4_TXN2 HSON2 GND62
B25
B26 GND8 HSIP2
A25
A26 X_1X4_RXP2 [22] * ECX5
470uF * CX46
0.1uF * CX48
0.1uF
GND9 HSIN2 X_1X4_RXN2 [22]
CX44 0.1uF 16V, X7R, +/-10% X_1X4_TXP3_C B27 A27 6.3V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10%
[22] X_1X4_TXP3 X_1X4_TXN3_C B28 HSOP3 GND61 A28
CX45 0.1uF 16V, X7R, +/-10% Dummy
[22] X_1X4_TXN3 B29 HSON3 GND60 A29
GND10 HSIP3 X_1X4_RXP3 [22]
B30 A30
RSVD2 HSIN3 X_1X4_RXN3 [22]
B31 A31
B32 PRSNT2_B31# GND59 A32
GND11 RSVD6
B33 A33
B34 HSOP4 RSVD5 A34
B35 HSON4 GND58 A35 +3V_PCIAUX
B36 GND12 HSIP4 A36
B37 GND13 HSIN4 A37
B38 HSOP5 GND57 A38
B39 HSON5 GND56 A39
B40 GND14
GND15
HSIP5
HSIN5
A40 * CX50
0.1uF
B41 A41 16V, X7R, +/-10%
B42 HSOP6 GND55 A42
B43 HSON6 GND54 A43
B44 GND16 HSIP6 A44
B45 GND17 HSIN6 A45
B46 HSOP7 GND53 A46
B47 HSON7 GND52 A47
B48 GND18 HSIP7 A48
GND19 GND51
B B
B50 A50
B51 HSOP8 RSVD4 A51
B52 HSON8 GND50 A52
B53 GND20 HSIP8 A53
B54 GND21 HSIN8 A54
B55 HSOP9 GND49 A55
B56 HSON9 GND48 A56
B57 GND22 HSIP9 A57
B58 GND23 HSIN9 A58
B59 HSOP10 GND47 A59
B60 HSON10 GND46 A60
B61 GND24 HSIP10 A61
B62 GND25 HSIN10 A62
SLOT4_LATCH B71 HSOP13 GND41 A71
G G B75 HSOP14 GND39 A75
HSON14 GND38
1
B76 A76
Retention Module B77 GND32 HSIP14 A77
A A
1

RSVD3 GND35 Title
Slot-PCIE-16X
Slot4: PCIe 4x
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+3V_S5
* RX8
D 2.2K D
[24] GPIO_WIRELESS_DISABLE#
C C
B B
A A
Title
TBD
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
CV1 0.1uF 16V, X7R, +/-10% V_DPC_TX0_DP
* *
[26] V_DDSP_C_DP_0_DP
DP_PORT
[26] V_DDSP_C_DP_0_DN
CV2 0.1uF 16V, X7R, +/-10% V_DPC_TX0_DN Dummy for Cost down-11/23/09
23 22
UV1
HOLE3 HOLE2
10 1 V_DPC_TX0_DP 1
9 O1 IN1 2 2 ML_Lane0_P
8 O2 IN2 3 V_DPC_TX0_DN 3 GND1
CV3 0.1uF 16V, X7R, +/-10% V_DPC_TX1_DP 7 GND_2 GND_1 4 V_DPC_TX1_DP 4 ML_Lane0_N
[26] V_DDSP_C_DP_1_DP
* ** *
6 O3 IN3 5 5 ML_Lane1_P
CV4 0.1uF 16V, X7R, +/-10% V_DPC_TX1_DN O4 IN4 V_DPC_TX1_DN 6 GND2
[26] V_DDSP_C_DP_1_DN CV5 0.1uF 16V, X7R, +/-10% V_DPC_TX2_DP V_DPC_TX2_DP 7 ML_Lane1_N
RCLAMP0524P.TCT Dummy
[26] V_DDSP_C_DP_2_DP 10 1 8 ML_Lane2_P
D CV6 0.1uF 16V, X7R, +/-10% V_DPC_TX2_DN 9 O1 IN1 2 V_DPC_TX2_DN 9 GND3 D
[26] V_DDSP_C_DP_2_DN 8 O2 IN2 3 V_DPC_TX3_DP 10 ML_Lane2_N
7 GND_2 GND_1 4 11 ML_Lane3_P
6 O3 IN3 5 V_DPC_TX3_DN 12 GND4
O4 IN4 DP_P13 13 ML_Lane3_N
RCLAMP0524P.TCT Dummy 14 GND5
CV7 0.1uF 16V, X7R, +/-10% V_DPC_TX3_DP UV2 V_DPC_AUX_DP 15 GND6
**
[26] V_DDSP_C_DP_3_DP 16 AUX_CH_P
CV8 0.1uF 16V, X7R, +/-10% V_DPC_TX3_DN V_DPC_AUX_DN 17 GND7
[26] V_DDSP_C_DP_3_DN V_DPC_HPD_SINK 18 AUX_CH_N
19 H_P_DETECT
20 RETURN
*RV1
1M *RV2 V_DPC_PWR
DP_PWR
UV3 100K 24 21
V_DPC_AUX_DN 6 1 V_DPC_AUX_DN HOLE4 HOLE1
O2 IN1 CONN - Display port
V_DPC_AUX_DP 5 2 V_DPC_AUX_DP
O1 IN2 Close to Connector
4 3
GND_2 GND_1
RCLAMP0522P.TCT
Dummy
UV4
DP_P13 6 1 DP_P13
O2 IN1
V_DPC_HPD_SINK 5 2 V_DPC_HPD_SINK
O1 IN2
4 3
C GND_2 GND_1 C
RCLAMP0522P.TCT
Dummy
V_DDPC_CTRL_CLK V_DDPC_CTRL_DATA V_DDSP_C_AUX_DP_C V_DDSP_C_AUX_DN_C
D
QV1 QV2 QV3 QV4
2N7002 2N7002 2N7002 2N7002
DP_P13_POS G G DP_P13_POS DP_P13_INV G G DP_P13_INV
CV9 0.1uF 16V, X7R, +/-10% V_DDSP_C_AUX_DN_C
S
**
[26] V_DDSP_C_AUX_DN
CV10 0.1uF 16V, X7R, +/-10% V_DDSP_C_AUX_DP_C
[26] V_DDSP_C_AUX_DP
Close to Connector
* RV3 *RV4 * RV5 *RV6
1M 1M 1M 1M
S
+/-5% +/-5% +/-5% +/-5%
G G G G
+3V +3V
+3V 2N7002 2N7002 2N7002 2N7002
QV5 QV6 QV7 QV8
FV1 FUSE_1.1A V_DPC_PWR
* * *
D
RV7 RV8
* CV11
1uF
* CV12
10uF * CV13
470pF * CV14
22uF
2.2K
+/-5%
2.2K
+/-5% V_DPC_AUX_DP V_DPC_AUX_DN V_DPC_AUX_DP V_DPC_AUX_DN
16V,X5R,+/-20% Dummy 50V, X7R, +/-10% 6.3V,X5R,+/-20%
10V,X5R,+/-20%
+12V +12V
B
[26] V_DDPC_CTRL_CLK
V_DDPC_CTRL_CLK * RV9
4.7K
* RV10
B
8.2K
V_DDPC_CTRL_DATA +/-5% +/-5%
[26] V_DDPC_CTRL_DATA DP_P13_POS
D
+5V
QV9
2N7002
*
DP_P13_INV RV11 0 G
* RV12
S
1K
Dummy QV10
Display Port Hotplug Detect 2N7002
*
DP_P13 RV13 8.2K G
+5V +/-5%
S
V_DPC_HPD_SINK * RV14 * CV15
* RV15 1M 0.1uF
1K +3V +3V_DUAL +3V +/-5% 16V, X7R, +/-10%
Dummy
+5V
*RV16 * RV17 * RV18

D
100KOhm 100KOhm 100KOhm

V_DPC_HPD_SINK QV11 +/-1% +/-1% +/-1%
A Dummy Dummy A
G
FDV301N V_DPC_AUX_DN
S
V_DPC_AUX_DP
*RV19
100K Title
* RV20 * RV21 Display Port

100KOhm 100KOhm
V_DDSP_C_HPD [21,26] DWG NO Rev
+/-1% +/-1%
Dummy A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
VGA Connector +3V
* CV16
0.1uF
+5V Change to short pad and remove VC19, 16V, X7R, +/-10%
+3V +3V
CV22,CV25 for cost down-11/23/09
2
D DV1 LV1 RV22 D
1N4148W V_RED 1 2 47ohm 100MHz Dummy1 2 3 QV12
[26] V_RED
BAV99
*RV23
C
+5V_DDC
2.2K
1
+/-5%
*RV24 *RV25
150
* CV17
* CV18
* CV19
2.2K +/ -1% 3.3pF 3.3pF 10pF
G
+/-5% 50V, NPO, +/-0.25pF 50V, NPO, +/-0.25pF 50V, NPO, +/-5%
Dummy
S D V_DDCA_CLK_5V
[26] V_DDCA_CLK
2
QV13
2N7002 LV2 RV26
V_GREEN 1 2 47ohm 100MHz Dummy1 2 3 QV14
[26] V_GREEN
+3V +3V BAV99
1
*RV27
150
* CV20
3.3pF
* CV21
3.3pF
* CV22
10pF
+5V_DDC +/ -1% 50V, NPO, +/-0.25pF 50V, NPO, +/-0.25pF 50V, NPO, +/-5%
*RV28 Dummy
2.2K
+/-5% *RV29
2
2.2K LV3 RV30
G
V_BLUE 1 2 47ohm 100MHz Dummy1 2 3 QV15

+/-5% [26] V_BLUE
BAV99
C S D V_DDCA_DATA_5V C
[26] V_DDCA_DATA
1
QV16
2N7002
*RV31
150
* CV23
3.3pF
* CV24
3.3pF
* CV25
10pF
+/ -1% 50V, NPO, +/-0.25pF 50V, NPO, +/-0.25pF 50V, NPO, +/-5%
Dummy
+5VSB +5V
+5V
FV2 FUSE_1.1A VGAPWR_F_20

*
2
Dummy for Cost
down-11/23/09
3 QV17 3 QV20 3 QV18 3 QV19 * CV26
0.1uF * CV27
0.1uF
BAV99 BAV99 BAV99 BAV99 16V, X7R, +/-10% 16V, X7R, +/-10%
1
+3V VGA_SERIALA
VGA
+5V V_DDCA_CLK_5V RV33 100 +/-1% B15 SCL GND B5
B10 GND
**
B14 VSYNC B4
*RV36
4.7K
V_VSYNC_5V RV32 0
B9 NC
ID0 V_GPI_VGA_CBL_DET# [21]
B13 HSYNC B3
+/-5%
* CV29
0.1uF
V_HSYNC_5V RV34 0
B8 GND
B V_BLUE_R
5
B B12 SDA B2 B
UV5 16V, X7R, +/-10% V_DDCA_DATA_5V RV35 100 +/-1% G V_GREEN_R
1 B7 GND
4 V_VSYNC_5V B11 ID1 R B1 V_RED_R * CV28
100pF
2 B6 GND 50V, NPO, +/-5%
[26] V_VSYNC_3V
74AHCT1G08GW CONN - Dual port
*RV37
3
1
2
100
+/-5%
Dummy
* CV30
100pF * CV31
12pF * CV32
12pF * CV33
100pF
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%

+3V
*RV38
4.7K +5V
+/-5%
5
UV6
1
4 V_HSYNC_5V
2
[26] V_HSYNC_3V
74AHCT1G08GW
*RV39
3
100
A +/-5% A
Dummy
Title
VGA Conn
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
SATA x 3
SATA0
CT1 10nF 25V, X7R, +/-10% T_SATA_TXP0_C 2
* * **
[23] T_SATA_TXP0 TX+
D CT2 10nF 25V, X7R, +/-10% T_SATA_TXN0_C 3 D
[23] T_SATA_TXN0 TX-
8
CT3 10nF 25V, X7R, +/-10% T_SATA_RXN0_C 5 NC#8
[23] T_SATA_RXN0 RX-
CT4 10nF 25V, X7R, +/-10% T_SATA_RXP0_C 6
[23] T_SATA_RXP0 RX+ 9
NC#9
1
4 GND
7 GND#4
GND#7
CONN-SATA
Just SATA port 0 support Gen3 ; EDS1.5
SATA1
** **
CT6 10nF 25V, X7R, +/-10% T_SATA_TXN1_C 3
8
NC#9
C 1 C
4 GND
7 GND#4
GND#7
CONN-SATA
SATA2
** **
8
NC#9
1
4 GND
7 GND#4
GND#7
CONN-SATA
B B
A A
Title
SATA Conn
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
Rear USB CONNECTOR
D D
USBPWR1_F_50 USBPWR1_F_50
USB
LU3 UU2
2 3 U_USB2N_R 41
[22] U_USB2N 1 6 42 VCC1
U_USB2N_R U_USB2P_R U_USB2N_R
1 4 U_USB2P_R U_USB2P_R 43 USB0-
[22] U_USB2P
Common Choke 90 Ohm
2 5 44 USB0+
GND1
UP
U_USB3N_R 3 4 U_USB3P_R
RU7
** 0
Dummy
IP4223CZ6
Dummy for Cost down-11/23/09 U_USB3N_R
U_USB3P_R
31
32
33
VCC2
USB1-
RU8 0
Dummy stuff on 20100723-EMC request 34 USB+
GND2
Second
+5V_DUAL_USBKB USBPWR1_F_50 USBPWR2_F_50
LU4
2 3 U_USB3N_R 21
[22] U_USB3N
*
FU2 1
* 2 Fuse 2A RU9 10K U_USB4N_R 22 VCC3
[22] U_USB3P
1 4 U_USB3P_R
*
+/-1% 1
U_USB_OC_R_#1 [22] U_USB4P_R 23
24
USB2-
USB2+ Third
Common Choke 90 Ohm
ECU2
470uF * CU8
0.1uF RU10 GND3
C 6.3V, +/-20% 16V, X7R, +/-10% 15K C
+/-1% 45
**
RU11 0 2 11 GND5 46
Dummy U_USB5N_R 12 VCC4 GND6 47
RU12 0
Dummy
U_USB5P_R 13
14
USB3-
USB3+ Down GND7
GND8
48
49
GND4 GND9 50
USBPWR2_F_50
GND10
CONN - USBX4
LU5 UU3
2 3 U_USB4N_R
[22] U_USB4N U_USB4N_R 1 6 U_USB4P_R
1 4 U_USB4P_R
[22] U_USB4P 2 5
Common Choke 90 Ohm
**
RU13 0
IP4223CZ6
Dummy
RU14 0 Dummy for Cost down-11/23/09
Dummy stuff on 20100723-EMC request
LU6
2 3 U_USB5N_R +5V_DUAL_USBKB USBPWR2_F_50
[22] U_USB5N
1 4 U_USB5P_R
*
[22] U_USB5P *
FU3 1 2 Fuse 2A RU15 10K
Common Choke 90 Ohm U_USB_OC_R_#2 [22]
+/-1% 1
B B
* ECU3
470uF
* CU9
0.1uF RU17
**
RU16 0 6.3V, +/-20% 16V, X7R, +/-10% 15K

Dummy +/-1%
RU18 0 2
Dummy
A A
Title
Rear USB
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+12V
TPM, TCM (TCM is just reserved

because MRD has removed TCM requirement)
+3V
(Default) *RF4
ST Micro POP S CF4 8.2K
+/-1%
ZTE POP Z CF2,CF4,CF7,RF10,RF19,RF20,RF21 * CF1
0.1uF
* CF2
0.1uF
* CF3
0.1uF
* CF4
10uF
@S,Z,J
G
Jetway POP J CF2,CF8,RF10,RF16,RF21 16V, X7R, +/-10% 16V, X7R, +/-10% 6.3V, X5R, +/-20%
@Z,J @S,Z
close to Pin 10
D S S_PLTRST#_R
close to Pin 19
16V, X7R, +/-10% [9,24,32,34,52,53] S_PLTRST#
D D
QF1
2N7002
@S,Z,J *RF5
8.2K
*
RF6 33 +/-1%
close to Pin 24 Dummy @S,Z,J
+3V +3V
20100510: UF1 TPM IC change to ST33ZP24

20100519: UF1 TPM IC change to SB19NP18ER28PVMT
20101001: UF1 usage TCM_SSX44-B-D-T +12V
10
24
C UF1 C
* CF5
* CF6
VPS1
VPS2
21 0.1uF 0.1uF
[27,53] C_LPC_TPM LCLK 15 F_TPM_CLKRUN# Dummy Dummy
22 GPIO5 9 F_TPM_PIN9 16V, X7R, +/-10%
[24,32,53] F_FRAME# LFRAME# GPIO4 7 F_TPM_PIN7 16V, X7R, +/-10%
S_PLTRST#_R 16 PP 6 F_TPM_PIN6 TPF1
+3V
LRESET# GPIO3 3 F_TPM_PIN3 TPF2
17 VNC 2 F_TPM_PIN2
TPF3
[24,32,53] F_LAD3 20 LAD3 GPIO2 1 F_TPM_PIN1 TPF4
[24,32,53] F_LAD2 23 LAD2 GPIO1 5 TPF5
+3V F_TPM_PIN5
[24,32,53] F_LAD1 26 LAD1 NC1 8 F_TPM_PIN8
[24,32,53] F_LAD0 LAD0 NC2 12 TPF6
F_TPM_PIN12
TPF7
20101001: add UF2 usage TPM_SB19NP18ER28PVMK
NC3 13 RF16 0
NC4
*
C_14M_TPM [27]
*
RF27 4.7K F_PWRDWN# 28 14 @J +/-5%
@S,Z,J +/-5%
LPCPD# NC5 19 UF2
*
27 NC6 25 RF10 0
[23,32] F_SERIRQ# SERIRQ NC7 @Z,J +/-5%
* CF7
1uF
GPIO5
15
GND3
GND2
GND1
6.3V,X5R,+/-10% 1
@Z GPIO1
SSX44-B-D-T
4
18
11
@Z
B B
SB19NP18ER28PVMK
@S,J
A A
F_TPM_PIN5 F_TPM_PIN9 F_TPM_PIN3 F_TPM_CLKRUN#
* CF8 *RF19 *RF20

1K *RF21 Title
0.1uF 1K @Z 4.7K
16V, X7R, +/-10% @Z +/-5% TPM & TCM
@J @Z,J
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
Change net to O_TR_MB+/-; SMSC suggestion-12/08/09

Removed THRM1 since useless-01/01/10
Header_1X2 O_TR_CPU+ [32]

2
1 * CO23
330pF
@DT
C THRM_1
@DT
50V, NPO, +/-5%
O_TR_CPU- [32]
Dummy THRM2,CO23; ME suggestion-12/04/09
O_TR_MB+
Header_1X2 O_TR_MB+ [32]
2
1 * CO24
330pF
50V, NPO, +/-5%
THRM_2 O_TR_MB-
O_TR_MB- [32]
THERMAL SENSOR
A
Title
Thermal Sensor Conn

DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
CPU Fan
+3V +3V
+3V +3V
*RO74 *RO75
*RO72 *RO73 1K 4.7K
4.7K 4.7K +/-5%
+/-5%
+/-5% +/-5%
*
RO76 0
B
D QO11 Dummy +/-5% D
MMBT3904-7-F
*
E C O_CPUFAN_PWM_R RO77 220
C
[32] O_CPUFAN_PWM [32] O_SEN_CPUFAN
*
B RO78 4.7K
+/-5% +12V
QO12
* CO29
E
MMBT3904-7-F 0.1uF
+5V 16V, X7R, +/-10%
FAN_CPU
+12V
1
* RO79 2
1K 3
*
+/-5% O_CPUFAN_PWM_R RO80 100 Ohm 4
*
RO81 39K +/-1% 5
1
[32] O_CPUFAN_ID +/-5%
Header-1X5
* ECO1
120uF
16V, +/-20%
2
* CO30
0.1uF *RO82 CO31
** CO32
* CO33
16V, X7R, +/-10%

39K 4.7uF 0.1uF 0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%

Dummy
+/-5% 25V,Y5V,+80/-20%
Dummy
Dummy
C C
+3V +3V
+3V +3V +12V

SYS Fan *RO85 *RO86
*RO83 *RO84 1K 4.7K
4.7K 4.7K +/-5% +/-5%
1
+/-5% +/-5% * ECO2
*
RO87 0 120uF
B
QO13 Dummy +/-5% 16V, +/-20%
2
MMBT3904-7-F
*
E C O_CHAFAN_PWM_R RO88 220
[32] O_CHAFAN_PWM [32] O_SEN_CHAFAN
*
B RO89 4.7K
+/-5% +12V
QO14
* CO34
E
MMBT3904-7-F 0.1uF
16V, X7R, +/-10%
FAN_SYS
B 1 B
2
3
*
O_CHAFAN_PWM_R RO90 100 4
+/-5% 5
Header-1X5
CO35
4.7uF *
25V,Y5V,+80/-20%
Dummy
PSU Fan
A A
20100111: Remove PSU PWM control
Title
FAN
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
KB/MS
D D
+5V_DUAL_USBKB
*
C C
FO1
FUSE_1.1A
* CO36
0.1uF
16V, X7R, +/-10%
+5V_DUAL_USBKB
Close to Pin 10 (EMI) Close to Pin 4 (EMI)

RNO3 KYBD_MOUSE
* CO37 * CO38
8
6
4
2
2K 0.1uF 0.1uF
13 16V, X7R, +/-10% 16V, X7R, +/-10%
+/-5%
7
5
3
1
16
*
****
FBO1 FB 600 Ohm O_MS_DATA_L 12 6

[32] O_MS_DATA 10 4
FBO2 FB 600 Ohm O_MS_CLK_L 8 2
[32] O_MS_CLK O_MS_DATA_L 7 14
FBO3 FB 600 Ohm O_KB_CLK_L 9 1 O_KB_DATA_L
[32] O_KB_CLK O_MS_CLK_L 11 3
FBO4 FB 600 Ohm O_KB_DATA_L 5 O_KB_CLK_L
[32] O_KB_DATA 17
CNO3 15
180pF UP DOWN
B * 50V, NPO, +/-10% CONN - KB_MS
B
Dummy
+5V_DUAL_USBKB
UO3 Dummy
O_MS_DATA_L 1 6 O_MS_CLK_L
2 5
O_KB_DATA_L 3 4 O_KB_CLK_L
IP4220CZ6
A A
Title
PS2 Conn
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
Serial Port 1
D D
VGA_SERIALB
4
CPO1
O_DCD1# T1 2 1
O_DSR1# T6
UO2 O_RXD1 T2 COPPER
20 1 O_+12VCOM O_RTS1# T7 Dummy
+5V VCC +12V O_TXD1 T3
TI
16 5 O_RTS1# O_CTS1# T8
[32] O_RTS1#_R 15 DA1 DY1 6 O_DTR1# O_DTR1# T4 O_+12VCOM C A
[32,33] O_DTR1#_R DA2 DY2 +12V
SN200602074PWR
13 8 O_TXD1 O_RI1# T9 DO2 1N4148W
[32] O_TXD1_R 19 DA3 DY3 2 O_RI1# T5
[32] O_RI1#_R 18 RY1 RA1 3 Dummy
O_CTS1#
[32] O_CTS1#_R 17 RY2 RA2 4 O_DSR1# 3 CO39 Dummy for Cost down-11/23/09
[32] O_DSR1#_R 14 RY3 RA3 7 O_RXD1 10nF
[32] O_RXD1_R 12 RY4 RA4 9 O_DCD1#
[32] O_DCD1#_R RY5 RA5 CONN - Dual port
11 10 O_-12VCOM
GND -12V
SN200602074PWR
C CPO2 C
2 1
O_DCD1# COPPER
O_DSR1# Dummy
O_RXD1
O_RTS1#
placed near GD75232 O_TXD1 O_-12VCOM A C
-12V
O_CTS1# DO3 1N4148W
O_DTR1#
+5V Dummy
O_+12VCOM O_-12VCOM O_RI1# CO40
10nF Dummy for Cost down-11/23/09
* *
* CO41
0.1uF * CO42
0.1uF * CO43
0.1uF
CNO4
180pF
CNO5
180pF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10%
Dummy Dummy
1. CO41 decouple change from placed near connector

+12V to O_+12VCOM-12/03/09
2. CO42 decouple change from
-12V to O_-12VCOM-12/03/09
B B
A A
Title
COM1
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+3V_S5
SPI
* CF10
0.1uF
**
RS167 0 16V, X7R, +/-10%
[24] F_SPI_CS1#_ISOLATE SPI_1
RS168 0 1 8
[24] F_SPI_CS0#_ISOLATE F_SPI_CLK_PRI_SEC_FLSH_R1 6 CS# VCC 7 F_SPI_HOLD1#
D Dummy D
F_SPI_MOSI_PRI_SEC_FLSH_R1 5 SCK HOLD# 3 F_SPI_WP1#
20091225: Change net 2 SI WP# 4
F_SPI_MISO_R1
name for Dual SPI SO GND
SPI SOCKET
Dummy
+3V_S5
Dummy for cost down-11/23/09 SPI1

CLOSE TO SPI
20100329: SPI_ROM1 Package Type
change to DIP from SMD , when usage If socket not use ,need change to SMD Tpye
* CF11
1uF * CF12
0.1uF
SPI_1 socket 6.3V,X5R,+/-10% 16V, X7R, +/-10%
MX25L1606EM2I-12G
20100512: SPI_ROM1 change to +3V_S5
NUMONYX_M25PX16-VMW6TG and mount

20100512: SPI_ROM1 rename to SPI1
*
20100930: SPI1 change to MXIC_MX25L1606EM2I-12G RNF1
7
5
3
1
1K
+/-5%
** ** **
8
6
4
2
[24] F_SPI_MISO RF22 33 F_SPI_MISO_R
RF23 33 F_SPI_MISO_R1
F_SPI_HOLD#
F_SPI_WP#
C RF28 33 F_SPI_CLK_PRI_SEC_FLSH_R F_SPI_HOLD1# C
[24] F_SPI_CLK_PRI_SEC_FLSH
F_SPI_WP1#
RF29 33 F_SPI_CLK_PRI_SEC_FLSH_R1
[24] F_SPI_MOSI_PRI_SEC_FLSH RF30 33 F_SPI_MOSI_PRI_SEC_FLSH_R
RF31 33 F_SPI_MOSI_PRI_SEC_FLSH_R1
SPI_2 20091225: Change net
20091225: RF23 change to 33ohm for Dual SPI F_SPI_HOLD# 1 16 F_SPI_CLK_PRI_SEC_FLSH_R
2 HOLD# C 15 F_SPI_MOSI_PRI_SEC_FLSH_R name for Dual SPI
20091225: Add RF28, RF29,RF30,RF31 for Dual SPI +3V_S5
3 VCC D 14
4 DU1 DU8 13
**
RS169 0 Dummy 5 DU2 DU7 12
[24] F_SPI_CS1#_ISOLATE 6 DU3 DU6 11
RS170 0 7 DU4 DU5 10
[24] F_SPI_CS0#_ISOLATE 8 S# VSS 9
F_SPI_MISO_R F_SPI_WP#
Q W#
ACA-SPI-006-K01
Dummy
SPI2
20100309: SPI2 Package Type
change to DIP from SMD, , when SPI_3
F_SPI_CS0#_ISOLATE 1 8
usage SPI_2 socket F_SPI_CLK_PRI_SEC_FLSH_R 6 CS# VCC 7 F_SPI_HOLD#
+3V_S5
20091225: Change net 5 SCK HOLD# 3
20100930: SPI2 change to F_SPI_MOSI_PRI_SEC_FLSH_R F_SPI_WP#
name for Dual SPI F_SPI_MISO_R 2 SI WP# 4
B MXIC_MX25L6445EMI-10G SO GND B
MX25L6445EMI-10G SPI SOCKET

Dummy
A A
Title
SPI
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
For debugging
XDP Connector - CPU
+1P05V_VCCIO XDP_CPU
+1P05V_VCCIO
Remove RH46 and
43 55
44 VCC_OBS_AB TCK1 57 option connection to
VCC_OBS_CD TCK0 52 H_TCK [9]
TDO 54 H_TDO [9] H_TAPPWRGOOD;
[9] H_PREQ#
3
OBSFN_A0
TRSTn
TDI
56 H_TRST# [9]
H_TDI [9]
follow CRB0.7-12/27/09 *RH47 *RH49 * RH70
5 58 1.5K 3.3K 0
[9] H_PRDY# 9 OBSFN_A1 TMS H_TMS [9]
Dummy Dummy Dummy
**
[9] H_BPM#0 11 OBSDATA_A_0 39 F_XDP_PWRGD RH45 249 Ohm Add RH68 to F_XDP_PWRGD
[9] H_BPM#1 15 OBSDATA_A_1 HOOK0 41 F_XDP_PLTRST# H_PWRGD [9,24,64]
D D
[9] H_BPM#2 17 OBSDATA_A_2 HOOK1 45 H_TAPPWRGOOD RH68 1K H_CFG0; follow
[9] H_BPM#3 OBSDATA_A_3 HOOK2 47 RH67 1 2 H_CFG0 [9] F_XDP_PLTRST#
HOOK3 P_VR_READY [20,24,33,64,67] Pin 47 add RH67 to
CRB0.7-12/27/09
21 40 H_ITPCLK_R Dummy
23 OBSFN_B0 ITPCLK/HOOK4 42 H_ITPCLK#_R P_VR_READY;
*
27 OBSFN_B1 ITPCLKB/HOOK5 46 F_RSTOUT_XDP_N RH50 1K H_TAPPWRGOOD
[9] H_BPM#4 29 OBSDATA_B_0 RESETB/HOOK6 48 H_RESET#_R [9] follow CRB
[9] H_BPM#5 OBSDATA_B_1 DBRB/HOOK7 FP_RST# [9,24,53] 20091209: CRB0.7 empty RH47 and RH45 use 249
33 0.7-12/27/09
Dummy RH52,RH53; follow
[9] H_BPM#6 35 OBSDATA_B_2 ohm RH70 to +1P05V_VCCIO;
Remove RH51 Change net name to Add
[9] H_BPM#7 OBSDATA_B_3 1 CRB 0.7-12/27/09
GND1 -12/29/09 H_RESET#_R -12/28/09
51 7 follow CRB0.7-12/27/09
** ** **
[15,16,17,18,20,32] S_SMBDATA_MAIN 53 SDA GND2 13 H_ITPCLK_R RH52 0 Dummy
[15,16,17,18,20,32] S_SMBCLK_MAIN 4 SCL GND3 19 H_ITPCLK#_R H_ITPCLK [9]
RH53 0 Dummy
6 OBSFN_C0 GND4 25 H_ITPCLK# [9]
10 OBSFN_C1 GND5 31 RH54 0
12 OBSDATA_C_0 GND6 37 Remove RH58,RH59 RH55 0
C_PCH_ITP [27]
16 OBSDATA_C_1 GND7 49 C_PCH_ITP# [27]
OBSDATA_C_2 GND8 -12/29/09
18 59 RH56 0 Dummy
OBSDATA_C_3 GND9 2 RH57 0 Dummy C_CK505_ITP [20]
GND10 8 C_Ck505_ITP# [20]
22 GND11 14
24 OBSFN_D_0 GND12 20
Change clock source to
28 OBSFN_D_1 GND13 26 CK505; follow CRB
30 OBSDATA_D_0 GND14 32
34 OBSDATA_D_1 GND15 38
0.7-12/29/09
* *
36 OBSDATA_D_2 GND16 50 RH69 3.3K
OBSDATA_D_3 GND17 O_PWRBTN#IN [24,32,53,56]
60
GND18_XDP_PRESENTB F_XDP_PLTRST# RH48 1K
C Dummy S_PLTRST# [9,24,32,34,46,53] C
XDP Dummy
Add RH69 to O_PWRBTN#IN and dummy RH48; follow
CRB0.7-12/27/09
XDP Connector - PCH For debugging

XDP_PCH
10 17
20091230: Remove all
TP_0
TPS133
TP_1 12 TP_0 BPM1_0/TP_13# 15 USB OC connection;
20091230:TP8,TP9 TPS134 TP_1 BPM1_1/TP_12#
TP_2 16 11
change to Test Point; TPS135 18 TP_2 BPM1_2/TP_11# 9
follow CRB 0.7
TP_3
TPS136 TP_4 28 TP_3 BPM1_3/TP_10# 5
follow CRB 0.7 TPS137 30 TP_4 BPM1_4# 3
TP_5
TPS138 TP_6 34 TP_5 BPM1_5#
20091230:Add pull-up to TPS139 36 TP_6 35
TP_7
+1P05V_PCH; follow TPS140 TP_8 4 TP_7 BPM2_0#/TP_17 33
TPS141 6 TP_8 BPM2_1#/TP_16 29
TP_9
CRB 0.7 TPS142 TP_9 BPM2_2#/TP_15 27
*
RS200 0 F_SINAI_JTAG_VREF 40 BPM2_3#/TP_14

+1P05V_PCH 42 XDP_H_CLK_DP 60 +3V_S5
XDP_H_CLK_DN XDP_PRESENT#
[27] C_SRC1_PCH
45
47 100M_CLK_DP PROC_VTT_1
43
44
RS172* 0
B [27] C_SRC1_PCH# 100M_CLK_DN PROC_VTT_2 B
20091230: change to 0ohm 20091209: The stuffing table
51 1 20091221: updated JTAG stuffing table
[15,16,17,18,20,32] S_SMBDATA_MAIN 53 SDA GND1 2 pull-up to +3_DSW need update
[15,16,17,18,20,32] S_SMBCLK_MAIN SCL GND2 7
F_TP_XDP_PWRGD 39 GND3 8 +3V_S5
20091231: Add Dummy TPS120 46 PWRGOOD GND4 13
20100105: Mount RS175 and change to 0ohm; CRB 0.7
Dummy TPS121 F_TP_XDP_RST 20100709: Reserve RS207 for S_RSMRST# connect to
RS35 pull-up 48 RESET# GND5 14
*
[9,24,53] FP_RST# RS35 51 Ohm 41 DBR# GND6 19 F_TP_XDP_RST

to +1P05_PCH; +1P05V_PCH TESTINB GND7 20091221: RS184 change to 20k ;
20
CRB 0.7 52 GND8 25 Stuff-up RS177, RS178, RS185 follow
[24] F_PCH_JTAG_TDO 56 TDO GND9 26 RS175 * * 0 F_TP_XDP_RST
[24] F_PCH_JTAG_TDI 58 TDI GND10 31 [24,32,53,56] O_PWRBTN#IN JTAG Enable option.
[24] F_PCH_JTAG_TMS F_PCH_FILTER_TCK 57 TMS GND11 32
TCK GND12
*
***
*****
F_PCH_JTAG_RST# RS208 0 F_PCH_JTAG_RST#_R 54 37 RS176 1K RS177 200Ohm +/-5% F_PCH_JTAG_TDO RS178 100 Ohm +/-1%
Dummy
TRST# GND13 38 [9,24,32,34,46,53] S_PLTRST#
Dummy
21 GND14 49 RS179 200Ohm +/-5% F_PCH_JTAG_TDI RS180 100 Ohm +/-1%
20091209: 0.7 CRB has reserved a 0 NC_1 GND15
22 50
ohm and empty for JTAG_RST 23 NC_2 GND16 59 +3V_S5 RS181 200Ohm +/-5% F_PCH_JTAG_TMS RS182 100 Ohm +/-1%
24 NC_3 GND17 CLOSE TO PCH
20091221:connect to F_PCH_JTAG_RST# via RS208 55 NC_4 F_PCH_FILTER_TCK RS183 51 Ohm+/-5%
and removed TPS123 NC_5
*
20091221: Rename Dummy RS184 20K F_PCH_JTAG_RST# RS185 10K +/-1%
XDP
+/-1%
F_PCH_JTAG_RST#_NC to
*
F_PCH_JTAG_RST# [24]
F_PCH_JTAG_RST#_R RS186 0
+3V
20091231: RS188 cahnge to 1k and
A A
pullup to +3V_DSW; CRB 0.7
US2
* *
1 5 RS188 1K
NC VCC +3V_S5
*
F_PCH_FILTER_TCK RS187 0 2
Dummy A F_TP_XDP_PWRGD RS189 1K Title
3 4 RS190 PWRGD_3V [24,32]
140Ohm Dummy
GND Y Dummy +/-1% F_PCH_JTAG_TCK_FILTER [24]
*RS192 XDP
SN74LVC1G17DCKR RS191 CS69
Dummy * 0
* 0.1uF 0 DWG NO Rev
Dummy 16V, X7R, +/-10% A00
Dummy
Dummy
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
Power Bottom Reset Bottom

+3V_DUAL
* 1K
D RO99 For debugging D
20091209: change to
20091216: Signal name
O_PWRBTN#IN For debugging
*
change to O_PWRBTN#IN RO101 100 SYS_PWRBT#
*
[24,32,52,56] O_PWRBTN#IN
Dummy +/-5% 100 Ohm
[9,24,52] FP_RST#
RO102 +/-1%
5
1 2
3 4 1 2
CONN-Switch * CO49
470pF 3 4 CONN-Switch
PWR_SWH 50V, X7R, +/-10%
6
RST_SWH
6
Dummy
Dummy
C C
LPC DEBUG
+3V +5V
For debugging
LPC_DEBUG
Dummy
*
**
RF24 0 1 2 RF25 0
[27,46] C_LPC_TPM 3 4 S_INIT3_3VB [23]
+/-5% Dummy
[9,24,32,34,46,52] S_PLTRST# 5 6 RF26 0
[24,32,46] F_LAD0 7 8 F_LPC_DEBUG [21] +5V
Dummy +3V
[24,32,46] F_LAD1 9
[24,32,46] F_LAD2 11 X 12
[24,32,46] F_LAD3 13 14
[24,32,46] F_FRAME#
Header_2X7_K10 * CF13
0.1uF * CF14
0.1uF
Dummy 16V, X7R, +/-10% 16V, X7R, +/-10%
CF15
22pF * CF16
10nF
50V, NPO, +/-5% 25V, X7R, +/-10%
B B
Dummy
A A
Title
Pilot Run Conn

DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1

Dummy +5V_DUAL_USBKB Dummy FD1 FD2 FD3 FD4
IMPEDANCE_1 IMPEDANCE_2 FMARK FMARK FMARK FMARK
1 1 FD40 FD40 FD40 FD40
2 2
Header_1X2 Header_1X2
1
Dummy +5V_DUAL_USBKB Dummy
IMPEDANCE_3 IMPEDANCE_4
D 1 1 D
2 2 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy
FD5 FD6 FD7 FD8 FD9 FD10 FD11 FD12
Header_1X2 Header_1X2 FMARK FMARK FMARK FMARK FMARK FMARK FMARK FMARK
FD40 FD40 FD40 FD40 FD40 FD40 FD40 FD40
Dummy
Dummy IMPEDANCE_6
1
IMPEDANCE_5 1
DIFF_5/5+ 1 2
DIFF_5/5- 2
Header_1X2
Header_1X2
MH1 MH2 MH3 MH4 MH5 MH6 MH7 MH8

Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole
6
5
6
5
6
5
6
5
6
5
6
5
6
5
6
5
7 4 7 4 7 4 7 4 7 4 7 4 7 4 7 4
8 3 8 3 8 3 8 3 8 3 8 3 8 3 8 3
9 2 9 2 9 2 9 2 9 2 9 2 9 2 9 2
1
1
C mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell C
A_GND
20100108: Add for EMI
+5V
+3V
+1P05V_VCCIO +1P05V_VCCIO +1P05V_VCCIO +5V +3V +3V
* CP222
* CP224
* CP225
* CP228
* CP237
* CP236 * CP238
0.1uF
* CP242
0.1uF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 16V, X7R, +/-10% 16V, X7R, +/-10%
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
+3V +1P05V_PCH
+12V
A_GND +5V
+3V +5V
+5V +3V +3V +3V +5V +5V +1P05V_ME
B B
* CP229
0.1uF
* CP230
0.1uF
* CP231
0.1uF
* CP232
0.1uF
* CP234
* CP233
* CP235
* CP240
* CP247
* CP251
* CP249
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
+3V +3V
+3V +3V +5V +12V +12V
+5V_DUAL_USBKB +5V_DUAL_USBKB +5V_DUAL_USBKB +5V_DUAL_USBKB * CP291

0.1uF * CP276
0.1uF * CP255
0.1uF * CP250
0.1uF * CP248
0.1uF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
Dummy Dummy
* CP285
0.1uF * CP268
0.1uF * CP246
0.1uF * CP244
0.1uF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
A A
Title
EMI
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
D D
Move PWR_SW conn to

page56 20091126
C C
Serial Port 2 Header
+3V
RO93 RO94 RO95 RO96 RO97

B * * * * * B
2.2K 2.2K 2.2K 2.2K 2.2K

+/-5% +/-5% +/-5% +/-5% +/-5%
O_DCD2#_R
O_DSR2#_R
O_RXD2_R
O_CTS2#_R
O_RI2#_R
+5V +12V -12V
SERIAL2
A
1 2 +12V -12V +5V A
[32] O_DCD2#_R 3 4
[32] O_DSR2#_R 5 6
[32] O_RXD2_R 7 8
* CO44
* CO45
* CO46
*
[32] O_RTS2#_R 9 10 0.1uF 0.1uF 0.1uF

RO33 0 +/-5%
[32,33] O_TXD2_R 11 12 O_COM_SER2_DET# [24,27]
Dummy 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
[32] O_CTS2#_R 13 14 Dummy Dummy Dummy Title
[32,33] O_DTR2#_R O_RI2#_R [32]
COM2 HDR
* CO22
10pF
Header_2X7
Dummy DWG NO Rev
Dummy Dummy Serial Port2 header from X01 A00
50V, NPO, +/-5% Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
Front USB/LED Header +5V_DUAL_USBKB

+5V_DUAL_USBKB
+5V_DUAL_USBKB
*1
USBPWR5_F_50
*RU29
0 FU6
+/-5% Fuse 2A
*1
USBPWR3_F_50 Dummy
FU5
2
Fuse 2A
*
RU31 10K +/-1%
[22] U_USB_OC_R_#5
2
D 1 D
*
[22] U_USB_OC_R_#3
1
RU30 10K +/-1% CU14
0.1uF * RU33
15K
* ECU6
470uF * CU15
0.1uF
25V, X7R, +/-10% +/-1% 6.3V, +/-20% 16V, X7R, +/-10%
CU12
0.1uF * RU32
15K
* ECU5
470uF * CU13
0.1uF
2
25V, X7R, +/-10% +/-1% 6.3V, +/-20% 16V, X7R, +/-10%

2
**
RU34 0 Dummy U_USB6N_R
[22] U_USB6N RU35 0 Dummy U_USB6P_R
[22] U_USB6P
CU16
0.1uF
* * CU17
0.1uF
+3V +5V
16V, X7R, +/-10% FRONTPANEL 16V, X7R, +/-10%

**
RU36 0 Dummy U_USB7N_R

[22] U_USB7N
[22] U_USB7P
RU37 0 Dummy U_USB7P_R
[37] A_MIC1_L_L
1 2
A_MIC1_R_L [37]
RO105 * *RO104 MT/DT CHASSIS
3 4 0 0
[37] A_JD_MIC1 5 6 A_JD_FRONT [37]
Dummy
[37] A_FRONT_L_L 7 8 A_FRONT_R_L [37]
A_FP_PRES# [23] FP_CHAS_DET# MT/DT
**
RU38 0 Dummy U_USB10N_R 9 10

[22] U_USB10N RU39 0 Dummy U_USB10P_R [32] O_DIAG_LED3# 11 12
[22] U_USB10P [32] O_DIAG_LED1# 13 14 O_DIAG_LED4# [32] 0 MT
[35] L_FP_LAN_LED_GRN# O_FIO_SATA_LED# 15 16 FP_CHAS_DET# O_DIAG_LED2# [32] * CO50
0.1uF
1 DT
C 17 18 16V, X7R, +/-10% C
**
RU41 0 Dummy U_USB11N_R 19 20 U_USB11N_R

[22] U_USB11N RU42 0 Dummy U_USB11P_R U_USB11P_R 21 22
[22] U_USB11P U_USB10P_R 23 24 U_USB10N_R
25 26 U_USB7N_R
U_USB7P_R 27 28
31 32
UU5
33 34
A_FP_PRES# [23]
Header_2X17
2 5
USBPWR5_F_50
* CA40
*
U_USB10N_R 3 4 U_USB10P_R 0.1uF FP_CHAS_DET# RU40 0 +/-5%
S_FP_CHAS_DET# [23]
16V, X7R, +/-10% Pitch 2.0mm
IP4223CZ6 20100111: Swap N/P net
for routing +3V

UU6
O_FIO_SATA_LED#
L_FP_LAN_LED_GRN# RNO2 O_DIAG_LED1#
2
4
6
8
*
2 5 8.2KOhm RO71 1K O_DIAG_LED2#
USBPWR3_F_50 [23] T_SATALED#
CO28
* CO53
* +/-5% O_DIAG_LED3#
* 13
5
7
U_USB6P_R 3 4 U_USB6N_R 470pF 470pF O_FIO_SATA_LED# O_DIAG_LED4#
50V, X7R, +/-10%

+5VSB Dummy
3
50V, X7R, +/-10%
CNO2
B IP4223CZ6 B
O_FIO_SATA_LED# 180pF
stuff on 20100723-EMC request * CO26

0.1uF T_SATALED# * 50V, NPO, +/-10%
Dummy
16V, X7R, +/-10% QO10
OQ14_C MMDT5551
4
LU9 OQ14_C
U_USB6N_R 1 4 FP_CHAS_DET#
U_USB6N [22]
U_USB6P_R 2 3
U_USB6P [22]
Common Choke 90 Ohm
LU10
U_USB7N_R 1 4
U_USB7N [22]
U_USB7P_R 2 3
U_USB7P [22]
POWER SWITCH Header +3V_DUAL
Common Choke 90 Ohm

+5VSB +5VSB
CO-LAY with 4 Serial resistors RU34, RU35, RU36, & RU37
*RO70
8.2K
LU11
U_USB10P_R 1 4
U_USB10P [22]
RO34 * *RO37
499 O_FP_CBL_DET#
+/-5%
499 +/-1%
U_USB10N_R 2 3 +/-1% O_GREEN#
U_USB10N [22] O_YELLOW#
A Common Choke 90 Ohm PWR_SW O_PWRBTN#IN A
**
RO67 100 +/-5% 1 2

[24,32,52,53] O_PWRBTN#IN 3 4
LU12
[32] O_GREEN#
RO30 0 +/-5%
O_FP_CBL_DET# [32]
CO27
* CO54
* CO52
*
*
U_USB11N_R 1 4 6 RO29 0 +/-5% 470pF 470pF 470pF

U_USB11N [22] X O_YELLOW# [32]
5 0V, X7R, +/-10%

Dummy Dummy
50V, X7R, +/-10%
50V, X7R, +/-10%

U_USB11P_R 2 3 Title
U_USB11P [22] Header_2X3
Common Choke 90 Ohm Front_Panel
CO-LAY with 4 Serial resistors RU38, RU39, RU41, &RU42 DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+5V For pci slot used

IRQ: CDAB
IDSEL: AD18 RNK3
REQ/GNT: 0
*1 2
K_TDI
K_TMS
3 4 K_TCK
D
5 6 K_TRST D
+3V +5V -12V +12V +5V +3V +3V_PCIAUX
7 8
4.7K Ohm
SLOT3 +/-5%
B1 A1 K_TRST
K_TCK B2 -12V TRST# A2
TCK +12V Moved from PCH section-12/30/09
B3 A3 K_TMS
B4 GND1 TMS A4 K_TDI
B5 TDO TDI A5
B6 +5V1 +5V2 A6
B7 +5V3 INTA# A7 K_INTC# [21]
[21] K_INTD# B8 INTB# INTC# A8 K_INTA# [21]
[21] K_INTB# B9 INTD# +5V4 A9
B10 PRSNT1# RSV1 A10
B11 RSV2 +5V5 A11
B12 PRSNT2# RSV3 A12
B13 GND2 GND3 A13
B14 GND4 GND5 A14
B15 RSV4 SB3V A15 K_AD[31..0] [21]
B16 GND6 RESET# A16 K_PCIRST#_SLOT [21]
[27] C_PCI_SL1 B17 CLK +5V6 A17 K_C/BE#[3..0] [21]
B18 GND7 GNT# A18 K_GNT#0 [21]
[21] K_REQ#0 B19 REQ# GND8 A19
B20 +5V7 PCI_PME# A20 K_PME# [21]
K_AD31 K_AD30
K_AD29 B21 AD(31) AD(30) A21
B22 AD(29) +3.3V1 A22 K_AD28
K_AD27 B23 GND9 AD(28) A23 K_AD26
K_AD25 B24 AD(27) AD(26) A24
B25 AD(25) GND10 A25 K_AD24
*
C K_C/BE#3 B26 +3.3V2 AD(24) A26 RK1 330 K_AD18 C
K_AD23 B27 C/BE#(3) IDSEL A27 +/-1%
B28 AD(23) +3.3V3 A28 K_AD22
K_AD21 B29 GND11 AD(22) A29 K_AD20
K_AD19 B30 AD(21) AD(20) A30
B31 AD(19) GND12 A31 K_AD18
K_AD17 B32 +3.3V4 AD(18) A32 K_AD16
K_C/BE#2 B33 AD(17) AD(16) A33
B34 C/BE#(2) +3.3V5 A34
GND13 FRAME# K_FRAME# [21]
K_IRDY# B35 A35
[21] K_IRDY# B36 IRDY# GND14 A36
K_DEVSEL# B37 +3.3V6 TRDY# A37 K_TRDY# [21]
[21] K_DEVSEL# B38 DEVSEL# GND15 A38
K_LOCK# B39 GND16 STOP# A39 K_STOP# [21]
LOCK# +3.3V7
**
[21] K_LOCK# B40 A40
K_PERR# RK4 0 Dummy
[21] K_PERR# B41 PERR# SDONE A41 RK5 0 Dummy
S_SMBCLK_PCI [13,16,18,24,32,38,39,59]
B42 +3.3V8 SBO# A42 S_SMBDATA_PCI [13,16,18,24,32,38,39,59]
K_SERR#
[21] K_SERR# B43 SERR# GND17 A43
B44 +3.3V9 PAR A44 K_PAR [21]
K_C/BE#1 K_AD15
K_AD14 B45 C/BE#(1) AD(15) A45
B46 AD(14) +3.3V10 A46 K_AD13
K_AD12 B47 GND18 AD(13) A47 K_AD11
K_AD10 B48 AD(12) AD(11) A48
B49 AD(10) GND19 A49 K_AD9
GND20 AD(9)
K_AD8 B52 A52 K_C/BE#0

K_AD7 B53 AD(8) C/BE#(0) A53
B54 AD(7) +3.3V11 A54 K_AD6
B
K_AD5 B55 +3.3V12 AD(6) A55 K_AD4 B
K_AD3 B56 AD(5) AD(4) A56
B57 AD(3) GND21 A57 K_AD2
+5V K_AD1 B58 GND22 AD(2) A58 K_AD0 +5V
B59 AD(1) AD(0) A59
RK2 2.7K B60 +5V8 +5V9 A60 RK3 2.7K
B61 ACK64# REQ64# A61
B62 +5V10 +5V11 A62
+5V12 +5V13
Slot-PCI
+5V
ECK1 ECK2 CK1 CK2 CK3 CK4

1
* 470uF *
6.3V, +/-20%
120uF
16V, +/-20% * 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10%
Dummy Dummy Dummy Dummy Dummy
2
+3V +12V -12V +3V_PCIAUX

A A
ECK3 CK5 CK6 CK7 CK8 ECK4 CK9 CK10

1
* 470uF
*
6.3V, +/-20%
0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * 0.1uF
25V, Y5V, +80%/-20%
* 120uF
16V, +/-20% * 0.1uF
25V, Y5V, +80%/-20% * 0.1uF
16V, X7R, +/-10%
Title
2
Slot3: PCI
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+3V
D D
***
RX17 4.7K +/-5% X1_TDI
RX18 4.7K +/-5% X1_TRST
RX19 4.7K +/-5% X1_TCLK
+3V_PCIAUX +3V
+12V +12V +3V
SLOT2
B1 A1
B2 +12V#B1 PRSNT1# A2
B3 +12V#B2 +12V#A2 A3
B4 RSVD#B3 +12V#A3 A4
**
RX6 0 Dummy B5 GND#B4 GND#A4 A5 X1_TRST
[13,16,18,24,32,38,39,58] S_SMBCLK_PCI RX5 0 Dummy B6 SMCLK JTAG2 A6 X1_TDI
[13,16,18,24,32,38,39,58] S_SMBDATA_PCI B7 SMDAT JATG3 A7
GND#B7 JATG4 20100111: Remove net X_WIRELESS_LED#
B8 A8
B9 +3.3V#B8 JATG5 A9 GPO_WLOM [22]
X1_TCLK
B10 JTAG1 +3.3V#A9 A10
B11 3.3Vaux +3.3V#A10 A11
[24] X1_WAKE# WAKE# PERST# X_PLTRST_PCIE_SLOT# [32,38,39]
B12 Mechanical Key A12
B13 RSVD#B12 GND#A12 A13
CX51 0.1uF 16V, X7R, +/-10% X_2X1_TXP_C B14 GND#B13 REFCLK+ A14 C_PCIEX1_2 [27]
**
[22] X_2X1_TXP CX52 0.1uF 16V, X7R, +/-10% X_2X1_TXN_C B15 PETp0 REFCLK- A15 C_PCIEX1#_2 [27]
C [22] X_2X1_TXN B16 PETn0 GND#A15 A16 C
B17 GND#B16 PERp0 A17 X_2X1_RXP [22]
B18 PRSNT2#B17 PERn0 A18 X_2X1_RXN [22]
GND#B18 GND#A18
Slot-PCIE-1X
+3V +3V_PCIAUX
CX53 CX54 CX55

B B
* 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10%
Dummy Dummy Dummy
A A
Title
Slot2: PCIe 1x
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
SATA port 3 only for MT

SATA3
** **

@MT
@MT
8
@MT
A CT16 10nF 25V, X7R, +/-10% T_SATA_RXP3_C 6 A
[23] T_SATA_RXP3 @MT RX+ 9
NC#9
1
4 GND
7 GND#4
GND#7 Title
CONN-SATA
@MT SATA_MT
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
FLEXBAY
D D
+5V_DUAL_USBKB
*1
FU4 USBPWR4_F_50
Fuse 2A
2
*
RU19 10K +/-1%
[22] U_USB_OC_R_#4
1
CU10
0.1uF * RU20
15K
* ECU4
470uF * CU11
0.1uF
25V, X7R, +/-10% +/-1% 6.3V, +/-20% 16V, X7R, +/-10%
2
INT_USB
20091209: Stuff RU22
1 2
**
**
Dummy RU21 0 +/-5% U_USB8N_R 3 4 U_USB9N_R RU22 0 +/-5% Dummy and RU24
[22] U_USB8N Dummy RU23 0 +/-5% U_USB8P_R 5 6 U_USB9P_R RU24 0 +/-5% Dummy U_USB9N [22]
[22] U_USB8P 7 8 U_USB9P [22]
10
C X S_FLEXBAY_HDR_CBL_DET# [24,27] C
Header_2X5_K9
Pitch 2.54mm
LU7
U_USB8N_R 1 4
U_USB8N [22]
U_USB8P_R 2 3
U_USB8P [22]
Common Choke 90 Ohm
B B
UU4
U_USB9N_R 1 6 U_USB9P_R LU8
U_USB9N_R 1 4
2 5 U_USB9N [22]
USBPWR4_F_50
U_USB9P_R 2 3
U_USB8P_R 3 4 U_USB8N_R U_USB9P [22]
Common Choke 90 Ohm
IP4223CZ6
CO-LAY with 4 Serial resistors RU21, RU22, RU23, & RU24

A A
Title
Flexbay USB
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
Print Port
PARALLEL
O_STB#_R 1 2 O_AFD#_R
D O_PD0_R 3 1 2 4 O_ERR# D
O_PD1_R 5 3 4 6 O_INIT_R
O_PD2_R 7 5 6 8 O_SLIN#_R
O_PD3_R 9 7 8 10
O_PD4_R 11 9 10 12 O_PRT_DET# [23]
O_PD5_R 13 11 12 14
O_PD6_R 15 13 14
O_PD7_R 17 15 18
O_ACK# 19 17 18 20
O_BUSY 21 19 20 22
O_PE 23 21 22 24
O_SLCT 25 23 24 26
25 26
Header_2X13_K16
Dummy
Dummy Print Port Header from X01
+5V
DO4
C C A C
RNO4 RNO5 RNO6 RNO7

1N4148W
* CO47
0.1uF
*
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
1K RO98 1K 1K 1K 16V, X7R, +/-10%
+/-5% 1K
+/-5% +/-5% +/-5%
*1
3
5
7
* 13
5
7
* 13
5
7
*1
3
5
7
Dummy Dummy Dummy
O_PD0_R O_PD4_R
O_ACK# O_PD1_R O_PD5_R
[32] O_ACK#
O_BUSY O_PD2_R O_PD6_R
[32] O_BUSY O_PE O_PD3_R O_PD7_R
[32] O_PE
O_SLCT
[32] O_SLCT
CNO7
220pF O_PD[7..0] RNO8 33
[32] O_PD[7..0]
50V, NPO, +/-10% O_PD0 +/-5% O_PD0_R
* Dummy O_PD1 8
6
7
5
O_PD1_R
O_PD2 O_PD2_R
O_PD3 4 3 * O_PD3_R
RNO10 2 1 Dummy
O_PD4
O_PD5
*1 2
O_PD4_R
O_PD5_R
B
O_PD6 3 4 O_PD6_R B
RNO9 O_PD7 5 6 O_PD7_R

*1 O_STB#_R 33 7 8 +/-5%
[32] O_STB# 2 O_AFD#_R Dummy
[32] O_AFD# 3 4 O_INIT_R CNO8 CNO9
[32] O_INIT# 5 6 O_SLIN#_R 220pF 220pF
[32] O_SLIN#
Dummy 7 8 50V, NPO, +/-10% 50V, NPO, +/-10%
[32] O_ERR#
33 +/-5% O_ERR# * Dummy * Dummy
CNO6
220pF * CO48
220pF
50V, NPO, +/-10% 50V, NPO, +/-5%
* Dummy Dummy
A A
Title
PRT Port
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
ATX POWER CONNECTOR
+5VSB -12V +5V +3V

D +3V +5V +12V +5VSB +5V D
RP3 POWER
* 4.7K 13
+3.3V3 +3.3V1
1 *RP1
+/-5% 14 2 1K
15 -12V +3.3V2 3
16 GND4 GND1 4 +/-1%
[32,70] O_PSON# 17 PSON +5V1 5
18 GND5 GND2 6
19 GND6 +5V2 7
20 GND7 GND3 8
21 RSVD PWR0K 9 B_ATX_PWROK [32,70]
* CP3
0.1uF 22 +5V3 +5V_AUX 10
16V, X7R, +/-10% 23 +5V4 +12V_1 11
24 +5V5 +12V_2 12
Dummy
GND8 +3.3V4 * CP1
0.1uF
ATX_2X12 16V, X7R, +/-10%
*RP4 Dummy
Change to 4.2mm for 330
+/-1% Dummy for cost
cost down-11/23
Dummy
A
down-11/23/09
AUX_PWR
LED_Yellow
Dummy
C
C C
Dummy for cost Dummy for cost

down-11/23/09 down-11/23/09
-12V +12V
+5V +3V +5VSB
+3V
* CP4
0.1uF * CP5
0.1uF * CP6
0.1uF * CP7
0.1uF * CP8
0.1uF
* ECP1
470uF * CP9
0.1uF * CP10
0.1uF * CP11
0.1uF
* ECP2
470uF
* ECP3
470uF
* ECP4
470uF
25V, X7R, +/-10% 25V, X7R, +/-10% 25V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 6.3V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 6.3V, +/-20% 6.3V, +/-20% 6.3V, +/-20%
Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy
B B
A A
Title
Power Conn
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+5VSB
+5VSB
For Deep Sleep
* RP666
4.7K
+5V_DUAL
*
*
RP669
S_SU S_PWR_ACK# [24]
10K
C
RP670 RP675 CP522
* * *
*
RP673 B 0 20K 0.1uF
10K QP93 16V, Y5V, +80%/-20%
C
D +5VSB D
RP674 MMBT3904-7-F Dum m y
*
E
B 10K RP677
QP100 10K
+5VSB RP679
* RP684
* CP524 MMBT3904-7-F Dum m y
E
1K 10K 0.1uF
*
*
RP678 +/-1% Dum m y
[24] S_SU SWARN# S_SU S_PWR_ACK# [24]
10K Dum m y
RP695
16V, Y5V, +80%/-20%

* RP680 SU S_ACK_CTRL 0
Dum m y
1K
C
*
SU S_WARN_5VDUAL B QP94
MMBT3904-7-F
C
RP681
E
*
B QP99 10K
[24] S_SU SWARN# MMBT3904-7-F
RP682 RP683
*
E
+5VSB 10K 5.6K
S_RSMRST#_R
SLP_SUS_R
QP76
*
D
RP685 2N7002
1K
G
C
S
*
B QP96
[24,65] S_SLP_SU S# MMBT3904-7-F
C C
RP687
E
4.7K
RESUME RESET Logic VR_READY DEFENSIVE
*
+5VSB +5VSB +5VSB +5VSB +5VSB
[20,24,32,66,69,70] S_SLP_S3# P_CORE_EN [67]
1 RP16 CP12
1
+3V_S5 10K 1uF
RP273 1 1 1 * 25V,X7R,+/-10%
22K Dum m y
*
2
+/-5% RP277 RP280 RP282 RP284
RP710 2 22K 0 22K 22K RP287
* 1K +/-5% +/-5% +/-5% 0
**
Dum m y 2 2 2 QP6
SLP_SU S_FET [65]
3
+3V_DUAL MMDT5551
E
RP279 RP283 +3V_S5
S_RSMRST# [24]
4
*
*
B B
S_RSMRST# [24] MMDT5551
QP18 RP289
1
QP17 10K MMBT3906 QP20 10K 10K
* * *
C
C
B B
+3V_S5 RP709 MMBT3906 RP19 RP17
*
4
10K 1 2 QP27 RP288 10K 10K

[24,65] S_SLP_SU S#
Dum m y CP529 CP530 MMDT5551 4.7K
*
C
*
1
RP274 RP278 RP281 +/-5%

RP708 B QP58 22K * RP275 * RP276 1M * 1uF
* 2.2uF
* 18K Dum m y
20100715 update
6
68KOhm MMBT3904-7-F +/-5% 1M 1M +/-5% +/-1% RP18
2
25V,X7R,+/-10%
+/-1% Dum m y +/-5% +/-5% Dum m y 6.3V, Y5V, +80%/-20% 10K

E
*
Dum m y Dum m y Dum m y
C
1 2 P_VR_READY [20,24,33,52,67]
[24,65] S_SLP_SU S#
3
S_RSMRST#_R B QP57 1 RP20
MMBT3904-7-F RP285 RP286 100 Ohm
Dum m y Dum m y 22K 15K +/-1%
E
1
CP528 +/-5% +/-1% QP7

* 1uF
2
MMDT5551
2
4
25V,X7R,+/-10%
*
+3V_DUAL
[9,24,52] H_PWRGD
RP21
100 Ohm
+/-1% * RP23
Dum m y
+3V_S5
* CP269
0.1uF
10K
16V, X7R, +/-10%

5
RP711 UP3
* 24.9KOhm
1
VCC
+/-1%
A OE# A
*
4 RP290 33
S_RSMRST# [24]
Y
S_RSMRST#_R 2
A
CP282 GND
Title
* 1uF SN 74LVC1G17DCKR
3
+/-10%
Power Sequence
DWG NO Rev
A00
Gold Coast_MT/DT
Date: Friday, Decem ber 24, 2010 Sheet 64 of 70
5 4 3 2 1
5 4 3 2 1
+3V_S5 +3V_S5
+3V_EPW +2.5V Ref for OP(UP1) +12V
+3V +3V_S5
*RP24 +2_5V_REF
10K
S
CP27 CP42 RP173
* * *
*
G 4.7uF 0.1uF 82.5Ohm
QP8 Dummy Dummy +/-1% *RP174
82.5Ohm
C
RP26 FDN340P +/-1%
6.3V, X5R, +/-10%
16V, X7R, +/-10%

*
*
B 0 B QP49
D [24,32,66] S_SLP_M# QP10
Dummy
[70] 5VDUAL_S3#O MMBT3904-7-F *RP177
0 D
D
1
1
RP27 CP18 MMBT3904-7-F CP16 +3V_EPW RP175 Dummy
* *
E
+3V_S5 10K 1uF 1uF 2 1K
Dummy CP194 CP195 +/-1%
* *
25V,X7R,+/-10%
2
2
10uF 1nF UP13 RP176
25V,X7R,+/-10%
TL431CDBZR 33 Ohm * +12V_UP1
6.3V,X5R,+/-10%
* RP211
50V, X7R, +/-10%
3
CP156 +/-1%
4.7uF
0
Dummy
* Dummy
6.3V, X5R, +/-10%
+3V_EPW
20100709: Reserve RP210 connect +3V_S5 to +3V_EPW
+5VSB
+3V_DUAL
*RP667
10K
Dummy
RP668
*
*
C
10K SLP_SUS_FET_R SLP_SUS_FET C
Dummy
C
RP672 CP523
*
*
B QP95 1K 0.47uF
[24,64] S_SLP_SUS#
MMBT3904-7-F 10V, X5R, +/-10%
+3V_PCIAUX(FOR PCI/PCIE SLOT)
Dummy
RP676 Dummy Dummy
E
4.7K
Dummy +5VSB +3V_S5 +3V_PCIAUX
+3V_S5 +3V_DUAL
*RP170
10K Dummy
CP132 CP45 RP172
* 0.1uF * 4.7uF 0
S
Dummy
G G CP43 CP44
SLP_SUS_FET
* *
6.3V, X5R, +/-10%

16V, X7R, +/-10%
[64] SLP_SUS_FET
RP178 4.7uF 0.1uF
QP50 QP53 0 Dummy Dummy
FDN340P FDN340P Dummy
6.3V, X5R, +/-10%
16V, X7R, +/-10%

Dummy
D
S
B +3V_S5 B
*
G
QP73
D
RP171 FDN340P
CP157
20K
+/-1% *CP145
1K
+/-5% *
CP151
4.7uF
*
CP152
22uF
D
4.7uF G QP71 Dummy
*
6.3V, X5R, +/-10%

Dummy [24,32,70] S_SLP_S4#
2N7002
6.3V,X5R,+/-20%
1
+5VSB 6.3V, X5R, +/-10% CP144
+5V_S5 *
S
1uF
25V,X7R,+/-10%
CP146 CP130
* 4.7uF * 0.1uF
D
RP262 Dummy Dummy
S
0
6.3V, X5R, +/-10%
16V, X7R, +/-10%
SLP_SUS_FET G Dummy
G QP72
[24] S_PCIAUX_GATE
2N7002
QP61
S
FDN340P +5V_S5
D
A A
Title
CP120
* 4.7uF Power-1:Linear Power-1

Dummy
6.3V, X5R, +/-10% DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+1P05V_ME
+V_1.05_PCH +V_1.05_ME LP1
80mil
P_1P05V_ME_LX_80
*
+5V_S5
+2_5V_REF +12V_UP1 1uH 1.05V/1.8A
+1P5V_SM +1P5V_SM
* CP22
22uF * CP23
22uF * CP26
10uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
RP32 CP24 CP25 8 3
* 13.7K
* 4.7uF
* 0.1uF CP28 CP29 VDD LX1
D
22uF 0.1uF 7 4
+/-1% QP11 Dum m y
* *
8
AOD452 Dum m y PVDD2 LX2 RP33
6.3V, X5R, +/-10%
*
6 9
6.3V,X5R,+/-20%
5
16V, X7R, +/-10%

P_1P05V_PC H_ADJ 16V, X7R, +/-10% P_1P05V_ME_FB
+ 7 P_1P05V_PC H_OUT G PVDD1 FB
6 1 10 1P05V_ME_COMP 75K RP34
1
D - SHDN/RT COMP D
RP35 CP30 UP1B P_1P05V_ME_EN RP36 +/-1% 0
* * *
S
10K 1uF LM358 2 11 27.4K
*
+/-1% RP38 GND EP_GND +/-1%
*
P_1P05V_PCH_COMP
2
*
25V,X7R,+/-10% 330KOhm 5 CP31
+/-1% PGND 33pF
RP37 1.065V/6.2A UP2
* * RP39 50V, NPO, +/-5%
*
1K RT8015AGQW CP33 240KOhm
*
C P32 +/-1% +1P05V_PC H 1nF +/-1%
RP40 1nF RT8015A_GND RT8015A_GND
0 50V, X7R, +/-10% CPP14
240mil
50V, X7R, +/-10%

*
RT8015A_GND RT8015A_GND 2 1
RP41 COPPER
1K CP34 CP35 EC P6 Dum m y
+/-1%
* 0.1uF
* 4.7uF * 1000uF
6.3v, +/-20%
+5V_S5
16V, X7R, +/-10%

RT8015A_GND
6.3V, X5R, +/-10%

+V_1.05_ME
RP43
ENABLE CIRCUIT * CP36
RP42
10K
+/-1% * 0.1uF
*
E
10K +/-1% 16V, X7R, +/-10%
*
+/-1% 2.2KOhm B QP12
C
RP45 MMBT3906
*
B RP44
C
1K
QP13
E
RP46 MMBT3904-7-F
* 10K P_1P05V_ME_EN
C +5V_S5 +/-1% C
+3V_S5
+V_1.05_PCH P_1P05V_PC H_ADJ +1P05V_PC H +1P05V_ME
ENABLE CIRCUIT * RP47 RNP1 RP57 RP55
10K *
1 2 * 1K * 10K
D
3 4 +/-1% +/-1%
5 6 Dum m y
C
QP15 7 8
*
B G 2N7002
[20,24,32,64,69,70] S_SLP_S3#
1
QP16 0
RP48 MMBT3904-7-F +/-5% QP14
E
10K Dum m y MMDT5551
6
RP49
PC H_MEPWRGD
[24,32,65] S_SLP_M#
2
CP37
10K * 1uF
+/-1% Dum m y
1
25V,X7R,+/-10%
+V_1P8_SFR
B +3V_EPW B
+2_5V_REF +12V_UP1 +3V +3V_S5
RP50
*
1
RP25 CP13 0
* 3.83KOhm * 1uF Dum m y
* RP51
D
+/-1% 25V,X7R,+/-10% QP9

* CP14
* CP15 0
2
8
AOD452 4.7uF 0.1uF

1P8V_SFR_ADJ 3 6.3V, X5R, +/-10% 16V, X7R, +/-10% RP52
+ 1 1P8V_SFR_OUT G Dum m y 33K RP53
2 +/-5% * 5.6K
1
RP28 CP17 - UP1A

* * +/-1%
S
10K 1uF LM358

4
+/-1% PC H_MEPWRGD
2
PC H_MEPWRGD [23]
25V,X7R,+/-10%
+1P05V_ME CP41
RP29 100pF CP38
1.812V/1.8A *
1P8V_SFR_COMP
1K 0.1uF
* *
*
4
50V, NPO, +/-5%
+/-1%
*
16V, X7R, +/-10%

+1P8V_SFR RP54 RP56 CP40
RP30 CP19
80mil 30.1KOhm *301KOhm
* 0.47uF QP19
0 1nF +/-1% MMDT5551
10V, X5R, +/-10%

50V, X7R, +/-10%
*
3
RP31
1K EC P5
+/-1%
* CP20
0.1uF * CP21
10uF
* 220uF
16V, +/-20%
20091209:
CRB0.7
6.3V,X5R,+/-10%
16V, X7R, +/-10%
A A
USED 301k
ohm
20091216: RP56 follow
CRB0.7 usage 301k ohm
Title
Power-2:Linear Power-2
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+1P05V_VCCIO
Sugar Bay VR12 POWER - 4+1 PHASE
+3V
+12V_CPU PWM ADDRESS
*RP59 +5V +1P05V_VCCIO
VCC_CORE 1K
+/-5% Dummy
*RP58
1.1KOhm
0
RP239 RP60 *RP61 RESISTOR
SVID
ADDRESS FOR
SVID
ADDRESS FOR
* *
+/-1% VCCIO_PWRGD [69] 2.2 1K
+/-5% +/-1% VALUE VCORE RAIL V_GT RAIL
D P_CORE_EN [64] CP51 CP48
* *RP137 *RP62
110Ohm *RP63
54.9 *RP64
91 Ohm 10K 0000 0001 D
CP47 4.7uF 10nF 1K Dummy +/-1% +/-1% +/-1%
0.1uF RP235 * 10V,X7R,+/-10% 50V,X7R,+/-10% +/-1% Dummy 25K 0010 0011
* Dummy * CP46 0
0.1uF NCP6151_GND 45K 0100 0101
10
12
16V, X7R, +/-10%
16V, X7R, +/-10% UP4 NCP6151_GND
4 70K 0110 0111
VCC
VRMP
SD IO H_VIDSOUT [9]
9 5
EN ABLE SC LK H_VIDSCLK [9]
RP65 6 95K 1000 1001
ALER T# H_VIDALERT# [9]
* 0
P_VR_READY VR_RDY 7 33
[20,24,33,52,64] P_VR_READY VR_RDY DRON 32 P_DRVON [68] 125K 1010 1011
DIFFOUT 52 PWM1/ADD R 35 P_CSN1 P_PWM1 [68]
165K 1100 1101
* * * * * * * *
DIFFOUT CSN 1 34 P_CSN1 [68]
P_CSP1
*RP70 CP80 RP71 CP82 RP69
* CP204
*
48 CSP1 P_CSP1 [68]
680pF 3.01K 2.2nF COMP RP72 100KOhm 0.1uF
*
50V, X7R, +/-10% +/-1% 50V, X7R,+/-10% COMP NCP6151S52MNR2G P_CSP1 +/-1% Dummy
47 RP73 CP53 CP49 47nF Dummy 16V, X7R, +/-10%
*
+/-5% 68pF 30 7.87K 16V,X7R,+/-10%
PWM2/VBOOT P_PWM2 [68]
*
50V,NPO,+/-5% FB 49 39 +/-1% NCP6151_GND P_CSN2
P_CSN2 [68]
*
1K FB CSN 2 38 P_CSP2
+VCORE RP74 CP52 RP75
* CP205
P_CSP2 [68]
*
+/-1% RP181 RP66 402 Ohm RP67 4.7nF CSP2 RP68 100KOhm 0.1uF
*
*
+/-1% TRBST 50 P_CSP2 +/-1% Dummy
BOOT VOLTAGE
50V, X7R, +/-10%

TRBST CP58 47nF Dummy
* RP76 NCP6151_GND 182K 24.9KOhm * CP90 1.2KOhm
PWM3/IMAX
31 7.87K 16V,X7R,+/-10%
16V, X7R, +/-10%
P_PWM3 [68]
100 Ohm +/-1% +/-1% 5.6nF +/-1% 37 +/-1% NCP6151_GND P_CSN3
CSN 3 36 P_CSN3 [68]
+/-1% Dummy 50V,X7R,+/-10%
CSP3
RP77
* CP206 P_CSP3
P_CSP3 [68] RESISTOR BOOT
*
NCP6151_GND VSP 1 RP79 100KOhm 0.1uF

VALUE VOLTAGE
*
[9] H_VCC_SENSE VSP P_CSP3
CP50
RP78 * 1nF CP54
+/-1%
47nF Dummy
Dummy
16V, X7R, +/-10%
0 Dummy 51 29 7.87K 16V,X7R,+/-10% +5V 10K
[9] H_VSS_SENSE VSN PWM4 40 P_CSN4
P_PWM4 [68] 0V
CP55 50V, X7R, +/-10% +/-1% NCP6151_GND
C * RP80 * 0.1uF
Dummy * CP56
0.1uF
CSN 4
CSP4
41
RP82
RP81
100KOhm * CP223
0.1uF
P_CSP4
P_CSN4
P_CSP4
[68]
[68] 3PHASE 25K 0.85V C
100 Ohm OPTION
*
16V, X7R, +/-10% Dummy P_CSP4 +/-1% Dummy 45K 0.9V
+/-1%
16V, X7R, +/-10% CP57 47nF Dummy 16V, X7R, +/-10% RP83
7.87K 16V,X7R,+/-10% 0 * 70K 0.95V
*** * * ** *
RP88 NCP6151_GND NCP6151_GND NCP6151_GND 44 CSSUM +/-1% NCP6151_GND RP84 32.4K Ohm P_CSP1
Dummy
*
43 CSSUM +/-1%
+5V 95K 1V
* * * *
IOUT 45 CSCOMP RP85 39.2K RP86 80.6kohm RP87 32.4K Ohm P_CSP2
7X7 SINGLE CSC OMP
0 +/-1% RTP1 +/-1% +/-1% 125K 1.1V
ROW QFN P_CSP3
Dummy
** CP59 RP91 100K CP71 3.3nF RP89 32.4K Ohm
*
RP90 0.1uF +3V 40.2K +/-1% +/-10% +/-1% P_PWM4 165K 1.5V
T
26.7K 47 ILIM CP60 820pF RP92 32.4K Ohm P_CSP4
16V, X7R, +/-10%
+/-1% ILIM +/-10% +/-1%

+/-1% *RP188 CP61
*
RP95 RP96 1K 680pF RP94 10 Ohm P_CSN1
* 1K 3.83KOhm * +/-1% 50V, X7R, +/-10% +/-1%
P_CSN2
+/-5% VCORE PORTION +/-1% RP93 RP97 10 Ohm
P_PWM2 P_PWMA
NCP6151_GND CP62 * CP207
680pF
10 Ohm
+/-1% RP99
+/-1%
10 Ohm P_CSN3
46 DROOP
* 0.1uF 50V, X7R, +/-10% +/-1%
*
DROOP RP98 8.45K RP100 10 Ohm P_CSN4
Dummy
16V, X7R, +/-10% 42 CSREF +/-1% +/-1%
CSR EF CP63
* VCORE
*RP102 V_GT
*RP103
*
P_VR_READY VR_RDYA 8 1nF 10K 27.4K

VR_RDYA 50V, X7R, +/-10%
VBOOT SET +/-1% IMAX SET +/-1%
RP101 DIFFOUTA 17 AT 0V AT 35A
0 RP104 CP64 RP105 DIFFOUTA 28
P_PWMA [68]
*
Dummy 680pF 3.01K CP65 COMPA 19 PWMA/IMAXA 26 NCP6151_GND

P_CSNA [68]
*
*
50V, X7R, +/-10% +/-1% 2.2nF COMPA CSN A 25 RP106 100KOhm
VCC_AXG 47 CP66 68pF 50V, X7R,+/-10% CSPA Dummy

**
+/-5% RP107 50V,NPO,+/-5% RP108 +/-1% NCP6151_GND NCP6151_GND

*
*
FBA 16 P_CSPA CP67
B B
*
+1P1V_AXG RP109 CP68 FBA 0.1uF RP112
*
*
1K RP208 RP110 402 Ohm 4.7nF 50V, X7R, +/-10% 24 CSSUMA 6.8K 16V, X7R, +/-10% P_CSPA
P_CSPA [68]
*
+/-1% +/-1% RP111 TRBSTA 18 CSSUMA +/-1%

TRBSTA 22 CSCOMPA 20K
*RP115
100 Ohm 1K 24.9KOhm * CP69
5.6nF
1.2KOhm
+/-1% CSC OMPA
RP113 150KOhm
+/-1%
RP114 200KOhm
+/-1% +/-1%
+/-1% RP116 NCP6151_GND +/-1% +/-1% 50V,X7R,+/-10% RTP3 100K P_PWM1 P_PWM3
*
0 Dummy RP117 +/-1% CP72 470pF
*
* **
T
NCP6151_GND VSPA 15 60.4K 50V, X7R, +/-10%
[9] H_VCCAGX_SENSE VSPA
*
CP92 20 ILIMA CP70 2.2nF
* 1nF
ILIMA 50V, X7R,+/-10% VCORE
14 RP203
[9] H_VSSAGX_SENSE
*RP120 CP74
Dummy
50V, X7R, +/-10% VSN A
+/-1%
RP118
*
* 1K
PWM
ADDRESS
*RP122
10K IMAX SET *RP123
93.1K
*
0.1uF 13K +/-1% P_CSNA +/-1% AT 120A +/-1%
* * CP75 CP73 680pF
P_CSNA [68]
*
100 Ohm Dummy 0.1uF +/-1% CP208
16V, X7R, +/-10% Dummy 50V, X7R, +/-10%
+/-1%
16V, X7R, +/-10%
V_GT PORTION * 560pF
+/-10%
RP119
10 Ohm
RP121
10 Ohm
21 +/-1% +/-1%
*
*
NCP6151_GND NCP6151_GND NCP6151_GND 23 DROOPA DROOPA
+5V IOUTA RP124 8.25KOhm +/-1% NCP6151_GND NCP6151_GND
*
RP125 RP126 VBOOTA 27 CP76

0
+5V
1K VBOOTA RP127 * 1nF
*
Dummy +/-1% 3 VRHOT# 50V, X7R, +/-10%
*RP129 VR_HOT#
ROSC
2
EPAD
Dummy 10K TSENSE

CP77 TSENSEA 13 TSEN SE
RP128 ** 0.1uF OPTION: DISALBE
+/-1%
*RP130
TSEN SEA *RP131
3.3KOhm
0
NCP6151_GND
H_PROCHOT# [9,32]
34.8KOhm 16V, X7R, +/-10% 3.3KOhm +/-1%
11
53
+/-1% V_GT +/-1%

NCP6151_GND
ROS C
Green mark is update from 20100720 NCP6151_GND NCP6151_GND

* CP79
CP78
0.1uF * *
A
PUT COLSE T RTP6
*RP132
* 0.1uF
*RP134 16V, X7R, +/-10% *RP133
7.5K
T RTP4
10K
2
CPP11
1
A
10K 7.5K 16V, X7R, +/-10% 8.25KOhm NCP6151_GND +/-1% +/-1%

TO V_GT +/-1% +/-1% +/-1% BOTTOM PAD PUT COLSE
HOT SPOT Work F= 300Khz COPPER
Green mark is update from 20100726 CONNECT TO TO VCORE Dummy
GND Through HOT SPOT
NCP6151_GND 4 VIAs NCP6151_GND NCP6151_GND Title
NCP6151_GND NCP6151_GND NCP6151_GND
Green mark is update from 20100830

Set 110deg OTP Power-3: Vcore PWM
DWG NO Rev
A00
Gold Coast_MT/DT
Green mark is update from 20101012 Date: Friday, December 24, 2010 Sheet 67 of 70
5 4 3 2 1
5 4 3 2 1
+12V_CPU
+12V_CPU +12V_VIN
+12V_VIN RP136
RP135 25V, X7R, +/-10% 2.2 BAT54HT1G
2.2 BAT54HT1G 220nF DP5 CP85
+/-5% DP4 CP84 CP190 CP183 A C CP184 CP185
*
A C 10uF 10uF CP81 10uF 10uF CP83
* * * * * *
*
CP263 0.1uF RP138 220nF CP264 0.1uF
16V, X5R,+/-10%
16V, X5R,+/-10%
16V, X5R,+/-10%
16V, X5R,+/-10%
RP271
* 3.3nF Dum m y 2.2 25V, X7R, +/-10%
* 3.3nF Dum m y
VCC2_20
2.2 NTMFS4921NT1G 5 +/-10% 16V, X7R, +/-10% +/-5% NTMFS4921NT1G 5 +/-10% 16V, X7R, +/-10%
D D
+/-5% BST1_25 +/-5% QP21 D BST2_25 +/-5% QP22 D LL=1.7m ohms
VCC1_20
2.2 2.2
1
UP5 RP139 4 RP183 UP6 RP140 4 RP184 0.25V~1.55V/112A MAX
4 8HG1_25 HG1_R_25 G S 1 * 1 4 8 HG2_25 HG2_R_25G S 1 * 1
BST
BST
VCC DRVH 2 +/-5% VCC DRVH 2 +/-5% TDC=85A
*
3 [67] P_PWM2 3
LP2 LP3 OS-CON
7 SW1_25 7 SW2_25
[67] P_PWM1 2 SW +VCORE 2 SW +VCORE
5 5 5 5
*
GND RP141 RP142
GND
PAD
PAD
*
*
3 PWM 5 PWM
P_DRVON
EN DRVL
10K
Dum m y
D D CP87
3.3nF
* 260nH P_DRVON 3
EN DRVL
5 LG2_25 10K
Dum m y
D D CP89
*
3.3nF
260nH
*
EC P9
820uF *
EC P10
820uF *
EC P8
820uF
RP182
*
220
1
1
RP143 NCP5901MNTBG LG1_25 4 G 4 G 50V, X7R, +/-10% RP145 CP88 NCP5901MNTBG 4 G 4 G 50V, X7R, +/-10% +/-5%
* *
9
2.5V, +/-20%
2.5V, +/-20%
2.5V, +/-20%
2
2
2.2Ohm CP86 S 1 S 1 2.2Ohm 1uF S 1 S 1 Dum m y
+/-1% 1uF 2 2 RP144 CPP1 CPP2 +/-1% 2 2 RP146 CPP3 CPP4
* *
2
25V,X7R,+/-10%
3 3 1 COPPER COPPER 3 3 1 COPPER COPPER
25V,X7R,+/-10%
BOTTOM PAD QP23 QP24 +/-1% Dum m y Dum m y BOTTOM PAD +/-1% Dum m y Dum m y
1
CONNECT TO NTMFS4939NT1G NTMFS4939NT1G CONNECT TO QP25 QP26
NTMFS4939NT1G NTMFS4939NT1G
GND Through GND Through EC P12 EC P11
4 VIAs 4 VIAs
* 820uF
* 820uF
2.5V, +/-20%
[67] P_CSP2
2.5V, +/-20%
+12V_CPU [67] P_CSP1 +12V_CPU
[67] P_CSN 2
[67] P_CSN 1
+12V_VIN Ceramic / 0805/X5R
+12V_VIN
RP147 RP148 CP96 CP115 CP116 CP99 CP118
2.2 BAT54HT1G 2.2 BAT54HT1G 22uF 22uF 22uF 22uF 22uF
DP6 DP7 * * * * *
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
A C CP181 CP182 A C CP186 CP187
*
*
CP91 CP93
C
RP149 CP94 CP265 * 10uF
* 10uF
* 0.1uF RP150 CP95 CP266 * 10uF
* 10uF
* 0.1uF
C
16V, X5R,+/-10%
16V, X5R,+/-10%
16V, X5R,+/-10%
16V, X5R,+/-10%
2.2 220nF 3.3nF Dum m y 2.2 220nF 3.3nF Dum m y
+/-5% 25V, X7R, +/-10% NTMFS4921NT1G 5 * +/-10% 16V, X7R, +/-10% +/-5% 25V, X7R, +/-10% NTMFS4921NT1G 5 * +/-10%
16V, X7R, +/-10%

BST3_25 +/-5% QP29 D BST4_25 +/-5% QP30 D
VCC3_20
2.2 2.2
VCC4_20
1
1
UP7 RP151 4 RP185 UP8 RP152 4 RP186 CP102 CP103 CP104 CP105 CP114
4 8 HG3_25 G
HG3_R_25 S 1 * 1 4 8 HG4_25 HG4_R_25 G S 1 * 1
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
BST
BST
VCC DRVH 2 +/-5% VCC DRVH 2 +/-5%
[67] P_PWM4
*
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
3 LP4 3 LP5
[67] P_PWM3
7 SW3_25 7 SW4_25
2 SW 5 5 +VCORE 2 SW 5 5
*
RP153 RP154
GND
GND
PAD
PAD
*
*
P_DRVON 3 PWM 5 10K D D CP107 260nH P_DRVON 3 PWM 5 10K D D CP109 260nH
EN DRVL Dum m y 3.3nF * EN DRVL Dum m y 3.3nF *
1
1
RP155 CP106 NCP5901MNTBG LG3_25 4 G 4 G 50V, X7R, +/-10% RP157 NCP5901MNTBG LG4_25 4 G 4 G 50V, X7R, +/-10%
* *
9
6
2
2
2.2Ohm 1uF S 1 S 1 2.2Ohm CP108 S 1 S 1
+/-1% 2 2 RP156 CPP5 CPP6 +/-1% 1uF 2 2 RP158 CPP7 CPP8 CP110 CP111 CP112 CP113
* *
2
2
25V,X7R,+/-10%
3 3 1 COPPER COPPER 3 3 1 COPPER COPPER 22uF 22uF 22uF 22uF

* * * *
25V,X7R,+/-10%
BOTTOM PAD +/-1% Dum m y Dum m y BOTTOM PAD +/-1% Dum m y Dum m y
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
CONNECT TO QP31 QP32 CONNECT TO QP33 QP34
NTMFS4939NT1G NTMFS4939NT1G NTMFS4939NT1G NTMFS4939NT1G
GND Through GND Through
4 VIAs 4 VIAs
[67] P_CSP4
[67] P_CSP3 [67] P_CSN 4

Inside processor socket
[67] P_CSN 3 +VCORE CP97 CP98 CP100 CP119
B
+12V_CPU
Bottom side * 22uF
* 22uF
* 22uF
* 22uF
B
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
CP117 CP101 CP162 CP161
22uF 22uF 22uF 22uF
RP159 +12V_VIN * Dum m y * Dum m y * Dum m y * Dum m y
2.2 DP8
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
BAT54HT1G
A C CP188 CP189
*
10uF 10uF CP121

CP122 * * * 0.1uF
16V, X5R,+/-10%
16V, X5R,+/-10%
RP160 220nF CP267 Dum m y
25V, X7R, +/-10%
2.2
+/-5%
NTMFS4921NT1G
QP36 5 QP62
NTMFS4921NT1G
5 * 3.3nF
+/-10%
16V, X7R, +/-10% LL=4.1m ohms
0.25V~1.55V/35AMax
BSTA_25 +/-5% D D +1P1V_AXG TDC=25A
VCCA_20
2.2
1
UP9 RP161 4 4 RP187

4 8 HGA_25 HGA_R_25
G S 1 G S 1 * 1
BST
VCC DRVH 2 2 +/-5% CP124 CP125 CP126 CP178 CP160 CP153

3 3 EC P17 EC P18 EC P19 EC P20 EC P22 EC P27 22uF 22uF 22uF 22uF 22uF 22uF
* * * * * *
*
[67] P_PWMA
SW
7
* 820uF * 820uF * 820uF * 820uF * 820uF * 820uF RP179
*
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
2 LP7 470nH Dum m y Dum m y 220
GND
PAD
*
2.5V, +/-20%
2.5V, +/-20%
P_DRVON PWM 3 5 RP162 SWA_25 2 1 +/-5%
[67] P_DRVON
2.5V, +/-20%
2.5V, +/-20%
2.5V, +/-20%
2.5V, +/-20%
CP127 EN DRVL 5 5
*
10K Dum m y
1
RP163 1uF NCP5901MNTBG Dum m y D D CP128

* *
9
2.2Ohm 3.3nF
25V,X7R,+/-10%
+/-1% LGA_25 4 G 4 G 50V, X7R, +/-10%

2
2
+12V_CPU +12V_VIN S 1 S 1
Choke 1uH BOTTOM PAD 2 2 RP164 CPP9 CPP10
LP6 CONNECT TO 3 3 * 1 COPPER COPPER
*
1 2 +/-1% Dum m y Dum m y

GND Through
1
1
A 12V_PWRCONN QP37 QP38 A
EC P14 EC P15 EC P16 4 VIAs NTMFS4939NT1G NTMFS4939NT1G +1P1V_AXG
4 3
* CP123
0.1uF
* 470uF
* 470uF
* 470uF Bottom side
2 1 16V, +/-20% 16V, +/-20% 16V, +/-20% [67] P_CSPA CP131 CP210
16V, X7R, +/-10%
22uF 22uF
[67] P_CSN A Dum m y Dum m y Title
Header_2x2 * *
Power-4: Vcore Driver
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+3V +12V_CPU +12V_CPU +12V_VIN +1P05V_VCCIO

1.05V or 1.0V/8.5A MAX VCCIO VID control
Bottom side
* RP180 VCCIO *
Dum m y Dum m y Dum m y Dum m y Dum m y
CP147
22uF
CP148 CP149
22uF 22uF
CP241 CP262
22uF
*
22uF
* * * *
Dum m y Dum m y Dum m y
CP252 CP270
22uF 22uF
CP271
22uF
* *
+5V
RP212
*
10K VCCIO_FB
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
+5V
DP2 CP135 EC P21 *RP209 49.9K
D
[67] VCCIO_PWRGD
VCCIO_PWRGD BAT54HT1G * CP134
0.1uF * 10uF * 470uF 10K +/-1%
*RP215
16V, +/-20%
16V, X5R, +/-10%
* CP138 RP167 Dum m y
C
0.1uF 2.2 10K G
16V, X7R, +/-10%

+/-5% Ceramic / 0805/X5R
16V, X7R, +/-10%

VCCIO_BST_25 QP74 QP46
S
D VCCIO_VCC MMDT5551 2N7002 D
*
11
CP258 CP261 CP256 CP260 CP259 CP257 CP275 CP254 CP274 CP150
UP10 5
6 1 RP190 D RP189 * 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF 0.1uF
Dum m y
EPAD
1
VCC BOOT
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
2.2 QP39 2.2
16V, X7R, +/-10%

+1P05V_PC H +5VSB 10 3 VCCIO_UG_25 +/-5%VCCIO_UG_R_25 4 NTMFS4921NT1G +/-5%
PGOOD UG G 1 RP226
S
*
VCCIO_COMP_EN 7 2 VCCIO_LX_25 2 VCCIO_VOS
QP69 Dum m y
COMP/EN LX * RP191 3
* CP139
2N7002 50V, NPO, +/-5% 8 4 VCCIO_LG_25 0.1uF 49.9K
* *RP199 10K
D
D
4
6
RP200 CP300 FB LG 25V, X7R, +/-10% +/-1%
9 5
1K 10K
* 220pF
VOS GND
Dum m y
VCCIO_FB
RP193 CP143 2 LP9 1 Bottom side
+/-1% +/-1%
*
VCCIO_VOS
G G
*
301 22pF NCP1589DMNTWG EC P23 EC P26 EC P24 EC P25 Dum m y Dum m y Dum m y
50V, NPO, +/-5%

+/-1% CP133 5 330nH 820uF 820uF 820uF 820uF CP280 CP277 CP272
*
1
* CP137 1uF
* D
* * *Dum m y* * Dum m y 22uF
* * 22uF 22uF
* QP48
C
2.5V, +/-20%
2.5V, +/-20%
RP166
S
S
0.1uF 25V,X7R,+/-10% QP40 CP142 2N7002
2.5V, +/-20%
2.5V, +/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
B Dum m y 2 1 4
VCCIO_LG_R_25 G NTMFS4939NT1G 2.2nF RP201 Dum m y
2
1
CP141
* S 50V, X7R, +/-10% 1K
*
16V, X7R, +/-10%
CP136 QP70 1nF RP165 2

* H_VCCIO_SEL [9]
E
0.1uF MMBT3904-7-F 15K 0 3

Close to Pin6 +/-1%
Dum m y 50V, X7R, +/-10% RP195 +/-1%
2.2 H_VCCIO_SEL High ->+1P05V_VCCIO=1.05V
16V, X7R, +/-10%
+/-5%
*RP202 Bottom side H_VCCIO_SEL Low ->+1P05V_VCCIO=1.0V
*
*RP205
13K 0 Dum m y Dum m y Dum m y Dum m y Dum m y
Close to UP10
+/-1%
*RP169
13K
RP168
0
H_VCCTT_SENSE [9] *
CP278 CP279
22uF 22uF
* *
CP281 CP273
22uF 22uF
CP253
22uF
* * VCCSA sequencing circuit
+/-1%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
Dum m y +5V_S5
H_VSSTT_SENSE [9]
*
*
C [9] H_VSSTT_SENSE C
RP194 RP217
* * RP198
3
RP206 10K
0 *RP207 0
Close to UP10 0 3.32KOhm RP204 Dum m y +1P05V_VCCIO QP44
*
+/-1% CP140 33nF 0 MMDT5551
*
+/-10% Bottom side
RP192
4
22 Ohm CP214 CP215 CP216 CP217 10K
VOUT= 0.8V(1+RP194/RP205) EC P13 22uF 0.1uF 0.1uF 0.1uF RP230
+/-1%
820uF * Dum m y * Dum m y * Dum m y * Dum m y VCCSA_COMP_EN
S_SLP_S3# [20,24,32,64,66,70]
*
* *
2.5V, +/-20%
6.3V,X5R,+/-20%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

+5V_S5
+12V_VIN
+12V_CPU RP218
VCCSA
3
10K
+12V_CPU
A
QP45
DP9 CP163 CP158
BAT54HT1G
* 0.1uF * 10uF CP218 CP219 CP221 CP220
MMDT5551
RP213 16V, X5R, +/-10%

* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
16V, X7R, +/-10%
4
2.2 Dum m y Dum m y Dum m y Dum m y
C
+/-5%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

VCCIO_PWRGD
VCCSA_VCC_20
1
CP191
*
1uF
25V,X7R,+/-10% *RP197
1 VCCSA VID control
2
11
+/-5%
UP11 5 +5V +5V RP233
*
B 6 1 VCCSA_BOOT_25 D QP41 VCCSA_FB B
EPAD
VCC BOOT
NTMFS4921NT1G
10 3 VCCSA_UG_25 VCCSA_UG_R_25 4
* CP154 1
*RP219 35.7KOhm
D
PGOOD UG 2.2 RP223 G 1 0.1uF RP216
S
VCCSA_COMP_EN 7 2 +/-5% 2 25V, X7R, +/-10% 15K 10K +/-1%
COMP/EN LX VCCSA_PH ASE_25 3
RP196 0.929V or 0.855V/8.8A +/-1%
VCCSA_FB 8 4 * 10K G
FB LG 2
+V_VCCSA RP225
LP10
*
9 5 QP42
S
VOS GND VCCSA_LG_25
* CP155 2N7002
*
NCP1589AMNTWG 100 Ohm 0.1uF
1
+/-1%
*RP234
2KOhm 5
* CP193
1uH
*
CP359
22uF
*
CP362
22uF *
EC P41
820uF
*
CP360
22uF +5V
Dum m y
16V, X7R, +/-10%

+/-1% RP231 D 2.2nF RP232
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
*
* CP159 1 +/-1% QP47 50V, X7R, +/-10% VCCSA_VOS
2.5V, +/-20%
*
1.5nF 2 1 4 G
VCCSA_LG_R_25 NTMFS4939NT1G QP43
Close to UP11 1 *RP220
50V, X7R, +/-10% S MMDT5551 35.7KOhm
D
4
6
RP227 2 RP228 10K +/-1%
Near MOSFET 3
CP192 15K 2.2
2.2nF * +/-1% +/-5%
Dum m y
RP222
*
G
50V, X7R,+/-10%
[9] H_VCCSA_VID
RP221 100 QP51
* *RP224
S
RP293 100 Ohm +/-5% 2N7002
*
VCCSA_VOS Close to L/S MOS +/-1% 1K Dum m y

+/-1%
Green mark is update from 20100720 RP294 3.32KOhm
45.3KOhm * +/-1%
+/-1%
A
H_VCCSA_VID Low ->+V_VCCSA=0.925V A
RP236 RP229
Green mark is update from 20100726 RP263 3.32KOhm H_VCCSA_VID High ->+V_VCCSA=0.85V
*
*
45.3KOhm
+/-1% H_VCCSA_SENSE [9]
+/-1%
0
*
Green mark is update from 20100908 VOUT= 0.8V(1+RP236/RP263) Title

*
RP238 CP164 Power-5: VCCIO_VCCSA

124 10nF
+/-1% 50V, X7R, +/-10% DWG NO Rev
Green mark is update from 20101012 A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
+5V +5V_DUAL +5VSB +5VSB +1P5V_SM
+V_1.5_SM Power(DDRIII)
* CP227
* CP226
* CP283
* CP284 *RP240
0 *RP241
3.24K Ohm *RP242
8.2K
* RP251
0.1uF 0.1uF 0.1uF 0.1uF Dummy +/-1% +/-5%
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% Dummy 0
RP249
*
VT_5078_PG 13 8 VT_5078_BOOT_25 VT_5078_PHASE_25
PGOOD BOOT
*
RP243 CP174
*
VT_5078_5VMAIN 4 9 VT_5078_HDRV_25 CP173
[32,63] B_ATX_PWROK
0 5VMAIN HDRV
0
0.1uF * 470pF
Dummy
D 14 10 16V, X7R, +/-10% 50V, X7R, +/-10% D
+3V +5VSB
VCC SW RP250
*RP252
* *
*
RP244 0 VT_5078_S3#I 17 11 VT_5078_ISNS 1.27K
[32,63] B_ATX_PWROK S3# I ISNS
RP246 Dummy 18 12 VT_5078_LDRV_25 4.99K
+/-1%
*RP253
1K
*
D
[24,32,65] S_SLP_S4# EN LDRV +/-1% +/-1%

1K
[20,24,32,64,66,69] S_SLP_S3#
+/-1% Dummy
*RP247
18K
Dummy
G
RP245
0
+/-1% +3V_DUAL
Dummy QP66
* CP175
D
2N7002 5VDUAL_SBSW 3 23 VT_5078_FB 4.7nF

SBSW FB CP176 RP255
Dummy
3.3V/1.5A MAX 15
3.3 ALW COMP
22 VT_5078_COMP
50V, X7R, +/-10%
* 47pF 33K *RP256
1.82KOhm
50V, NPO, +/-5%

G +/-5% +/-1%
QP68 5VDUAL_S3#O 16
CP165 2N7002 [65] 5VDUAL_S3#O S3# O *RP254
18K
Dummy
D
S
* 1uF Dummy
16V,X5R,+/-10%
+/-1%
Dummy
G
5VDUAL_USBSW 1 7
QP77 SBUSB# VDDQ IN
+V_SM_VTT Power(DDR VTT)

S
2N7002 2 24 VT_5078_REF_IN CP196

[32,63] O_PSON#
Dummy
[24,32,65] S_SLP_S4# S4ST# REF IN
* 10nF * RP257
6 Dummy 1K
VTT OUT 25V, X7R, +/-10% +1P5V_SM_VTT
+/-1%
5 VT_5078_VTT_SNS
VTT SNS
C * CP166
10uF * CP167
0.1uF * CP168
4.7uF * CP169
1uF * CP170
0.1uF * CP171
4.7uF
0.75V/1.5A MAX C
16V, X7R, +/-10%
16V, X5R, +/-10%
16V, X7R, +/-10%

6.3V, X5R, +/-10%
Dummy 6.3V, X5R, +/-10%

* CP197
* RP258
6.3V,X5R,+/-10%
10nF
Dummy 1K
VT_5078_ILIM 20 19 25V, X7R, +/-10% ECP36
ILIM GND +/-1%
VT_5078_SS 21 25 * CP198
* CP199 * 1000uF
SS GND1
0.1uF 4.7uF 6.3V, +/-20%
*RP260
16V, X7R, +/-10%
6.3V, X5R, +/-10%

100 Ohm
RP248 +/-5%
+5VSB 200KOhm
* CP172 Dummy
+5V_DUAL_USB +/-1% 0.1uF

16V, X7R, +/-10%
UP12
0
RP259
*
FAN5078D3MPX
4
RP267
*
5VDUAL_USBSW 3
QP64 +5V_DUAL_USBKB
1M NTGS4111PT1G
+/-5% +5VSB +5V_DUAL
+V_1.5_SM Power(DDRIII)
1
2
5
6
2
3 CP177 VT_5078_REF_IN
*
1 2.2nF
*RP272
*
50V, X7R, +/-10%
D
D
DP3 QP59 10K
BAT54C AOD452 *RP268
1K *RP269
1K Dummy FBP3 FBP2 FBP1 FBP4
+/-1% +/-1% 30 Ohm@100MHz 30 Ohm@100MHz
5VDUAL_S3#O G G G G 30 Ohm@100MHz 30 Ohm@100MHz
[20,24,32,64,66,69] S_SLP_S3#
B B
* CP245
* CP239 QP60 QP78 QP79 CP200 CP201 ECP29 ECP30
S
S
1nF 1nF AOD452 2N7002 2N7002 Dummy
* 1uF
* 10uF * 470uF * 470uF
16V, X5R, +/-10%
6.3V,X5R,+/-10%
6.3V, +/-20%
6.3V, +/-20%
Dummy Dummy Dummy Dummy NTMFS4921NT1G NTMFS4921NT1G
50V, X7R, +/-10% 50V, X7R, +/-10% QP52 5 QP54 5
D D
VTTsequencing control
+5V VT_5078_HDRV_25 4 4 +1P5V_SM
+5VDUAL +5VSB +12V +3V

G S 1
2
3
G S 1
2
3
LP12 Choke 1uH
VT_5078_PHASE_25 2 1 1.5V/25A MAX
4
*
*
5VDUAL_SBSW 3 ECP40 CP243
*RP270 * 1000uF
* 10uF
*
ECP31
*
ECP32
*
ECP33
*
ECP35 CP129 CP211 CP213
*
ECP34
*
ECP43
RP264 QP65 8.2K Dummy Dummy
* CP202 1000uF 820uF 1000uF 1000uF
* 22uF
* 22uF
* 22uF 820uF 820uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V, +/-20%
6.3V, +/-20%
2.5V, +/-20%
6.3V, +/-20%
6.3V, +/-20%
2.5V, +/-20%
0 NTGS4111PT1G +/-5% NTMFS4939NT1G NTMFS4939NT1G 2.2nF Dummy
2.5V,+/-20%
+5V_DUAL QP55 5 QP56 5 50V, X7R, +/-10%
S
1
2
5
6
CP179 D D
G
*
VT_5078_LDRV_25 4 G 4 G
2.2nF AOD452 1 1
S S
D
50V, X7R, +/-10%

*RP265 *RP266 CP180 * ECP37 QP75 2
3
2
3
+1P5V_SM
1K 1K
* 4.7uF 470uF
D
10V, X7R, +/-10%
6.3V, +/-20%
+/-1% +/-1% RP261 Bottom side

5VDUAL_S3#O G 2.2
QP67 ECP38 +/-5%
AOD452 * 1000uF CP203 CP212 CP209
S
A 6.3V, +/-20%
* 22uF
Dummy * 22uF
Dummy * 22uF
Dummy
A
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
+3V_DUAL
+5V
Title
Max. output current = 1.5A
Power-6: DDR3/5Vdual/5VUSB
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
IRQ Routing Table PCH

On-Die PLL Voltage Regulator Voltage Select Boot BIOS Destination Selection
HDA_SYNC Description
GNT1# SATA1GP/GP19
INTA# INTB# INTC# INTD# IDSEL REQn# GNTn# (IN-PU) (IN-PU) Description
High 1.5V
Slot3 C D A B 18 0 0 Low Low Flash cycle routed to LPC
Low 1.8V DEFAULT
D D
High Low Flash cycle routed to PCI
On-Die PLL Voltage Regulator
Low High Flash cycle routed to NAND
STRAPPING Table GPIO28
(IN-PU) Description
High High Flash cycle routed to SPI DEFAULT
CPU side
High Regulator is enabled. DEFAULT
CFG[17:0] Description
Low Regulator is disabled.
PCI Express static x16 1: normal Default
[2] lane numbering reversal 0: lane numbers reversed
Topblock Swap Mode Deep S4/S5 Well on-die Voltage Regulator Enable
GNT3#/GPIO55
00: 1x8, 2x4 PCI Express (IN-PU) Description DSWVRMEN Description
01: reserved
[6:5] PCI Express Bifurcation High Topblock swap mode: Disable DEFAULT High Enable DEFAULT
10: 2x8 PCI Express
11: 1x16 PCI Express
Default Low Topblock swap mode: Enable Low Disable
No Reboot Mode Digital Port C Strap

SPKR
(IN-PD) Description DDPC_CTRLDATA Description
C C
Clock Gen. High No reboot mode: Enable High Configure Port C DEFAULT
FREQ C_CK_BSEL0 C_CK_BSEL1 C_CK_BSEL2 Low No reboot mode: Disable DEFAULT Low Disable
Integrated 1.05V VRM

100 1 0 1
INTVRMEN Description
133 1 0 0 Default
High Integrated 1.05V VRM: Enable DEFAULT
PIN NAME NET Strapping description

Low Integrated 1.05V VRM: Disable
1 Overclocking DISABLED DEFAULT
PCI2/TME C_CK505_33M_PCI2
0 Overclocking ENABLED TLS Confidentiality
(PIN4)
1 SRC5 DEFAULT GPIO15
PCI4/SRC5_EN C_CK505_33M_PCI4 (IN-PD) Description
0 CPU_STOP# and PCI_STOP#
(PIN6) ME Crypto TLS cipher suite
1 CPU_ITP High with confidentiality
PCIF5/ITP_EN C_CK505_33M_PCI5
0 SRC8 DEFAULT ME Crypto TLS cipher suite
(PIN7) Low with no confidentiality DEFAULT
See CFG Table DEFAULT
B
C_CK505_33M_PCI3
Low (Set SATA and SRC come from PLL4)
Flash Descriptor Override Strap
B
PCI3/CFGP
(PIN5) Mid See CFG Table
High See CFG Table HDA_SDO Description

Flash descriptor security
High will be override
Low Disable ME in Manufacturing Mode DEFAULT
SIO SMSC5544 DMI Rx Termination Voltage
PIN NAME NET Strapping description SPI_MOSI

(IN-PD) Description
1 Diag_En Disable
GP070 / PWM4 O_SPEAKER
(PIN127) 0 Diag_En Enable DEFAULT Low DMI Rx Termination Voltage DEFAULT
DTR1# [TEST_EN] 1 PE BOOT Loader Strap (DTR1#)= Load from SPI
/GP051 O_DTR1#_R DMI Termination Voltage
(PIN104) 0 PE BOOT Loader Strap (DTR1#)= No Load from SPI DEFAULT
NV_CLE
(IN-PU) Description
DMI and FDI Tx/Rx
High Termination Voltage DEFAULT
A A
Title
GPIO/IRQ/IDSEL Table
DWG NO Rev
A00
Gold Coast_MT/DT
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
GPIO Table
DW G NO Rev
Gold Coast_MT/DT A00
Date: Friday , December 24, 2010 Sheet 8 of 70

5 4 3 2 1

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5 4 3 2 1

Intel PROCESSOR SANDY BRIDGE LGA1155

1. Index / Block diagram

PCI Rear USB Ports X4

53. Pilot Run Conn Page 21-30

70. Power: DDR3/5Vdual/5VUSB Page 51

Index / Block diagram

25 MHZ LAN 82579 C_PCIE_L1/L1#

POWER DELIVERY MAP

DDR3 DDR3 Vtt VCCSA

Deep Sleep : Off

SMBus SMLINK1 QO4/QO5

PCIE 16x SMBUS

PCI EXPRESS 16x SLOT 1

PCI EXPRESS 16x (wired as 4x signal) SLOT 4

PCI EXPRESS 1x SLOT 2

PCI SLOT SLOT 3

DDR3 DIMM1 CHA Address : 0 X00

DDR3 DIMM3 CHA Address : 0 X02

DDR3 DIMM2 CHB Address : 0 X04

DDR3 DIMM4 CHB Address : 0 X06

POWER ON Timing Diagram

t225 Power rails rise

SLP_S5# VCCSA VID[0] Buffers Output is

Recommended that VccSA ramp after VCCIO has

A A Set VID A A GETReg A A

CPU SVID buffers are Hi-Z once VCCIO is T

Note:DDR spec reuqires that DDR_RESET# be

Deep Sleep Exit PSU (1ms)

100ms~500ms Min 10 PCIe bclks PCH: No min/max requirement

DPWROK BCLK, PCIe

RSMRST# T =PCH_PWROK & SYS_PWROK &

SUSWARN# DMI training CPU_RESET_DONE

Gold Coast_MT/DT A00

Date: Friday, December 24, 2010 Sheet 5 of 70

RESET / Power Good MAP Deep Sleep Exit MAP

Power On Botton (1) (1) (8)

PCH_MEPWRGD (D5) (D4) (D2)

+5VDUAL Sequence +5V_S5/+3V_S5

RH4 usage 1kOhm ; CRB 0.7-12/10/09

+5V RH17 change to 4.7k; CRB 0.7-11/30/09

Remove CH1,CH2-12/29/09 Add H_VCCIO_SEL circuit; CRB 0.7-12/03/09

AF33 D3_DQ_B62 Title

D13 VCC_36 VCC_116 J18 J8 VCCIO_29 U39 VAXG_30

6.3V, X5R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

A17 AM27 AT8 F37

AH40 AP40 C11 K2

16V, X7R, +/-10%

6.3V, X5R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

Change to 0.1uF; PDG 0.7-12/07/09

6.3V, Y5V, +80%/-20%

16V, X5R, +/-10%