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    DLD Lab Report 13

    Uploaded by

    Talha Tufail
    This document provides the rubrics and details for Lab 13 on designing latches using logic gates in a digital logic design course. The rubrics assess a student's ability to analyze problems by pointing out hardware and software limitations and implications, record raw data/evidence, and select relevant hardware tools or software components for experiments. The lab report objectives are to understand the working principle of an SR latch and implement a D-latch, T-latch in hardware and software. It introduces sequential systems containing memory elements that make the system state dependent on previous states, unlike combinational systems. The tasks are to implement a gated D-latch on a trainer and make a T-flip flop using a D-flip flop

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    DLD Lab Report 13

    Uploaded by

    Talha Tufail
    93 views7 pages
    This document provides the rubrics and details for Lab 13 on designing latches using logic gates in a digital logic design course. The rubrics assess a student's ability to analyze problems by pointing out hardware and software limitations and implications, record raw data/evidence, and select relevant hardware tools or software components for experiments. The lab report objectives are to understand the working principle of an SR latch and implement a D-latch, T-latch in hardware and software. It introduces sequential systems containing memory elements that make the system state dependent on previous states, unlike combinational systems. The tasks are to implement a gated D-latch on a trainer and make a T-flip flop using a D-flip flop

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    This document provides the rubrics and details for Lab 13 on designing latches using logic gates in a digital logic design course. The rubrics assess a student's ability to analyze problems by pointing out hardware and software limitations and implications, record raw data/evidence, and select relevant hardware tools or software components for experiments. The lab report objectives are to understand the working principle of an SR latch and implement a D-latch, T-latch in hardware and software. It introduces sequential systems containing memory elements that make the system state dependent on previous states, unlike combinational systems. The tasks are to implement a gated D-latch on a trainer and make a T-flip flop using a D-flip flop

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    93 views7 pages

    DLD Lab Report 13

    Uploaded by

    Talha Tufail
    This document provides the rubrics and details for Lab 13 on designing latches using logic gates in a digital logic design course. The rubrics assess a student's ability to analyze problems by pointing out hardware and software limitations and implications, record raw data/evidence, and select relevant hardware tools or software components for experiments. The lab report objectives are to understand the working principle of an SR latch and implement a D-latch, T-latch in hardware and software. It introduces sequential systems containing memory elements that make the system state dependent on previous states, unlike combinational systems. The tasks are to implement a gated D-latch on a trainer and make a T-flip flop using a D-flip flop

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    Rubrics for CPE241 Digital Logic Design Lab

    Lab #: 13

    Lab Title: Design of Latch using logic gates(SR latch, gated SR, D-Latch)

    Names:
    Muhammad.Zain Registration #: Fa20-bce-015

    Rubrics Name & Number Marks

    R4: Limitations and Implications:

    Ability to point out limitations and implications of Hardware

    Problem Analysis And software Components.

    R5: Data/Evidence Measurements:

    Ability to record raw data / evidence.

    R10: Realization of Hardware and Software Tools for

    Experiments:
    Modern Tools Usage
    Ability to select relevant hardware tools or software

    components
    Lab Report # 13
    Title: Design of Latch using logic gates (SR latch, gated SR, D-latch)

    Objectives:
    1. Understand the working principle of SR Latch

    2. Implement the D-Latch, T-Latch on hardware and software

    Introduction:
    Sequential systems are those digital systems, which contains a memory element. It
    consists combinational circuit to which storage elements are connected to form a
    feedback path. The binary information stored in the element at a given time defines the
    state of the sequential circuit at that time.

    The state of the sequential system is not only dependent upon the current input but
    also the previous state of the system. In contrast, the output of a combinational system
    is only the function of the current inputs.

    Sequential system can be divided into two main categories, synchronous and
    asynchronous sequential systems. The behavior of the synchronous sequential system
    can be defined form the knowledge of its signal at discrete instant of time.
    Synchronization is achieved through a timing device called clock which is periodic chain
    of pulses. Where in asynchronous sequential system, the behavior of the system
    depends upon the input of at any time instant and the order of input change.

    In Lab Task:

    Implement gated D-Latch on ePal trainer using logic gates.


    Implement the T-Flip Flop using a D-Flip Flop.

    Answer 1:
    Circuit Diagram:

    In-lab Diagram:
    Answer 2:

    Circuit Diagram:

    In-Lab Diagram:
    Post Lab Task:

    Save the output of the following combinational circuit in a D-Flip Flop


    Answer:
    Circuit Diagram:

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