14-Programming of Hardware Interrupts - Int0 & Int1-06-03-2023

8051 Interrupts
• Interrupts are basically the events that temporarily suspend the main program, pass
the control to the external sources and execute their task. It then passes the control
to the main program where it had left off.
• 8051 has five interrupts.
• These interrupts are
 INT0
 INT1
 T0
 T1
 TI/RI
• All of the interrupts can be enabled or disabled by using the IE (interrupt enable)
register.
The interrupt addresses of these interrupts are like below −
Interrupt Enable (IE)Register:
 This register can be used to enable or disable interrupts programmatically.
 This register is an SFR.
 The address is A8H.
 This byte is bit addressable.
 So it can be programmed by the user.
 The bits in this register has a different meaning.
Now, let us see the bit details and different operations when the value is low (0) and
high(1).
Example: Show the instructions to (a) enable the serial interrupt, Timer 0 interrupt,
and external hardware interrupt 1 (EX1), and (b) disable (mask) the Timer 0 interrupt,
then (c) show how to disable all the interrupts with a single instruction.
Solution:
(a)MOV IE,#10010110B ;enable serial, Timer 0, EX1
Since IE is a bit-addressable register, we can use the following instructions to access
individual bits of the register.
(b)CLR IE.1 ;mask(disable) Timer 0 interrupt only
(c)CLR IE.7 ;disable all interrupts
Another way to perform the “MOV IE,#10010110B” instruction is by using single-bit
instructions as shown below.
SETB IE.7 ;EA=1, Global enable
SETB IE.4 ;enable serial interrupt
SETB IE.1 ;enable Timer 0 interrupt
SETB IE.2 ;enable EX1
Interrupt Priority (IP) Register:
 All of these five interrupts can be in one or two interrupt level.
 The priority levels are level 1 and level 0.
 Priority level 1 indicates the higher priority, and level 0 indicates lower priority.
 This IP register can be used to store the priority levels for each interrupt.
 This is also a bit addressable SFR.
 Its address is B8H.
Now, let us see the bit details and different operations when the value is low (0) and
high(1).
Programming Timer Interrupts
• The timer flag (TF) is raised when the timer rolls over. In polling TF, we
have to wait until the TF is raised. The microcontroller is tied down
while waiting for TF to be raised, and cannot do anything else. If the
timer interrupt in the IE register is enabled, whenever the timer rolls
over, TF is raised. This avoids tying down the controller.
• The microcontroller is interrupted in whatever it is doing, and jumps

to the interrupt vector table to service the ISR. In this way, the
microcontroller can do other task until it is notified that the timer has
rolled over
TF Interrupt
Programming the Serial Communication Interrupt
• TI (transfer interrupt) is raised when the last bit of the framed data, the
stop bit, is transferred, indicating that the SBUF register is ready to transfer
the next byte.
• RI (received interrupt) is raised when the entire frame of data, including
the Stop bit, is received.
• In the 8051 there is only one interrupt set aside for serial communication
This interrupt is used to both send and receive data.
If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is raised the 8051
gets interrupted and jumps to memory location 0023H to execute the ISR.
In that ISR we must examine the TI and RI flags to see which one caused the
interrupt and respond accordingly.
• The serial interrupt is used mainly for receiving data and is never used for
sending data serially.
This is like getting a telephone call in which we need a ring to be notified
If we need to make a phone call there are other ways to remind ourselves
and there is no need for ringing.
However in receiving the phone call, we must respond immediately no
matter what we are doing or we will miss the call.
• The TCON register holds four of the interrupt flags, in the 8051 the
SCON register has the RI and TI flags
Programming of Hardware Interrupts- INT0 & INT1
Fig. Activation of INT0 and INT1

• In the level-triggered mode, INT0 and INT1 pins are normally high
If a low-level signal is applied to them, it triggers the interrupt.
Then the microcontroller stops whatever it is doing and jumps to the interrupt
vector table to service that interrupt.
The low-level signal at the INT pin must be removed before the execution of
the last instruction of the ISR, RETI; otherwise, another interrupt will be
generated.
• This is called a level-triggered or level-activated interrupt and is the default
mode upon reset of the 8051
• To make INT0 and INT1 edge-triggered interrupts, we must program the bits
of the TCON register.
The TCON register holds, among other bits, the IT0 and IT1 flag bits that
determine level- or edge-triggered mode of the hardware interrupt.
IT0 and IT1 are bits D0 and D2 of the TCON register.
They are also referred to as TCON.0 and TCON.2 since the TCON register is
bit addressable.
• In edge-triggered interrupts, The external source must be held high for at

least one machine cycle, and then held low for at least one machine cycle

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8051 Interrupts

• The microcontroller is interrupted in whatever it is doing, and jumps

Fig. Activation of INT0 and INT1

• In edge-triggered interrupts, The external source must be held high for at

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